Progress on Design of Module for Track Triggering

Progress on Design of Module for Track Triggering

A. MarchioroCERN

October 2009

A.Marchioro / Oct 2009 2

Outline

• Recap of the proposed architecture• Details of interconnect for module• Logic for Trigger Primitives• The simulation (hardware simulation!)

environment• Plans


Layout model

Red Modules: Trigger LayersGreen Modules: Outer Layers

100

cm


Measuring transverse momentum (pT)

OK, small bend

Not OK, too large bend


6*(7

.2 +

.8) m

m

3*16 mm + 12 mm

Module Layout

F

Z

Pixelized ASICfor Track Triggering

Integration

Optical Link,Powering,Passives,

Auxiliary etc.


250um150 um100 um800 um100um150 um250 um7.2 mm

TFEA

ROA

Substrate

16 mm

6 x (7.2 + 0.8) mm

AUX

Module size = [6 * 8] x [3 * 16 + 12] mm

…

…

7.2 mm

TFEA

Base Option: WB + BB

F

r

Z

r


250um150 um100 um2*400 + 400um100um150 um250 um

7.2 mm

TFEA

ROA

Substrate 1

16 mm

6 x (7.2 + 0.8) mm

AUX

Module size = [6 * 8] x [3 * 16 + 12] mm

…

7.2 mm

TFEA

Base Option++: WB & BB

Substrate 2Cooling

Kapton connection


Stacking in Commercial Devices


Sensor 250umC4 100 umASIC 100 umC4 100 umSubstrate 700 umC4 100 umASIC 100umC4 100 umSensor 250 um

8.0 mm

ROA

Substrate

16 mm

6 x (8.0) mm AUX

Module size = [6 * 8] x [3 * 16 + 10] mm

…

Advanced Option: TSV & BB

…

TSVZ

r

F

r


Front-End to Opto-link connectivity

Opto to Trigger• 18 chips/side• 18 inputs to Opto-link

– Only master provide trigger info

• Synchronous decision 10+5 ??? bit/chip @ 40 MHz to

• Overhead per module: 8 bit• Total BW/ MCM = 10 * 18 *

40 MHz = 10.8 Gbit/sec


…

16 mm

7.2

mm

ASIC size:7.2 x 16 mm2Strip size: ~ 100 um x 2000 umChannel size: 100um x 1750um# channels: 160 x 4 = 640 channelsTotal BW required for trigger: 25.6 Gbit

Pixel Cells

Periphery

FE chip floorplan


Single Channel size: 100 x 1750 um

Analog circuit: 100 x 750 um2

Bias, Dacs etc: 100 x 200 um2

Bump-bond pad: 90 x 90 um2

Event Memory depth: 6 usec-> memory length: 40 x 6 ~ 256 bits-> cell size: 2.1 um2 -> block size: 750 um2 ~ 28x28 um2 (rounded to 100x100 um2)

Coincidence logic: Lookup SRAM-> 100x100 um2

Read-Out Logic: 80 x 80 um2Channel Configuration regs: 100 x 100 um2

DACs

Anal

og F

ECo

inci

denc

e

SRAM

Pixel block Floorplan

DACs

Anal

og F

ECo

inci

denc

e

SRAM

R-O R-O

DACs

Anal

og F

ECo

inci

denc

e

SRAM

DACs

Anal

og F

ECo

inci

denc

e

SRAM

R-O R-O

DACs

Anal

og F

ECo

inci

denc

e

SRAM

DACsAn

alog

FE

Coin

cide

nce

SRAM

R-O R-O

DACs

Anal

og F

ECo

inci

denc

e

SRAM

DACs

Anal

og F

ECo

inci

denc

e

SRAM

R-O R-O

Configuration

Shared Routing and Logic

Shared Logic and Routing


Functional block diagram

FE

Ev StoreDataLink

TriggerLinkTrigger

Logic

Pixel BlockU

pper

Lay

erLo

wer

Lay

er

Local TriggerLink

FE

Ev StoreDataLink

TriggerLinkTrigger

LogicLocal TriggerLink

CLK & Cntrl

CLK & Cntrl

ActiveInactive


To encode or not-to-encode?

Hit Occupancy (%)


Sensor to FE chip Z-pitch adaptation

(for WB option)

2 mm

1.80 mm

Sensor

FE-chip

Z

r

7.20 mm

8.00 mm


Simple Trigger Logic Algorithm

• Step 1: – Elimination of large clusters

• Step2:– Z alignment

• Step 3:– Coincidence between planes


Step 1: Rejection of large clusters

- All these combinations to be eliminated before transferring pattern to master layer.- Algorithm for clean-up:

if any pixel has more than one neighbor turned on in a + - 1 vicinity, all are turned off


Step 1: Implementation

Local clusterlogic

…8 neighbors from same plane

“this” hit

Hit

For each pixel hit:- Look in all adjacent pixels

for clusters of at least 3 pixels- eliminate all clusters of 3 or more


Step 2: 2+2mm strips Simplified Z alignment

Upper plane

Lower plane

Z

r

Notice:Maximum Z shift for 2 mm spacing: ~ 11 mm at h=2.5 but only some connections shows


Step 2’: Z alignment with (some) details Upper plane

Lower plane

Z

r

Maximum Z shift for 2 mm spacing: ~ 11 mm at h=2.5

21

Step 2 (option): Z alignment with (some) details

A.Marchioro / Oct 2009

Upper plane

Lower planeZ

r

Maximum Z shift for 2 mm spacing: ~ 11 mm at h=2.5

f f f f f f f f f f

f


Connectivity per module (high granularity, 1’)

• Each MCM has 18 chips per side , i.e. 3 rows of 6

• Assuming that each chip with 640 pixels multiplexes one column of four pixels into one line, then:– For each column:

• First 4 rows of chips have 3 inputs • Fifth row of chips has 2 inputs• Sixth row of chips has 1 input

– Total connectivity per Z-column: 17 lines• Total module connectivity: 17*480=8,160 lines


Step 3: coincidence between planesEach pixel in the lower planereceives the “image” of the 9 adjacent pixel in the upper plane

Local trigger

logic

…9 neighbors from upper plane

“this” hit

Hit

F

Z


Step 3, other option: coincidence between planes

If matching at low pT necessary,one could imagine an asymmetric mask pattern, say 5x2

Local trigger

logic

…10 neighbors from upper plane

“this” hit

Hit

F

Z


Connectivity on modules

• If projection from –Z is also necessary, the connectivity problem gets only worse!


Inter-Module Links• Chip to chip link on MCM

– 160 (4:1 mux) CMOS drivers per chip working at 160 bit/s max– ~50 mm length– Driving level: 1 V – Capacitance on line: 3-4 pF

• Chip to Opto– 1 CMOS driver per chip working at 40 Mbit/s– 100 mm length <avg>– Driving level: 1 V– Capacitance on line: 4-8 pF

• Chip to Data– LV-LVDS– 4 mW per driver– 1 m length


HW (Simulated) vs Software event filtering

Events from M. Pesaresi’s or equiv M.C.

Classical MC Filter

Comparison of decisions

(Python)

Verilog Model

Conversion to Verilog

vectors

Conversion backwards

(Verilog)

(Python)


Step 1: Event from MCEvent:2Module Position(r,phi,z) : 25.2684 : 0.901326 : -0.19High28 28 12164 0.2437442 36 18855 0.5733193 66 30925 0.1634323 67 30925 0.1634323 68 30925 0.16343225 89 19225 1.2367428 93 16268 0.42448721 98 34681 0.17038220 99 34681 0.17038220 100 34681 0.17038216 167 22324 0.2360072 192 37920 0.21092218 192 21067 0.9196572 193 37920 0.2109228 193 0 5016 203 25168 0.70314726 216 21064 0.51838820 222 20445 0.174685Low28 20 12164 0.2437443 34 30925 0.1634323 35 30925 0.1634323 36 30925 0.16343215 60 50120 0.14262515 61 50120 0.14262515 62 50120 0.14262515 63 50120 0.14262515 64 50120 0.14262515 65 50120 0.14262515 66 50120 0.14262521 75 34681 0.17038221 76 34681 0.17038224 87 19225 1.2367428 89 16268 0.42448716 175 22324 0.2360072 182 37920 0.21092218 190 21067 0.9196577 193 0 5020 198 22033 0.49365119 199 20445 0.17468519 200 20445 0.17468516 205 25168 0.703147End


Step 2: Conversion to Verilog

30

Step 3: Verilog Model

A.Marchioro / Oct 2009

module pixel (TriggerOut, ClusterRejectOut, PixelUpOut, LocalHitOut, CleanPixelOut

, SerialConfOut, ConfCkOut, Ck, ConfCkIn, SerialConfIn, Reset, MasterSlave

, PixelUpIn, LocalHitIn, AdjPixelsUp, AdjLocalHits, AdjClusterRejects);

input Ck; //clockinput LocalHitIn; //local pixel value input Reset, MasterSlave;input SerialConfIn; //serial input of configuration logicinput ConfCkIn; //clock for configuration logicinput PixelUpIn; //value of the pixel from the upper planeinput [7:0] AdjPixelsUp; //adjacent pixel to pixelUp in the upper planeinput [7:0] AdjLocalHits; //adjacent pixel to localHit (for cluster reject logic in upper/slave plane)input [7:0] AdjClusterRejects; //cluster reject signals from adjacent pixel of the planeoutput TriggerOut, ClusterRejectOut;output PixelUpOut;output LocalHitOut;output CleanPixelOut; //pixel to transfer from upper/slve plane to lower/master planeoutput SerialConfOut; //serial output of configuration logicoutput ConfCkOut;

reg PixelUpOut;reg LocalHitReg;


Step 3’: Verilog Modelpixel pixel12 (TriggerOut[12], ClusterRjectOut12, PixelUpOut12, LocalHitOut12, CleanPixelOut12, SerialConfOut12, ConfCkOut12, Ck, ConfCkOut11, SerialConfOut11, Reset, MasterSlave, PixelUpIn12, LocalHitIn[12], {3'b000,PixelUpOut11,PixelUpOut13,PixelUpOut171,PixelUpOut172,PixelUpOut173}, {3'b000,LocalHitOut11,LocalHitOut13,LocalHitOut171,LocalHitOut172,LocalHitOut173}, {3'b000,ClusterRejectOut11,ClusterRejectOut13,ClusterRejectOut171,ClusterRejectOut172,ClusterRejectOut173});pixel pixel13 (TriggerOut[13], ClusterRjectOut13, PixelUpOut13, LocalHitOut13, CleanPixelOut13, SerialConfOut13, ConfCkOut13, Ck, ConfCkOut12, SerialConfOut12, Reset, MasterSlave, PixelUpIn13, LocalHitIn[13], {PixelUpOut-148,PixelUpOut-147, PixelUpOut-146,PixelUpOut12,PixelUpOut14,PixelUpOut172,PixelUpOut173,PixelUpOut174}, {LocalHitOut-148,LocalHitOut-147,LocalHitOut-146,LocalHitOut12,LocalHitOut14,LocalHitOut172,LocalHitOut173,LocalHitOut174}, {ClusterRejectOut-148,ClusterRejectOut-147,ClusterRejectOut-146,ClusterRejectOut12,ClusterRejectOut14,ClusterRejectOut172,ClusterRejectOut173,ClusterRejectOut174});pixel pixel14 (TriggerOut[14], ClusterRjectOut14, PixelUpOut14, LocalHitOut14, CleanPixelOut14, SerialConfOut14, ConfCkOut14, Ck, ConfCkOut13, SerialConfOut13, Reset, MasterSlave, PixelUpIn14, LocalHitIn[14], {PixelUpOut-147,PixelUpOut-146, PixelUpOut-145,PixelUpOut13,PixelUpOut15,PixelUpOut173,PixelUpOut174,PixelUpOut175}, {LocalHitOut-147,LocalHitOut-146,LocalHitOut-145,LocalHitOut13,LocalHitOut15,LocalHitOut173,LocalHitOut174,LocalHitOut175}, {ClusterRejectOut-147,ClusterRejectOut-146,ClusterRejectOut-145,ClusterRejectOut13,ClusterRejectOut15,ClusterRejectOut173,ClusterRejectOut174,ClusterRejectOut175});pixel pixel15 (TriggerOut[15], ClusterRjectOut15, PixelUpOut15, LocalHitOut15, CleanPixelOut15, SerialConfOut15, ConfCkOut15, Ck, ConfCkOut14, SerialConfOut14, Reset, MasterSlave, PixelUpIn15, LocalHitIn[15], {PixelUpOut-146,PixelUpOut-145, PixelUpOut-144,PixelUpOut14,PixelUpOut16,3'b000}, {LocalHitOut-146,LocalHitOut-145,LocalHitOut-144,LocalHitOut14,LocalHitOut16,3'b000}, {ClusterRejectOut-146,ClusterRejectOut-145,ClusterRejectOut-144,ClusterRejectOut14,ClusterRejectOut16,3'b000});


Conclusion and Outlook• Moderately aggressive technological choices with predictable

cost• Interconnect technology discussed with two potential vendors:

– No major show-stopper identified• “Consider” splitting the substrate in two halfs• But connectivity for Z-alignment must be kept “reasonable”

• Verilog model of entire Front-End Trigger Logic and interconnectivity being developed:– ready by end of year– Physics events to validate model and estimate efficiency are then

necessary • Evaluation of 90 nm CMOS technology and design of basic

building blocks has started


Thank you!

Documents

Progress on Design of Module for Track Triggering