Prof. Joongho Choi

CMOS DYNAMIC LOGIC DESIGN

Integrated Circuits

Spring 2001

Dept. of ECE

University of Seoul

Prof. Joongho Choi

Dynamic Logic Motivation

Complementary CMOS Logic

VOH=VDD, VOL=GND

No Static Power Dissipation

For Fan-In of N, (2N) Transistors Required

Series Network Unavoidable

pseudo-nMOS Logic

For Fan-In of N, (N+1) Transistors Required

Series Network Avoidable

VOLGND

Static Power Dissipation

Dynamic Logic Combination of Two Design Approaches

Prof. Joongho Choi

Basic Principle – n Network

CLK=L [PRECHARGE] MN OFF : Y can’t go down to GND

MP ON : Y prechaged to VDD

CLK=H [EVALUATION] MP OFF

MN ON

Y can go down to GNDor

stay at VDD

according to PDN evaluation.

M P

V DD

M N

Y

C

A

B

CLK

CLK

PDN

Prof. Joongho Choi

M P

V DD

M N

Y

C

A

B

CLK

CLK

Basic Principle – p Network

CLK=L [PRECHARGE] MP OFF : Y can’t go up to VDD

MN ON : Y prechaged to GND

CLK=H [EVALUATION] MN OFF

MP ON

Y can go up to VDD

or stay at GNDaccording to PUN evaluation.

PUN

Prof. Joongho Choi

n Network – Operation

EVALUATION

M P

V DD

M N

Y

C

A

B

CLK

CLK

M P

V DD

M N

Y

C

A

B

CLK

CLK

CLK

Y

PRECHARGE

M P

V DD

M N

Y

C

A

B

CLK

CLK

CLK

Y

CABY

Prof. Joongho Choi

n Network – Characteristics

Logic – PDN consists of nMOS Transistors

Number of Transistors: N+2

Faster Switching Speed due to Reduced # of Transistors

Ratioless Logic: VOH=VDD, VOL=GND

No Static Power Dissipation, Only Dynamic Power Dissipation

Reduced Noise Margin (NML)

CABY

CLK

A

B

Y Y

A,BV THN

VIL, VIH & VM

Prof. Joongho Choi

n Network – Example

4-Input NAND Waveform

0.00e+00 2.00e-09 4.00e-09 6.00e-09t (nsec)

0.0

2.0

4.0

6.0

Vou

t (V

olt)

Vout

PRECHARGEEVALUATION

tpHL

How about tpLH? tpLH=0!!

Prof. Joongho Choi

M P

V DD

M N

Y

A

CLK

CLK

CLK

Y0

C L V DD

0

T/2

n Network Problem – Leakage Current

ILK = IRD (Reverse-Biased Diode) + IWI (Weak-Inversion)

For Proper Logic Operation, VDD-VLK > VIH

IRD

IWIV LK

L

LKLK C

2TIV

Prof. Joongho Choi

Leakage Current Example

ILK= 10nA (for example)

CL= 32.75fF (pp. 133 in

textbook)

Leakage Ripple

High Voltage @ Y

VIH for Inverter

VIH=2.92V (pp. 128 in

textbook)

LKLKDDYOH V5VVV

M P

V DD

M N

YA

CLK

CLK

0X

5.2/1.2

1.8/1.2

V DD

15

9

L

LKLK

1075.32

2T1010C

2TIV

kHz 2.734f sec 62.13T

Prof. Joongho Choi

n Network Problem – Charge Sharing

Before A Rising,

After A Rising,

Charge Sharing Ripple

M P

V DD

Y

B

CLK

CLK

CLK

Y

C L

V DD

0A

A

B

0CVCQ ADDL1

YAL2 VCCQ DD

AL

LY V

CCC

V

DDAL

AYDDCS V

CCC

VVV

ON

C A

C BV CS

Prof. Joongho Choi

Solution - Charge Sharing Problem

Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl

(b) Precharge of internal nodes

(a) Static bleeder

Prof. Joongho Choi

n Network Problem – Clock Feedthrough

Mp

Me

VDD

Out

A

B

CL

Ca

Cb

Ma

Mb

X

5V

overshoot

out

could potentially forwardbias the diode

0 1 2 3

t (nsec)

0

2

4

6

V (

Vol

t)

out

internal node in PDN

output without redistribution (Ma off)

feed

thro

ugh

might forward-bias PN junction

Prof. Joongho Choi

n Network Problem – Cascading

Ideally, Y = NOT(X) = NOT(NOT(A)) = A = “H”

Non-Zero Falling Time @ X-node Y-node Also Falling

until X-node reaches VTHN

Basic Problems: Outputs Precharged to VDD & They drives nMOSFET.

V DD

A

CLK

CLK

V DD

CLK

CLK

YX

V DD

CLK

Y

X

A

0

V THN

Prof. Joongho Choi

DOMINO Logic

Solve Problem of Cascading

But Still Dynamic Logic Leakage, Charge Sharing, Clock Feedthrough

Can’t Make Inverting Logic such as NAND, NOR, …

Very High Speed Operation Achievable

V DD

IN 1

CLK

CLK

PDN 1

V DD

IN 2

CLK

CLK

PDN 2

Y 1

V DD

IN 3

CLK

CLK

PDN 3

Y 2 Y 3

H H H

Prof. Joongho Choi

ZIPPER LogicV DD

IN 1

CLK

CLK

PDN 1

V DD

IN 2

CLK

CLK

PUN 2

V DD

IN 3

CLK

CLK

PDN 3

Y 2

Y 3

Y 1H H

L

nMOS

pMOS

nMOS

Precharged to VDD (GND) Drives pMOS (nMOS) Logic

Speed Unbalance between PDN (nMOS) & PUN (pMOS)

Higher Speed Than Domino Due to Lack of Inter-stage Inverters

DEC Alpha Processor

Prof. Joongho Choi

CMOS Logic Comparison