Product Specification · 2018. 1. 19. · Segment 127 (Row 128 ) Segment 126 ( Row 127 ) Segment 0 ( Row 1 ) Common 95 ( Column 64 ) Common 32 ( Column 1 ) Pixel Detail Scale (10:1)

Product Specification

Part Name : OEL Display ModuleCustomer Part ID :TOPWIN Part ID : VG-6428TSWAG03 Doc No. : SAS1-1G004-A

Customer:

Approved by

From: Topwin Semiconductor Inc. Approved by

RReevviisseedd HHiissttoorryy

Part Number Revision Revision Content Revised on

VG-6428TSWAG03 A New November 18, 2015

UCCoonntteennttss

RReevviissiioonn HHiissttoorryy ................................................................................................................................i

CCoonntteennttss...........................................................................................................................................ii

11.. BBaassiicc SSppeecciiffiiccaattiioonnss................................................................................................................1~3

1.1 Display Specifications ....................................................................................................................1

1.2 Mechanical Specifications...............................................................................................................1

1.3 Active Area / Memory Mapping & Pixel Construction ........................................................................1

1.4 Mechanical Drawing.......................................................................................................................2

1.5 Pin Definition ................................................................................................................................3

22.. AAbbssoolluuttee MMaaxxiimmuumm RRaattiinnggss ........................................................................................................4

33.. Optics & EElleeccttrriiccaall CChhaarraacctteerriissttiiccss .......................................................................................5~10

3.1 Optics Characteristics ....................................................................................................................5

3.2 DC Characteristics .........................................................................................................................5

3.3 AC Characteristics .........................................................................................................................6

3.3.1 4-wire SPI interface Timing Characteristics ...........................................................................6

3.3.2 I2C interface Timing Characteristics......................................................................................8

3.3.3 Reset Timing Characteristics ................................................................................................9

44.. FFuunnccttiioonnaall SSppeecciiffiiccaattiioonn.....................................................................................................10~13

4.1 Commands ................................................................................................................................. 10

4.2 Power down and Power up Sequence ........................................................................................... 10

4.2.1 Power up Sequence........................................................................................................... 10

4.2.2 Power down Sequence ...................................................................................................... 10

4.3 Reset Circuit ............................................................................................................................... 10

4.4 Application Circuit ....................................................................................................................... 11

4.4.1 4-wire SPI interface Timing Characteristics ......................................................................... 11

4.4.2 I2C interface Timing Characteristics.................................................................................... 12

4.5 Actual Application Example .......................................................................................................... 13

55.. RReelliiaabbiilliittyy ..................................................................................................................................15

5.1 Contents of Reliability Tests ......................................................................................................... 15

5.2 Failure Check Standard ................................................................................................................ 15

66.. OOuuttggooiinngg QQuuaalliittyy CCoonnttrrooll SSppeecciiffiiccaattiioonnss............................................................................16~20

6.1 Environment Required ................................................................................................................. 16

6.2 Sampling Plan ............................................................................................................................. 16

6.3 Criteria & Acceptable Quality Level ............................................................................................... 16

6.3.1 Cosmetic Check (Display Off) in Non-Active Area................................................................. 16

6.3.2 Cosmetic Check (Display Off) in Active Area........................................................................ 18

6.3.3 Pattern Check (Display On) in Active Area........................................................................... 19

77.. PPaacckkaaggee SSppeecciiffiiccaattiioonnss..............................................................................................................20

88.. PPrreeccaauuttiioonnss WWhheenn UUssiinngg TThheessee OOEELL DDiissppllaayy MMoodduulleess .......................................................21~23

8.1 Handling Precautions ................................................................................................................... 21

8.2 Storage Precautions..................................................................................................................... 21

8.3 Designing Precautions ................................................................................................................. 22

8.4 Precautions when disposing of the OEL display modules ................................................................ 22

8.5 Other Precautions........................................................................................................................ 22

WWaarrrraannttyy ........................................................................................................................................23

NNoottiiccee.............................................................................................................................................23

11.. BBaassiicc SSppeecciiffiiccaattiioonnss

1.1 Display Specifications

1) Display Mode : Passive Matrix

2) Display Color : Monochrome (White)

3) Drive Duty : 1/64 Duty

1.2 Mechanical Specifications

1) Outline Drawing : According to the annexed outline drawing

2) Number of Pixels : 128 × 64 3) Module Size : 14.00 × 43.80 × 1.20 (mm) 4) Panel Size : 14.00 × 28.00 × 1.20 (mm) including “Anti-Glare Polarizer” 5) Active Area : 10.86 × 21.74 (mm) 6) Pixel Pitch : 0.17 × 0.17 (mm) 7) Pixel Size : 0.15 × 0.15 (mm) 8) Weight : T.B.D. (g) ± 10%

1.3 Memory Mapping & Pixel Construction

Segment 1( Row 2 )

Segment127(Row 128 )

Segment 126( Row 127 )

Segment 0( Row 1 )

Common 95( Column 64 )

Common 32( Column 1)

Pixel DetailScale (10:1)

0.150.17

0.1

50.

17

Driver IC Memory Mapping( 128 x 64 in 128x 128 )

Notes:

1. Color: White2. Driver IC: SH11073. FPC Number: UT-0607-P044. Interface:4-wire SPI , I2C5. General Tolerance: ±0.306. The total thickness (1.3 Max) is without polarizer protective film & remove tape. The actual assembled total thickness with above materials should be 1.55 Max.

Topwin Semiconductor Inc.

VG-6428TSWAG03 Folding Type OEL Display Module Pixel Number: 64 x 128, Monochrome, COG Package

±0.3

mm

Unless Otherwise Specified

Unit

Tolerance

AngleDimension

General Roughness

Title

Date

ByDrawn

Drawing Number

1 of 1Sheet

Material

Panel / E.E.E.

1:1Scale

A3Size

DateItem Remark

Rev.

Soda Lime / Polyimide

Customer ApprovalSignature

±1

ADMX6428SDGF04

Fanny Shen

A Original Drawing

P.M.

20151117

8

CS

Symbol

NC

2

5

76

43

1Pin

910

RES

IREF

VDD

1213

11

VCOM

D0

VPP

D1

NC

P0.17x64-0.02=10.86 (A/A)

P0.1

7x1

28-0

.02=

21

.74

(A/A

)

11.86 (V/A)

22.74

(V/A

)

14±0.2 (Panel Size)

28

±0.2 (Pan

el Size)

14±0.2 (Cap Size)

25

.2±0

.2 (C

ap S

ize)

13±0.5 (Polarizer)

24.2±0

.5 (P

olarizer)

0.5±0.5(1.07)(1.57)

(1.6)(1.1)

0.5±0.5

(43.8

)

1.2±0.1

0.1

Glu

e

9.3±0.215.8±0

.3

(2.35)

Pixel DetailScale (10:1)

0.150.17

0.15

0.17

Pro

tect

ive

Tap

e1

1(5)

x8x0

.05m

m

Tom Chang Jamie Chen Tiffany Hsu

Segment 1( Row 2 )

Segment127(Row 128 )

Segment 126( Row 127 )

Segment 0( Row 1 )

Common 95( Column 64 )

Common 32( Column 1)

(10)

(5)

(8) R

emov

e T

ape

t=0

.15

mm

Max

Po

lari

zer

t=0.

2m

m

VSS

Active Area 0.96"64 x 128 Pixels

IM1

A01.8±0.3

5±0.24±0.2

W=0.4±0.05P0.7x(13-1)=8.4±0.05

1 13

2-φ1

.0±0.1

12.4±0.2C

onta

ct S

ide

Co

ntac

t S

ide

20151117

2.35±0.3

10.4±0.1

2±0.2

1±0.2

20151117 20151117 20151117

ThinkPad图章

1.5 Pin Definition

Pin Number Symbol I/O Function

PPoowweerr SSuuppppllyy

2 VPP P PPoowweerr SSuuppppllyy ffoorr OOEELL PPaanneell

This is the most positive voltage supply pin of the chip. It must be supplied

externally.

4 VDD P PPoowweerr SSuuppppllyy ffoorr LLooggiicc

This is a voltage supply pin. It must be connected to external source.

12 VSS P

GGrroouunndd ooff OOEELL SSyysstteemm

This is a ground pin. It also acts as a reference for the logic pins, the OEL

driving voltages, and the analog circuits. It must be connected to external

ground.

DDrriivveerr

3 VCOMH O VVoollttaaggee OOuuttppuutt HHiigghh LLeevveell ffoorr CCOOMM SSiiggnnaall

This pin is for the voltage output high level for COM signals. A capacitor should

be connected between this pin and GND.

6 IREF O CCuurrrreenntt RReeffeerreennccee ffoorr BBrriigghhttnneessss AAddjjuussttmmeenntt

This pin is segment current reference pin. A resistor should be connected

between this pin and GND. Set the current at 15.625µA maximum.

IInntteerrffaaccee

5 IM1 I

CCoommmmuunniiccaattiinngg PPrroottooccooll SSeelleecctt

These pins are MCU interface selection input. See the following table:

IM1

4-wire SPI 0

I2C 1

7 CS I CChhiipp SSeelleecctt

This pin is the chip select input. The chip is enabled for MCU communication

only when CSB is pulled low.

8 RES I PPoowweerr RReesseett ffoorr CCoonnttrroolllleerr aanndd DDrriivveerr

This pin is reset signal input. When the pin is low, initialization of the chip is

executed.

9 A0 I

DDaattaa//CCoommmmaanndd CCoonnttrrooll

This pin is Data/Command control pin. When the pin is pulled high, the input at

D7~D0 will be interpreted as display data. When the pin is pulled low, the input

at D7~D0 will be transferred to the command register.

When the pin is pulled high and serial interface mode is selected, the data at SI

will be interpreted as data. When it is pulled low, the data at SI will be

transferred to the command register. In I2C mode, this pin acts as SA0 for slave

address selection.

For detail relationship to MCU interface signals, please refer to the Timing

Characteristics Diagrams.

10, 11 D0, D1 I/O

SSeerriiaall DDaattaa IInnppuutt//OOuuttppuutt aanndd cclloocckk

When serial mode is selected, D1 will be the serial data input SI and D0 will be the

serial clock input SCL.

When I2C mode is selected, D1 be the serial data input SDA and D0 is the serial

clock input, SCL.

RReesseerrvvee

1, 13 N.C. - RReesseerrvveedd PPiinn

The N.C. pins between function pins are reserved for compatible and flexible

design.

22.. AAbbssoolluuttee MMaaxxiimmuumm RRaattiinnggss

Parameter Symbol Min Max Unit Notes

Supply Voltage for Logic VBDDB -0.3 3.6 V 1, 2

Supply Voltage for Display VBPPB 0 10 V 1, 2

Operating Temperature TBOPB -40 70 °C

Storage Temperature TBSTGB -40 85 °C 3

Life Time (150 cd/mP2P) 10,000 - hour 4

Note 1: All the above voltages are on the basis of “GND B = 0V”.

Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the

module may occur. Also, for normal operations, it is desirable to use this module under the

conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used

beyond these conditions, malfunctioning of the module can occur and the reliability of the module

may deteriorate.

Note 3: The defined temperature ranges do not include the polarizer. The maximum withstood

temperature of the polarizer should be 80°C.

Note 4: End of lifetime is specified as 50% of initial brightness reached. The reference average operation life

time at room temperature is estimated by the accelerated at high temperature conditions.

33.. OOppttiiccss && EElleeccttrriiccaall CChhaarraacctteerriissttiiccss

3.1 Optics Characteristics

Characteristics Symbol Conditions Min Typ Max Unit

Brightness LBbrB Note 4 120 150 - cd/mP2

P

C.I.E. (White) (x)

(y) C.I.E. 1931

0.25

0.27

0.29

0.31

0.33

0.35

Dark Room Contrast CR - >10,000:1 -

Viewing Angle - Free - degree

* Optical measurement taken at VBDDB = 3.0V, VBPPB = 9.0V.

Software configuration follows Section 4.5 Initialization.

3.2 DC Characteristics

Characteristics Symbol Conditions Min Typ Max Unit

Supply Voltage for Logic VBDDB 1.65 3.0 3.5 V

Supply Voltage for Display VBPPPP Note 5 8.5 9.0 9.5 V

High Level Input VIHC 0.8×VBDDB - VBDDB V

Low Level Input VILC 0 - 0.2×VBDDB V

High Level Output VOHC IBOHB = -500µA 0.8×VBDDB - VBDDB V

Low Level Output VOLC IBOLB = 500µA 0 - 0.2×VBDDB V

Operating Current for VBDDB IBDDB - 110 160 µA

Note 6 - 5.3 6.6 mA

Note 7 - 8.7 10.9 mA Operating Current for VBPPB IBPPB

Note 8 - 16.9 21.1 mA

Sleep Mode Current for VBDDB IBDD, SLEEPB - 0.1 5 µA

Sleep Mode Current for VBPPB IBPP, SLEEPB - 0.5 5 µA

Note 5: Brightness (LBbrB) and Supply Voltage for Display (VBPPB) are subject to the change of the panel

characteristics and the customer’s request.

Note 6: VBDDB = 3.0V, VBPPB = 9.0V, 30% Display Area Turn on.



* Software configuration follows Section 4.5 Initialization.

3.3 AC Characteristics

3.3.1 4-wire SPI interface Timing Characteristics:

(VDD - GND = 1.65V to 2.4V, Ta = 25°C)

Symbol Description Min Max Unit

tSCYC Serial Clock Cycle Time 500 - ns

tSAS Address Setup Time 300 - ns

tSAH Address Hold Time 300 - ns

tSDS Data Setup Time 200 - ns

tSDH Data Hold Time 200 - ns

tCSS Chip Select Setup Time 240 - ns

tCSH Chip Select Hold Time 120 - ns

tSHW Serial Clock H Pulse Width 200 - ns

tSLW Serial Clock L Pulse Width 200 - ns

tR Rise Time - 30 ns

tF Fall Time - 30 ns

(VDD - GND = 2.4V to 3.5V, Ta = 25°C)


tSCYC Serial Clock Cycle Time 250 - ns

tSAS Address Setup Time 150 - ns

tSAH Address Hold Time 150 - ns

tSDS Data Setup Time 100 - ns

tSDH Data Hold Time 100 - ns

tCSS Chip Select Setup Time 120 - ns

tCSH Chip Select Hold Time 60 - ns

tSHW Serial Clock H Pulse Width 100 - ns

tSLW Serial Clock L Pulse Width 100 - ns

tR Rise Time - 15 ns

tF Fall Time - 15 ns

3.3.2 I2C interface Timing Characteristics:

(VDD - GND = 1.65V to 3.5V, Ta = 25°C)


fSCL SCL Clock frequency DC 400 KHz

tLOW SCL clock Low pulse width 1.3 - µs

tHIGH SCL clock High pulse width 0.6 - µs

tSU:DATA Data Setup Time 100 - ns

tHD:DATA Data Hold Time 0 0.9 µs

tR SCL, SDA Rise Time 20+0.1Cb 300 ns

tF SCL, SDA Fall Time 20+0.1Cb 300 ns

Cb Capacity load on each bus line 400 pF

tSU:START Setup Time for re-START 0.6 - µs

tHD:START START Hold Time 0.6 - µs

tHD:STOP Setup Time for STOP 0.6 - µs

tBUF Bus free times between STOP and START condition 1.3 - µs

3.3.3 Reset Timing Characteristics:

(VDD - GND = 1.65V to 3.5V, Ta = 25°C)


tR Reset time - 2.0 µs

tRW Reset Low pulse width 10.0 - µs

44.. FFuunnccttiioonnaall SSppeecciiffiiccaattiioonn

4.1 Commands

Refer to the Technical Manual for the SH1107

4.2 Power down and Power up Sequence

To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include

a delay period between high voltage and low voltage power sources during turn on/off. It gives the

OEL panel enough time to complete the action of charge and discharge before/after the operation.

4.2.1 Power up Sequence:

1. Power up VBDDB

2. Send Display off command

3. Initialization

4. Clear Screen

5. Power up VBPPB

6. Delay 100ms

(When VBPP is stable)

7. Send Display on command

4.2.2 Power down Sequence:

1. Send Display off command

2. Power down VBPPB

3. Delay 100ms

(When VBPP is reach 0 and panel is completely

discharges)

4. Power down VBDDB

Note 9:

1) Since an ESD protection circuit is connected between VBDDB and VBPPB inside the driver IC, VBPPB

becomes lower than VBDDB whenever VBDDB is ON and VBPPB is OFF.

2) VPPB should be kept float (disable) when it is OFF.

3) Power Pins (VBDDB, VPP) can never be pulled to ground under any circumstance.

4) VBDDB should not be power down before VPP power down.

4.3 Reset Circuit

When RESB input is low, the chip is initialized with the following status:

1. Display is OFF. Common and Segment are in high impedance state.

2. 128×128 Display Mode 3. Normal segment and display data column and row address mapping (SEG0 is mapped to the top line

of the display).

4. Shift register data clear in serial interface

5. Column address counter is set at 0

6. Normal scan direction of the COM outputs

7. Contrast control register is set at 80h

8. Internal DC-DC is selected

DDiissppllaayy oonn

VBDD

VVBDDDDB oonn

VVBPPPPB oonn

VBSSB/Ground

VBPP

VVBDDDDB ooffff

VBDD

DDiissppllaayy ooffff

VVBPPPPB ooffff

VBSSB/Ground

VBPP

4.4 Application Circuit

4.4.1 4-wire SPI interface

4.4.2 I2C interface

4.5 Actual Application Example

Command usage and explanation of an actual example

If the noise is accidentally occurred at the displaying window during the operation, please reset the

display in order to recover the display function.

Set Display Off

0xAE

Power Stabilized

(Delay Recommended)

Set RES# as High

(3µs Delay Minimum)

Initialized State

(Parameters as Default)

Set Contrast Control

0x81, 0x4F

Set DC/DC off

0xAD, 0x8A

Set Segment Re-Map

0xA0

Set COM Output Scan Direction

0xC0

Set Display Start Line

0xDC, 0x00

Set Display offset

0xD3, 0x60

Set Normal Display

0xA6

Set Entire Display Off

0xA4

Power up VBPPB

(100ms Delay Recommended)

Clear Screen

Set Display On

0xAF

Power up VBDDB

(RES# as Low State)

Initial Settings

Configuration

Set Display Clock Divide Ratio/Oscillator Frequency

0xD5, 0x51

Set Discharge / Pre-Charge Period

0xD9, 0x22

Set VCOM Deselect Level

0xDB, 0x35

VBDDB/VBPPB off State

Display Data Sent

Set Memory Addressing Mode

0x20

Set Multiplex Ratio

0xA8, 0x3F

Power down VBPPB

(100ms Delay Recommended)

Power down VBDDB Set Display Off

0xAE

Normal Operation VBDDB/VBPPB off State

Power down VBPPB

Set Display Off

0xAE Sleep Mode

Normal Operation

Set Display On

0xAF

Power up VBPPB

(100ms Delay Recommended) Normal Operation

Sleep Mode

55.. RReelliiaabbiilliittyy

5.1 Contents of Reliability Tests

Item Conditions Criteria

High Temperature Operation 70°C, 240 hrs

Low Temperature Operation -40°C, 240 hrs

High Temperature Storage 85°C, 240 hrs

Low Temperature Storage -40°C, 240 hrs

High Temperature/Humidity Operation 60°C, 90% RH, 120 hrs

Thermal Shock -40°C ⇔ 85°C, 24 cycles 60 mins dwell

The operational

functions work.

* The samples used for the above tests do not include polarizer.

* No moisture condensation is observed during tests.

5.2 Failure Check Standard

After the completion of the described reliability test, the samples were left at room temperature for 2

hrs prior to conducting the failure test at 23±5°C; 55±15% RH.

66.. OOuuttggooiinngg QQuuaalliittyy CCoonnttrrooll SSppeecciiffiiccaattiioonnss

6.1 Environment Required

Customer’s test & measurement are required to be conducted under the following conditions:

Temperature: 23 ± 5°C Humidity: 55 ± 15% RH Fluorescent Lamp: 30W

Distance between the Panel & Lamp: ≥ 50cm

Distance between the Panel & Eyes of the Inspector: ≥ 30cm

Finger glove (or finger cover) must be worn by the inspector.

Inspection table or jig must be anti-electrostatic.

6.2 Sampling Plan

Level II, Normal Inspection, Single Sampling, MIL-STD-105E

6.3 Criteria & Acceptable Quality Level

Partition AQL Definition

Major 0.65 Defects in Pattern Check (Display On)

Minor 1.0 Defects in Cosmetic Check (Display Off)

6.3.1 Cosmetic Check (Display Off) in Non-Active Area

Check Item Classification Criteria

Panel General Chipping Minor

X > 6 mm (Along with Edge)

Y > 1 mm (Perpendicular to edge)

X

Y

X

Y

6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)


Panel Crack Minor

Any crack is not allowable.

Copper Exposed

(Even Pin or Film) Minor Not Allowable by Naked Eye Inspection

Film or Trace Damage Minor

Terminal Lead Prober Mark Acceptable

Glue or Contamination on Pin

(Couldn’t Be Removed by Alcohol) Minor

Ink Marking on Back Side of panel

(Exclude on Film) Acceptable Ignore for Any

6.3.2 Cosmetic Check (Display Off) in Active Area

It is recommended to execute in clear room environment (class 10k) if actual in necessary.


Any Dirt & Scratch on Protective Film Acceptable Ignore for Any

Scratches, Fiber, Line-Shape Defect

(On Polarizer) Minor

W ≤ 0.1 Ignore

W > 0.1

L ≤ 2 n ≤ 1

L > 2 n = 0

Dirt, Spot-Shape Defect

(On Polarizer) Minor

Φ ≤ 0.1 Ignore

0.1 < Φ ≤ 0.25 n ≤ 1

0.25 < Φ n = 0

Dent, Bubbles, White spot

(Any Transparent Spot on Polarizer) Minor

Φ ≤ 0.5

� Ignore if no Influence on Display

0.5 < Φ n = 0

Fingerprint, Flow Mark

(On Polarizer) Minor Not Allowable

* Protective film should not be tear off when cosmetic check.

* Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2

W

L

b: Minor Axis

a: Major Axis

6.3.3 Pattern Check (Display On) in Active Area


No Display Major

Missing Line Major

Pixel Short Major

Darker Pixel Major

Wrong Display Major

Un-uniform Major

77.. PPaacckkaaggee SSppeecciiffiiccaattiioonnss

B pcs Tray with Vacuum Packing

Primary Box (L450mm x W296mm x H110mm, B wave)x C Set

Module

Tray (420mm x 285mm)

Carton Box

Carton Box(Major / Maximum: L464mm x W313mm x H472mm, AB wave)

C Set Primary Box

Label

Vacuum Packing Bag

Sponge Protective(370mm x 280mm x 20mm)

Staggered Stacking

Sponge Protective

x 1 pcs (Empty)

x A pcs

Wrapped with Adhesive Tapex B pcs

Item Quantity

Module TBD per Primary Box

Holding Trays (A) TBD per Primary Box

Total Trays (B) TBD per Primary Box (Including 1 Empty Tray)

Primary Box (C) 1~4 per Carton (4 as Major / Maximum)

88.. PPrreeccaauuttiioonnss WWhheenn UUssiinngg TThheessee OOEELL DDiissppllaayy MMoodduulleess

8.1 Handling Precautions

1) Since the display panel is being made of glass, do not apply mechanical impacts such us dropping

from a high position.

2) If the display panel is broken by some accident and the internal organic substance leaks out, be

careful not to inhale nor lick the organic substance.

3) If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell

structure may be damaged and be careful not to apply pressure to these sections.

4) The surface of the OEL display module is soft and easily scratched. Please be careful when

handling the OEL display module.

5) When the surface of the OEL display module has soil, clean the surface. It takes advantage of by

using following adhesion tape.

* Scotch Mending Tape No. 810 or an equivalent

Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent

such as ethyl alcohol.

Also, pay attention that the following liquid and solvent may spoil the surface becoming cloudy

without proper handling:

* Water

* Ketone

* Aromatic Solvents

6) Hold OEL display module very carefully when placing OEL display module into the system housing.

Do not apply excessive stress or pressure to OEL display module. And, do not over bend the film

with electrode pattern layouts. These stresses will influence the display performance. Also,

secure sufficient rigidity for the outer cases.

7) Do not apply stress to the driver IC and the surrounding molded sections.

8) Do not disassemble nor modify the OEL display module.

9) Do not apply input signals while the logic power is off.

10) Pay sufficient attention to the working environments when handing OEL display modules to prevent

occurrence of element breakage accidents by static electricity.

* Be sure to make human body grounding when handling OEL display modules.

* Be sure to ground tools to use or assembly such as soldering irons.

* To suppress generation of static electricity, avoid carrying out assembly work under dry

environments.

* Protective film is being applied to the surface of the display panel of the OEL display module.

Be careful since static electricity may be generated when exfoliating the protective film.

11) Protection film is being applied to the surface of the display panel and removes the protection film

before assembling it. At this time, if the OEL display module has been stored for a long period of

time, residue adhesive material of the protection film may remain on the surface of the display

panel after removed of the film. In such case, remove the residue material by the method

introduced in the above Section 5).

12) If electric current is applied when the OEL display module is being dewed or when it is placed under

high humidity environments, the electrodes may be corroded and be careful to avoid the above.

8.2 Storage Precautions

1) When storing OEL display modules, put them in static electricity preventive bags avoiding exposure

to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high

humidity environment or low temperature (less than 0°C) environments. (We recommend you tostore these modules in the packaged state when they were shipped from Topwin Semiconductor

Inc.)

At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur

with them.

2) If electric current is applied when water drops are adhering to the surface of the OEL display

module, when the OEL display module is being dewed or when it is placed under high humidity

environments, the electrodes may be corroded and be careful about the above.

8.3 Designing Precautions

1) The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module,

and if these values are exceeded, panel damage may be happen.

2) To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH

specifications and, at the same time, to make the signal line cable as short as possible.

3) We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VDD).

(Recommend value: 0.5A)

4) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring

devices.

5) As for EMI, take necessary measures on the equipment side basically.

6) When fastening the OEL display module, fasten the external plastic housing section.

7) If power supply to the OEL display module is forcibly shut down by such errors as taking out the

main battery while the OEL display panel is in operation, we cannot guarantee the quality of this

OEL display module.

8) The electric potential to be connected to the rear face of the IC chip should be as follows: SH1107

* Connection (contact) to any other potential than the above may lead to rupture of the IC.

8.4 Precautions when disposing of the OEL display modules

1) Request the qualified companies to handle industrial wastes when disposing of the OEL display

modules. Or, when burning them, be sure to observe the environmental and hygienic laws and

regulations.

8.5 Other Precautions

1) When an OEL display module is operated for a long of time with fixed pattern may remain as an

after image or slight contrast deviation may occur.

Nonetheless, if the operation is interrupted and left unused for a while, normal state can be

restored. Also, there will be no problem in the reliability of the module.

2) To protect OEL display modules from performance drops by static electricity rapture, etc., do not

touch the following sections whenever possible while handling the OEL display modules.

* Pins and electrodes

* Pattern layouts such as the FPC

3) With this OEL display module, the OEL driver is being exposed. Generally speaking,

semiconductor elements change their characteristics when light is radiated according to the

principle of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning

may occur.

* Design the product and installation method so that the OEL driver may be shielded from light in

actual usage.

* Design the product and installation method so that the OEL driver may be shielded from light

during the inspection processes.

4) Although this OEL display module stores the operation state data by the commands and the

indication data, when excessive external noise, etc. enters into the module, the internal status may

be changed. It therefore is necessary to take appropriate measures to suppress noise generation

or to protect from influences of noise on the system design.

5) We recommend you to construct its software to make periodical refreshment of the operation

statuses (re-setting of the commands and re-transference of the display data) to cope with

catastrophic noise.

Documents

Product Specification · 2018. 1. 19. · Segment 127 (Row 128 ) Segment 126 ( Row 127 ) Segment 0 ( Row 1 ) Common 95 ( Column 64 ) Common 32 ( Column 1 ) Pixel Detail Scale (10:1)