Upload
s-vivek-ramjee
View
217
Download
0
Embed Size (px)
Citation preview
7/31/2019 Processor Chips in Nokia Phones
1/30
PROCESSOR CHIPS IN NOKIA
PHONES
G.GOWSALYA 11MX11
M.LOGESWARAN 11MX24
G.PACKIYA LAKSHMI 11MX30S.ROSALINMARY 11MX41
S.VIVEK RAMJEE 11MX56
7/20/20121
7/31/2019 Processor Chips in Nokia Phones
2/30
AGENDA
7/20/20122
INTRODUCTION
FEATURES
OPERATING MODESREGISTERS
FLAGS
INSTRUCTION STYLE
7/31/2019 Processor Chips in Nokia Phones
3/30
Where is ARM?
Enabling the ARM Learning in INDIA
3
7/31/2019 Processor Chips in Nokia Phones
4/30
INTRODUCTION
ARM Advanced RISC machines.
Advances RISC Machines (now known as ARM) wasestablished as a joint venture between Acorn, Apple in
November 1990.
Used in majority of Nokia phones, Iphone, Androidseries of samsung and sony ericssions phones.
32 bit architecture.
In ARMWord-32bit
Half word-16bit
Byte-8bit7/20/20124
7/31/2019 Processor Chips in Nokia Phones
5/30
7/20/20125
INTRODUCTION
7/31/2019 Processor Chips in Nokia Phones
6/30
The ARM11 microarchitecture is the first
implementation of the ARMv6 instruction set architecture, and
forms the basis of a new family of ARM11 cores.
Improved cache architecture.
Improved exception and interrupt handling
Unaligned and mixed-endian data support
ARM's architecture is compatible with all four
major platform operating systems: Symbian OS,Palm OS,
Windows CE, and Linux.
7/20/20126
INTRODUCTION
7/31/2019 Processor Chips in Nokia Phones
7/30
FEATURES
2 different instruction sets
32 bit ARM instruction set 16 bit thumb instruction set
Simplified system design and increased code density.Can address only first 8 registers.
8bit jazelle instruction set to execute java byte code.
ARM has 37 registers.
Most instructions execute in a single cycle.
A load/store architecture .
7/20/20127
7/31/2019 Processor Chips in Nokia Phones
8/30
Instruction set extension via coprocessors
cost-sensitive embedded applications
Simple addressing modes
High Performance
Low power consumption
8-stage pipeline
7/20/20128
FEATURES
7/31/2019 Processor Chips in Nokia Phones
9/30
MEMORY AND ADDRESSING
32bit addressing, a maximum of 4GB addressed.
Memory is usually divided into 4 banks.
Cannot read or write directly from memory .
7/20/20129
7/31/2019 Processor Chips in Nokia Phones
10/30
Operating Modes
There are 7 operating modes
User mode
FIQ
IRQ
Supervisor
Abort
Undef
System
7/20/201210
7/31/2019 Processor Chips in Nokia Phones
11/30
Operating Modes
user mode - used for running general
user applications. FIQ - fast/high priority interrupts
IRQ - general purpose interrupts
7/20/201211
7/31/2019 Processor Chips in Nokia Phones
12/30
Operating Modes
Supervisor - protected mode foroperating systems
Abort - instruction prefetch halt. ie
when fetching the upcominginstructions to reduce wait times andthe fetch fails.
Undef - to handle undefinedinstruction exception handling
System - mode for operating systems7/20/201212
7/31/2019 Processor Chips in Nokia Phones
13/30
Registers
37 registers, each 32bits
1 dedicated PC
1 dedicated program status/flag register
5 dedicated saved program status registers
30 general purpose registers
7/20/201213
7/31/2019 Processor Chips in Nokia Phones
14/30
Register Organization
User
mode
r0-r7,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)r15 (pc)
cpsr
r0
r1
r2
r3
r4
r5
r6
r7
User
r13 (sp)
r14 (lr)
spsr
IRQ
User
mode
r0-r12,
r15,
andcpsr
r13 (sp)r14 (lr)
spsr
Undef
User
mode
r0-r12,
r15,
andcpsr
r13 (sp)
r14 (lr)
spsr
SVC
User
mode
r0-r12,
r15,
andcpsr
r13 (sp)
r14 (lr)
spsr
Abort
User
mode
r0-r12,
r15,
andcpsr
Note: System mode uses the User mode register set
7/20/201214
7/31/2019 Processor Chips in Nokia Phones
15/30
Program Status Registers
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carriedout
V = ALU operation
overflowed
Q flagSticky Overflow flag
J bit
J = 1: Processor in Jazelle
state
Interrupt Disable bits.
I = 1: Disables the IRQ.(
general purpose interrupt )
F = 1: Disables the FIQ. (Fastinterrupt)
T Bit
Architecture xT only
T = 0: Processor in ARMstate
T = 1: Processor in Thumb
state
Mode bits 7/20/201215
7/31/2019 Processor Chips in Nokia Phones
16/30
FlagsThese register's functions are:
Hold information about the most recentlyperformed ALU operation.
Control the enabling and disabling of interrupts.
Set the processor operating mode.
Q - You can set the Sticky Overflow, Q flag, to 1 by
executing certain multiply and fractional arithmetic
instructions. When set to 1 conditional instructionscant be executed. Q flag must be explicitly cleared.
7/20/201216
7/31/2019 Processor Chips in Nokia Phones
17/30
Condition Code Flags
The N, Z, C and V are condition code flagsmay be changed as a result of arithmetic and
logical operations in the processor
may be tested by all instructions to determine ifthe instruction is to be executed
Control Bits
The I, F, T and M[4:0]) bits will be changed when
an exception arises.If the processor is operating in a privileged mode,
they can also be manipulated by software.
Program Status Registers
7/20/201217
7/31/2019 Processor Chips in Nokia Phones
18/30
T bit:
This reflects the operating state. When this bit isset, the processor is executing in THUMB state,
otherwise it is executing in ARM state. This is
reflected on the TBIT external signal.
Note that the software must never change the
state of the TBIT in the CPSR. If this happens,
the processor will enter an unpredictable state.
Interrupt disable bits:The I and F bits are the interrupt disable
bits. When set, these disable the IRQ and
FIQ interrupts respectively.
Program Status Registers
7/20/201218
7/31/2019 Processor Chips in Nokia Phones
19/30
Mode bits:
The M4, M3, M2, M1 and M0 bits (M[4:0])
are the mode bits.These determine the processor's operating
mode.
Not all combinations of the mode bits definea valid processor mode. Only those explicitly
described shall be used.
The user should be aware that if any illegalvalue is programmed into the mode bits,
M[4:0], then the processor will enter an
unrecoverable state. If this occurs, reset
should be applied. 7/20/201219
7/31/2019 Processor Chips in Nokia Phones
20/30
Mode bits
M[4:0] MODE
10000 User
10001 FIQ
10010 IRQ
10011 Supervisor
10111 Abort
11011 Undefined
11111 System
7/20/201220
7/31/2019 Processor Chips in Nokia Phones
21/30
When the processor is executing in ARM state:
All instructions are 32 bits wideAll instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0]undefined (as instruction cannot be halfword or byte
aligned).When the processor is executing in Thumb state:
All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0]undefined (as instruction cannot be byte aligned).
When the processor is executing in Jazelle state:
All instructions are 8 bits wide
Processor performs a word access to read 4 instructions at
Program Counter
7/20/201221
7/31/2019 Processor Chips in Nokia Phones
22/30
ARM11 - Key Features
Branch prediction
Pipeline parallelism
Improved memory access
64-bits datapaths
7/20/201222
7/31/2019 Processor Chips in Nokia Phones
23/30
Pipelining
user 8 stages of Pipelining
mul & load/store or ALU/shift &
load/store can occur simultaneously.
7/20/201223
7/31/2019 Processor Chips in Nokia Phones
24/30
8 stages in normal pipeline
Fe1 Address is sent and instruction
received
Fe2 Much of the branch prediction goes
here
De Decode instruction
Iss Read registers and issue instruction
Sh Perform shift operations ALU Perform integer operations
Sat Saturate results
WB
Write back data to registers 7/20/201224
7/31/2019 Processor Chips in Nokia Phones
25/30
MP11 CPU Pipeline Stages
1st Fetch
Stage (Fe1)
Shifter
Stage (Sh)
ALU
Operation
(ALU)
Saturation
Stage (Sat)Write back
Mul/ALU
(WBex)1st multiply
acc. Stage
(MAC1)
2nd multiply
acc. Stage
(MAC2)
3rd multiply
acc. Stage
(MAC3)
Address
Generation
(ADD)
Data
cache 1
(DC1)
Data
cache 2
(DC2)
Write back
from LSU
(WBIs)
1st Fetch
Stage (Fe2)
Instruction
Decode (De)
Reg. read
and issue
(Iss)
Notes
1) To minimize power consumption, each of the MAC and ALU stages is only clocked when required.
Stage 1 Stage 2 Stage 3 Stage 8Stage 7Stage 6Stage 5Stage 4
7/20/201225
7/31/2019 Processor Chips in Nokia Phones
26/30
Instruction code style
ARM instructions can be made toexecute conditionally by post fixing
them with the appropriate condition
code field.
This improves code density and
performance by reducing the number of
forward branch instructions.
7/20/201226
7/31/2019 Processor Chips in Nokia Phones
27/30
Conditional Execution and Flags
BEQ - Branch on Equal to
-similarly Bxx Branch on xx (xx is condition)
By postfixing the EQ (equal to), NE (not equal) in other instructions perform
the job branching for single instruction without having to use 2 separate
instructions, Increasing code density.
Eg. cmp r3, #3
beq skip
add r0, r1, r2
skip:
can be coded simply as
cmp r3, #3
addne r0, r1, r2
7/20/201227
7/31/2019 Processor Chips in Nokia Phones
28/30
Subroutine
Need not stack flags/status or return addresses. It is done using the additional program
flags/status registers (spsr - stored program
status register).And return addresses are restored using the link
register (r14) to the program counter (r15).
If the program take up multiple branches thenLR has to be stacked (r13 - stack pointer).
7/20/201228
7/31/2019 Processor Chips in Nokia Phones
29/30
conclusion
7/20/201229
7/31/2019 Processor Chips in Nokia Phones
30/30
7/20/201230