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Process Introduction

Process features Key Design Rules

P substrate and P-epi Twin well LOCOS High performance bipolar devices Dual gate oxide available（optional） Low voltage CMOS(5V) High voltage CMOS(30V) High poly resistor(optional) Double metal

Device Specification

Specification Device Parameter

Min Typ Max Unit Hfe(Ic=100uA) 60 200 -

BVebo(Iebo=1uA) 11 13.6 V HV NPN

（Ae=5x7um2） BVceo(Iceo=1uA) 25 - - V

Hfe(Ic=100uA) 80 200 - BVebo(Iebo=1uA) 10 13.6 V

NPN （Ae=5x7um2）

BVceo(Ic=1uA) 9 - - V Hfe(Ic=10uA) 140 - HV LPNP

(Wb=4um ) BVceo(Ic=1uA) 50 - - V Hfe(Ic=10uA) 20 - LPNP

(Wb=4um ) BVceo(Ic=1uA) 35 - - V Vth(Vds=0.1V) 0.5 0.65 0.8 V LV-NMOS

(W/L=20/1.5) BVdss 8 12 18 V Vth(Vds=-0.1V) -0.9 -0.75 -0.6 V LV-PMOS

(W/L=20/1.5) BVdss -18 -12 -8 V Vth(Vds=0.1V) 0.9 1.3 1.7 V HV-NMOS

(W/L=50/3) BVdss 30 V Vth(Vds=-0.1V) -1.6 -1.2 -0.8 V HV-PMOS

(W/L=50/3) BVdss -30 V N+ 25 40 55 Ω/

P+ 60 80 100 Ω/ N+ Poly 18 25 32 Ω/

High-R Poly 1.6 2.0 2.4 kΩ/

Sheet Resistance

N-Well 0.8 1.1 1.4 kΩ/ Poly/N-Well(200A) 1.55 1.75 1.95 fF/um2

Capacitance Poly/N-Well(600A) 0.5 0.58 0.65 fF/um2

14 Masks Min. Width/Space(um)

Active 1.5/3

PBASE 3.0

Poly 1.5/2

Cont 1.5

M1 2/2

Via 2

M2 3/3

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Process Introduction Vertical NPN, CBE, with sink ——model name: VN5x7_D(LV)

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Process Introduction Vertical NPN, CBE, with sink ——model name: HN5x7_D(HV)

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Process Introduction Vertical NPN, Use Pwell as base, with sink Model name: WN5x7_D

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Process Introduction Circle emitter Use pbase as emitter and collector Emitter φ=7, Base width=4 Model name: LP7_4

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Process Introduction Low voltage NMOS L=1.5um~20um, W=2um~50um Model name: nl

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Process Introduction Low voltage PMOS L=1.5um~20um, W=2um~50um Model name: pl

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Process Introduction High voltage NMOS lmin=3.0um lmax=50um wmin=5um wmax=50um model name: nh nh L=3um W=50um

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Process Introduction High Voltage PMOS lmin=3.0um lmax=50um wmin=5um wmax=50um Model name: ph PH W=50um L=3um