Presentation No 05

7/31/2019 Presentation No 05

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5. CMOS Operational Amplifiers

Analog Design for CMOS VLSI Systems

Franco Maloberti


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5. CMOS Operational Amplifiers1

Analog Design for CMOS VLSI SystemsFranco Maloberti

Basic op-ampThe ideal operational amplifier is a voltage controlledvoltage source with infinite gain, infinite input impedance

and zero output impedance.

The op-amp is always used in feedback configuration.


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Typical feedback configuration

V0=V

2

Z4

Z3 + Z4

Z1+ Z

2

Z1

V1

Z2

Z1

The error due to the finite gain is proportional to 1 / A0. Thiserror must be smaller than the error due to impedance

mismatch.

V0= V

2

Z4

Z3+ Z

4

Z1+ Z

2

Z1

V1

Z2

Z1

1+

Z1+ Z

2

A0Z1

Finite gain effect:


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OTA

If impedances are implemented with capacitors and

switches, after a transient, the load of the op-amp is made

of pure capacitors. The behavior of the circuit does not

depend on the output resistance of the op-amp and stageswith high output resistance (operational transconductance

amplifiers) can be used.


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Transient

Vi(0+) =V

in

C1

C1 +C//C0

Vo (0+) =Vi(0+)

C

C0 +C

Vi(

)=

VinC1 +C

C1 +C(1+ gmr0)

Vo () = Vi() gmr0

C0

gm


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Performance characteristicsActual op-amps deviate from the ideal behavior. The

differences are described by the performance

characteristics.

DC differential gain:

It is the open-loop voltage gain measured at DC with a

small differential input signal. Typically Ad

= 80 100 dB.


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Common mode gain:

It is the open-loop voltage gain with a small signal applied

to both the input terminals. Acm

= 20 40 dB.

Common mode rejection ratio:

It is defined as the ratio between the differential gain andthe common mode gain. Typically CMRR = 40 80 dB.


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Power supply rejection ratio:

If a small signal is applied in series with the positive (or

negative) power supply, it is transferred to the output with a

given gain Aps+ (orAps-).

The ratios between differential gain and power supply gainsfurnish the two PSRRs.

Typically: PSRR = 90 dB (DC)PSRR = 60 dB (1 kHz)

PSRR = 30 dB (100 kHz)


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Input offset voltage:

In real circuits if the two input terminals are set at the same

voltage the output saturates close to VDD

or to VSS

.

Input common mode range:

It is the maximum range of the common-mode input voltagewhich do not produce a significant variation of the

differential gain.

Typically |Vos

| = 4 6 mV.


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Output voltage swing:

It is the swing of the output node without generating a

defined amount of harmonic distortion.

Equivalent input noise:The noise performances can be described in terms of an

equivalent voltage source at the input of the op-amp.

Typicallyvn= 40 50 nV/Hz at 1 kHz,in a wide band (1 MHz) it results 10 50 V RMS.


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Unity gain frequency:

It is the frequency where the open-loop gain is zero. It is

also the -3 dB bandwidth in unity-gain closed loop

conditions. Typically fT

= 200 MHz.

Phase margin:

It is the phase shift of the small-signal differential gainmeasured at the unity gain frequency. A phase margin

smaller than 60 causes ringing in the output response.


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Slew rate:

It is the maximum slope of the output voltage. Usually it is

measured in the buffer configuration. The positive slew rate

can be different from the negative slew rate. Typically SR =

50 200 V/s (lower values for micropower operation).

Settling time:

The settling time is the time required to settle the output

within a given range (usually 0.1%) of the final value.

Power dissipation:It depends on speed and bandwidth requirements.

Typically, for 3.3 V supply, it is around 1 mW.


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Typical parameters of a 0.25 m OTA

m22000Silicon areamW1Power consumption

Vpp2.2Output dynamic rangeV1.5Input common mode voltage

V3.3Supply voltage

kHz1Corner frequency

nV/Hz100Input referred noise (white)dB30PSRR @ 100 kHz

dB60PSRR @ 1 kHz

dB90PSRR @ DC

ns300Settling time: 1 V, CL

= 4 pF

V/s3Slew-rate MHz100Bandwidth

mV4-6Offset

dB40CMRR

dB80DC gainUnitValueFeature


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Basic architecture

1st gain stage

differential to single-ended converter

2nd gain stage

output stage (to reduce the output impedance)

Key requirements:

absolute stability in unity gain closed-loop conditionswhen driving maximum load.

minimum number of gain stages.


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Two-stage op-amp

Key design issues:

open-loop differential gain dc offset

power supply rejection (PSRR)


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Open-loop differential gain:

The gain is obtained by multiplying the gains of the twostages.

At low frequency the gain is inversely proportional to the

bias current.

Av =A1A2 =

gm1

(gds2 + gds4)

gm5

(gds5 + gds6)=

= 2 2npC

ox

(n + p )2

W

L

1

W

L

5

W

L

B

W

L

6

W

L

7

1IBias


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Common mode dc gain:

Applying the same signal to both inputs the circuit becomessymmetrical and can be studied considering half circuit.

ACM =ACM1ACM2 =gds72gm1

gm5gds5 + gds6

CMRR=AvACM

=

2gm1gm3gds7(gds2 + gds4)


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Offset:

The offset is composed of two terms:

systematic offset

random offset

The systematic offsetcan be reduced to zero with acareful design. A necessary condition to have zero

systematic offset, is that the currents of M5 and M6 are

equal, when the inputs are connected to the same voltage.

Assuming all the transistors in saturation this condition is:

IBias

W L( )6

W L

( )B

= IBias

W L( )7

W L

( )B

W L( )5

W L

( )3

W L( )3

W L( )6

=

1

2W L( )

7

W L( )5


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The random offsetis due to the geometrical mismatching

and process dependent inaccuracies.

Vos

= Vos1

2+

Vos2

A1

2

When we refer the offset of the second stage at the input

terminal we have to divide it by the gain of the first stage.

Since the two offsets are uncorrelated we have:

The total offset is dominated by the offset of the input

stage.


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We study the effect of a mismatch between M3 and M4:

mirror factor (1 + ) instead of 1.

IBias2

gm1Vos1

2

1+ ( ) = IBias

2+ gm2 V

os1

2

Vos1 I

1

gm1


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MOS:

I1gm1

=

VGS1 VTh2

=150300 mV

(in sub-threshold)

I1

gm1=

nVT=

nkT

q

(in saturation)

BJT:

I1gm1

26 mV

Assuming = 0.01:

Vos,BJT = 0.26 mVV

os,MOS = 1.5 3 mV


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Power supply rejection:

A signal on the positive bias line determines a modulationin the reference current, which, in turn, gives an equal

modulation of the currents in M5 and M6, if the condition of

the zero systematic offset is fulfilled.


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The spur signal v+n

affects the currents of M5 and M6.

in,6

W/ L( )6

=in,7

W/ L( )7

= CoxVGS,MB VTh( )vn+

vo,n,1 = in,totW/ L( )

6

W/ L( )B

1

2

W/ L( )5W/ L( )

7

W/ L( )4W/ L( )

B

1

gds6 + gds7

vo,n,1 = in,RefW/ L( )

6

W/ L( )B

1

gm5

b) high frequency:

a) low frequency:


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Power supply rejection at low frequency

vo,tot( )2

=

gds6 gm5(1 k+)

2gm3rds3gds5 + gds6

vn+

( )2

+

gds6 gm5k

2gm3rds3gds5 + gds6

vn( )2


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Effect of external components on PSRR


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Frequency response and

compensation

A two-stage scheme with poles in the same frequency

range needs compensation.

A single pole system is always stable. Strategy: Approach the single pole performance by

splitting the two poles apart.


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Miller capacitance moves p1 at lower frequency.

Shunt feedback moves p2 at higher frequency.

Small signal equivalent circuit for two-stage op-amp.

v0vin

= gm1R1R2gm2

sCc

1+ sR1R2gm2Cc+ s2R1R2 C1C2 + (C1 +C2)Cc[ ]

v1(g1 + sC1) + (v1 v0)sCc+ gm1vin = 0

v0(g2 + sC2)+ (v0 v1)sCc+ gm2v1 = 0


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The circuit has two poles and a zero in the right half plane.

p1

1

R1R

2gm2Cc

p2 gm2Cc

C1C2 + (C1 +C2)Cc

since in practice Cc > C1, CcC2, gm1 > 1/R1, gm2 > 1/R2 it

results:

z=gm2Cc

p1 >

1

R2C

2

Assuming p1 as dominant, the unity gain angular frequency

is:

T = p1A0 1

R1R

2gm2Cc

gm1gm2R1R2 =gm1Cc


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The locations of the second pole p2 and of the zero with

respect to T are derived by considering:

p2

T

=

gm2Cc

gm1C2

for stability > 2 to 4

z

T

=

gm2gm1

The phase shift given by the

zero is also negative and

can worsen the phase

margin. It must be located

far from the unity gain

frequency.


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ifCc> C2 and gm2 > gm1

The right half-plane worsen the phase margin.

In bipolar technology gm2 >> gm1 because the current inthe second stage is normally higher than the one in the

first stage.


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5. CMOS Operational Amplifiers30Analog Design for CMOS VLSI SystemsFranco Maloberti

In CMOS technology gm2gm1 because they are

proportional to the square root ofIand W/L; moreover,the transconductance of the input pair must be high in

order to reduce their thermal noise contribution.

In real situations the obtainable phase margin does not

guarantee stability.

Eliminating the right half-plane zero:

unity gain buffer zero nulling resistor

unity gain current amplifier

The zero is due to a signal feedforward

to a point that is 180 out of phase.


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Solution 1: Eliminate feedforward with source follower

Disadvantages:Area

Power dissipation

Actually it creates a doublet in the feedback path.

Potentially not stable.Alternative, a substrate emitter follower may be used.

(The bipolar transistor is smaller and has highergm

.)


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Solution 2: Zero nulling resistor

The zero position is pushed away with a resistance in

series with Cc.

v0vin

A01+ s Rz1/ gm2

( )Cc

1+s

p1

1+

s

p2


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The pole locations are close to the original.

The zero is moved depending on Rz.

z=1

1/ gm2 Rz

( )Cc

IfRz= 1 / gm2 the zero is moved at infinity

IfRz> 1 / gm2 the zero is located in the left half-plane

Implementation:

1

Rz

=

1

Rn

+

1

Rp


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Choose (W/L)n and (W/L)p such that:

1

Rn

= kn

W

L

n

VDD

V1

VTh

,n

( )

1

Rp= k

p

W

L

p

V1

VSS

VTh,p

( )

kn WL

n

= kp WL

p

and:

1Rz

= kn WL

n

VDD Vss VTh,n VTh,p( )

Problem: Supply sensitivity.

Since the swing of the node 1 is A2 less than the outputswing, only one transistor with supply independent bias can

be used.


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Solution 3: Unity gain current amplifier

v1(g1 + sC1) + gm1vin v0sCc = 0

v0(g2 + sC2)+ gm2v1 + v0sCc = 0


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Slew rate

For large input signal:

M1, M4 are off so the current IM7 discharges Cc through

M2. Assuming M5 able to drive the current request by Cc,

CL and IM6.

SR=

V

tmax

= IM7

Cc


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M2, M5 are off so the current IM7 mirrored by M4 charges

Cc; CL and Ccare charged by IM6. The smaller of thesetwo limits will hold:

SR+=

V+

t max

=

IM6

Cc+

CL

SR+=

V+

tmax

=

IM7

Cc

To have SR+ = SR-, a condition can be:

IM7

Cc

=

IM6

Cc+CL

Since T= gm1 / Cc, the SR is

SR=IM7

gm1

T = VGS1 VTh( )T

ForT= 2 40 106 rad/s, (VGS1 - VTh) = 300 mV, SR

75.4 V/s.


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Single stage schemes

High gain is get with a cascode scheme.

Telescopic cascode

Mirrored cascode

Folded cascode


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Telescopic cascode

DC gain A0 (gmrds)2

low power consumption

only one high impedance

node: compensated with acapacitance load (if

necessary)

low output swing reference of the input close

to the negative supply

two bias lines (VB1

, VB2

)

5 transistors in series


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Mirrored cascode

optimum input common

mode range

only 4 transistors in series

improved output swing

speed of the mirror

higher power consumption

Voutmax

= VB1max + VGS4 - Vsat

VB1max = VDD - Vsat - VGS4

Voutmax = VDD - 2Vsat

Voutmax

= VGS7 + Vsat


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Conventional folded cascode


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Modified folded cascode

(improved output swing)


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Two stage amplifier vs. single stage amplifier

Two stages:

Voltage gain less affected by resistive loading

Maximum signal swing

Less bussing of bias lines

Requires an additional capacitor for frequency

compensation

More power consumption


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Single stage:

No need for additional compensation capacitor

Lower power consumption

Better CMRR

Lower signal swing More bussing of bias lines


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Class AB op-ampsClass AB: a circuit which can have an output current which

is larger than its DC quiescent current.

Two stages amplifier with class AB second stage

M6 and M7 act as alevel shifter

M8 and M9 act as a

class AB push-pullamplifier

A2

=

gm8 + gm9

gds8 + gds9


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The quiescent current in the output stage is bias voltage

and technological variation dependent.VDD

= VGS8 + VGS6 + VGS9

neglecting the body effect:

VDD =VTh,p + 2VTh,n +2kn

LW

6

I6 +

2kn

LW

8

I8 +

2kn

LW

9

I9

Typically with VDD

= 5 V the numerator is around 1.6 V; if it

is assumed VDD = (5 0.5) V and VTh = 200 mV, itresults that the numerator can change from 0.7 V to 2.5 V;

hence, Imin

= 0.3 Inom

; Imax

= 2.5 Inom

I9 =

VDD VTh,p 2VTh,n 2

kn

L

W

6

I6

2

kn

L

W

8

+

2

kn

L

W

9


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Single stage class AB amplifier (only inverting)

In the input pair M1 and M2

operate as source followers

and drive the common gate

stage M3 and M4.

VB = VTh,n + VTh,p + Vov,n + Vov,p

forVin = 0

I1 = I2 = IBias

forVin > 0

Iout= K8,9I1 - K5,6I2

K8,9 and K5,6 mirror factors(assumed equal)


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It results:

Iout

= K8,9 (I1 - I2) = K8,9VBVin

Until I1 orI2 goes to zero, for a

largerVin, I

outincreases

quadratically with Vin.

Small signal gain:A

v= 2 G

mrout

VB

+

Vin=

VGS2+

VGS4=

VTh,n+

VTh,p+

2

kn

W

L

2

+

2

kp

W

L

4

I2

VB Vin =VGS1 +VGS3 =VTh,n +VTh,p +2

kn

W

L

3

+

2

kp

W

L

1

I1


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Gm

is the transconductance of the cross coupled input

stage

gm2 Vin VA( ) = gm4VA

VA =gm2Vin

gm2 + gm4

Iout = gm4VA =gm2gm4gm2 + gm4

Vin =GmVin

F ll diff ti l


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Fully differential op-ampsThe use of fully differential paths in analog signal

processing gives benefits on:

PSRR

dynamic range clock feedthrough cancellation

Consider an integrator and its fully differential version:

N i f th l d l k f dth h


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Noise from the power supply and clock feedthrough are

common mode signals. The output swing is doubled (Vmax+ - Vmax- = 2 Vmax).

Since the noise is unchanged, the dynamic range

improves by 6 dB.

Single ended to differential and double ended to single

ended converters are necessary

Larger area

More bussing of bias lines

Common mode feedback is necessary

Th SE/DE d DE/SE bl k i th l it d


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The SE/DE and DE/SE blocks increase the complexity and

introduce noise. The differential approach is convenient ifthe differential processor contains more than 4 stages.

The feedback around the op-amp control the difference of

the input terminal voltages and not their mean value. In turn,

there is no control on the output common mode voltage.

Fully differential two stage OTA


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Fully differential two stage OTA

A1=

1

2

gm1gds1 + gds4

1st stage with gain: two 2nd stages with gain:

A2=

gm5gds5 + gds6

Fully differential single stage OTA


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Fully differential single stage OTA

COMMON MODE FEEDBACK


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COMMON MODE FEEDBACK

continuous time

sampled data

Continuous-time common mode feedback

V is such that M1 and M2 are in the linear region;


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VB

is such that M1 and M2 are in the linear region;

(W

/L

)1 = (W

/L)2; M1 and M2 are like the parallel of twovoltage dependent resistances.

I1= C

ox

W

L

1

V+V

Th( )VDS1

2VDS

2

I2= C

ox

W

L

2

V VTh( )VDS1

2VDS

2

Iout

= I1+ I

2=1

2C

oxW

L

3

VBV

DSV

Th( )2

With a differential signal Iout

= cost

With a common mode signal: if positive, Iout increases

if negative, Iout

decreases

Fully differential folded cascode with CMFB


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Fully differential folded cascode with CMFB

Fully differential folded cascode with CMFB (2)


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Fully differential folded cascode with CMFB (2)

Problems:


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Problems:

dynamic range

linearity

Compensation of the non-linearities of the n-channel and p-

channel CMFB cell.

Sampled-data common mode feedback


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Sampled data common mode feedback

The common mode feedback operates on slowly variable

signal. It can be implemented at discrete time intervals.

The sampled data feedback is essential for low bias

voltage and low power.

linearity (mean value with

capacitors)

low power consumption

no limitation to the dynamic

range

clock signal necessary

clock feedthrough effect

Micro-power op-amps


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Micro-power op-amps Required in battery operated systems

(portable/wearable equipment: pocket calculators, PDA's, digital

cameras, ; medical equipment: pace makers, hearing aids, );

Use of MOS transistors in weak inversion;

Low current (< 10 A) low slew rate.

Av =Bgm1

gds6 + gds8=

B

nVT n + p

( )

gm =ID

nVT

gds = ID

high dc gain (Av 60 dB)

Dynamic biasing of the tail current


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y g

Basic idea:

Generate |I1 - I2| and increase the current in the differentialstage by k|I1 - I2|.

Since


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Franco Maloberti

i1i2 = gm(vin+

vin)

gm =

ID

nVT ID = IB + k i1

i2

i1 i

2= I

B+ k i

1 i

2( )vin+

vin

nVT

The current increase becomes significant when:

kvin+

vin

nVT

>1

Typical performance:

DC gain 95 dB

ft

130 kHz

SR 0.1 V/sIB

0.5 A

Itot

2.5 A

Class AB single stage with dynamic biasing


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g g y g

For maximum output swing VBIAS-p and VBIAS-n must be as

close as possible to the supply voltages.

During the slewing the current source of the output


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cascodes can be pushed in the linear region, hence loosingthe advantage of the AB operation.

The problem is solved with the dynamic biasing:

Noise


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o se

The noise of an operational amplifier is described with an

input referred voltage source vn.

The spectrum ofvn is made of a white term and 1/f term.

vn

is due to the contributions, referred to the input, of the

noise generators associated to all the transistors of the

circuit (assumed uncorrelated).


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We assume gm1 = gm2; gm3 = gm4 (we assume the noise


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source of M5 does not contribute) moreover since usuallyW1 = W2; L1 = L2; W3 = W4; L3 = L4; v2n1 = v

2n2; v

2n3 = v

2n4;

if we referv2n,out to the input, we get:

vn,out2

A1

2= vn,in

2= vn,out

2

gm12

gds2 + gds4( )2= 2 vn1

2+ gm3

2

gm12vn3

2

The contribution of the active loads is reduced by the

square of the ratio gm3/gm1

It is worth to remember that

gm = 2CoxW

LI

vn2

=

8kT

3gm+

KF

2Cox

1

WL

1

f

f

The attenuation by the factor (gm3/gm1)2 gives, for the white


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term:

vn,in,w2

= 2vn12

1+gm3gm1

= 2vn1

21+

3 W/ L( )3

1 W/ L( )

1

Where KF1 and KF3 are the flicker noise coefficient fortransistors M1 and M3. The white contribution of the active

load is reduced by choosing (W/L)input >> (W/L)load. The 1/f

noise contribution of the active load is reduced by choosing

Linput < Lload. If the above conditions are satisfied the input

noise is dominated by the input pair.

vn,in,1/ f

2= 2

KF1

1CoxW1L1

1

f1+

KF3L1

2

KF1L3

2

and for the 1/f term:

Cascode scheme:


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The noise is contributed bythe input pair and the current

sources of the cascode load.

vn,in2

= 2 vn12+

gm4gm1

2

vn42

Folded cascode scheme:


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The noise contributed by the same source as in the

cascode and by the current source M2.

vn,in2

= 2 vn12+ gm2

gm1

2

vn22+ gm5

gm1

2

vn52

Two stage op-amp: (feedforward + zero nulling comp.)


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The noise is modeled with two input referred noise sources:

one at the input of the first stage and the other at the input

of the second stage.


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In the low frequency range the noise is dominated by vn1.

In the high frequency range the noise is dominated by vn2.

Frequency response:


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The cutoff frequency is: p1 = -gm/C0

The input referred noise generator is transmitted to theoutput as a conventional input signal

The feedback network around the op-amp must be taken

into account.One stage amplifier:

Power of noise:


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We consider only the white term.

Single stage amplifier:

vn0

2= v

n

2 df

1+ s /p10

= 2 1+

( )

8

3

kT1

gm1

df

1+ 2fC0/ gm1( )

2

=

0

8

3

1+

( )

kT

C0

Two stage amplifier: we consider only the white term

contributed by the noise source of the second stage

vn22

= 2 1+ ( ) 83

kT

gm2

vn02= vn2

2 df

1+ s /p20

vn0

2=

4

31+ ( ) kT

C1+C

2

p2=

gm2C

1+C

2

Layout


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Rules:

Use poly connections only for voltage signals, never for

currents, because the offset RI 15 mV.

Minimize the line length, especially for lines connectinghigh impedance nodes.

Use matched structure (necessary common centroid).

Respect symmetries (even respect power devices).

Only straight-line transistors. Separate (or shield) the input from the output line, to

avoid feedback.

Shield high impedance nodes to avoid noise injection

from the power supply and the substrate.

Regular shapes and layout oriented design.

Stacked layout:


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Structure A:

Capacitances are

further reduced if the

diffusion area is shared

between different

transistors.

Csb =Cdb =CjbW(d+ 2xj)

Csb=

1

2Cdb=

CjbW

2 (d+

2xj)

Structure B:

Csb=

Cdb=

Cjb2W

3 (d+

2xj)

Key point: use ofequal width transistors

Transistors with arbitrary width are not allowed


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Transistors with arbitrary width are not allowed.

Placement and routing:

If we divide a transistor in

an odd number of parallel

transistors the resulting

stack has the source onone side and the drain on

the other side.

If we divide a transistor in

an even number of parts

the resulting stack has

source or drain on the twosides.

Example:


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Routing into stacks: use of comb connections or serpentineconnections.


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Example: Fully differential folded cascode.


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Presentation No 05