Preliminary Design of Calorimeter Electronics

Shudi Gu

June 2002

CsI Crystal

• 9864 CsI crystals

• 2 PIN photo diodes each crystal

• 0.8fc/MeV sensitivity

• CsI crystal resolution:

%1)(

%14

GeVEE

E

Operation Conditions & Specifications

System clock 20MHz

L1 trigger latency 3.2s

Single channel event rate ≤1KHz

Range of charge 0.5fc~1500fc

Resolution of charge (Energy) 0.16fc (200KeV)

Number of channel 9864

Integral nonlinearity 1% (before correction)

Cross talk 0.3%

Dynamic range 15Bit

Information to trigger Analogue “sum” of 8 channels

Gain adjustable on line ≤ 20% nonuniformity

Block Diagram

From DetectorPost amplifier Q Module

TestController

Fan-outTrigger

TEST, DAC

CLK

CLK

L1

VME

L1 reset

Buffer full

CLK

L1

L1 reset

Buffer full

L1

L1 reset

Buffer fullSCLK, DIN

Analog Sum

Preamplifier

Preamplifier

• Low noise charge sensitive amplifier• 1 AMP/diode, 2 AMPs/crystal• Average of 2 AMP outputs to improve S/N • Average of 2 AMPs or one of the 2 AMPs

can be selected by jumpers on Post AMP when one AMP fails

• Calibration circuit at the input• 20 wire twisted cable/Ch to Post AMP

Preamplifier Specification

Gain 1mV/fc

ENC0.16fc (80pf input capacitance)

Dynamic Range 0.5fc ~ 1500fc

Output decay time 50s

Max linear output 2V

Post Amplifier

• ½(A+B), A, B can be selected• CR-(RC)2 with pole-zero cancellation shaping, =1s• Gain adjustable with digital potentiometer• Analogue sum for trigger• Differential connection with Pre-AMP and Q module

A+BAB

CR (RC)2

From Test Controller

To Q Module

To Trigger ∑

A

B

From Preamplifier

Q Module

• 3 FADCs sample signals from 3 different gain AMPs• Delay samples with pipeline to wait for 3.2s trigger latency L1• Find peak during 2.5s after L1 arrival• Select peak, make range encoding & compression, store data in buffer• Inner trigger for radiation source calibration & adjusting gain• 9U VME module, 32ch/module

×.25 Pipeline

×1

×8

Pipeline

Pipeline

Peak Selec.Range

EncodingCompress

Peak

Peak

Peak

Buffer

From Post AMP.

FADC

FADC

FADC

Disc. Delay L1

Out. TrigInn. Trig

Thr. Register

Three Range Digitization

• Three 10Bit FADCs with 3 ranges to get 15Bit dynamic range from 0.08MeV to 2.5GeV

• Small resolution degradation due to digitization

Range Gain Full Scale Min. Energy Digital Res. CsI Res. Res. Increa.

High ×0.25 2.5Gev 0.625Gev 1.4×10-3 2.1×10-2 0.2%

Middle ×1 0.625Gev 0.078Gev 2.3×10-3 2.9×10-2 0.3%

Low ×80.078Gev

20Mev 1.1×10-3 3.7×10-2 0.04%

0.6Mev 3.5×10-2 7.3×10-2 11%

System Dynamic Range

• Dynamic range of digitization is wider than the charge measurement range

• Charge measurement precision is not infected by noise and digital resolution seriously

Noise σQ = 0.16fc200KeV

2.5GeV2000fc

75KeV0.06fcDynamic range of digitization (15Bits)

Charge measurement range

1500fc1.875GeV

0.5fc625KeV

Test Controller

• Fan out and send 20MHz clock, L1 and L1 reset from trigger system to Q modules in the same crate for collision mode

• Generate 20MHz clock, L1, DAC and Test pulse for calibration mode• Generate 20MHz clock for inner trigger mode. Test system with

radiation source• Generate 20MHz clock, serial clock and data for gain adjustment mode

1

Trigger

DelayShaping

2

3

1

2

3

1 2 3 ＋ 5V

Trigger

16bit DAC

DIN

SCLK

DAC

Test

L1

CLKAddress20MHzCrystal

FrequencyDivider

PLD

VME

1.Inner trigger2.Calibration & gain adj.3.Outer trigger

Local Buffer Readout

• Separate VME addresses and buffers for trigger number, Hit Map and data of 32 channels

• Only read channels pointed by Hit Map OR

Read all channels without compression with Linked List DMA

• Enough readout speed with Linked List DMA• A Q module for testing is designing with local

buffer

Global Buffer Readout

• Controller on board moves compressed data from local buffers to a global buffer

• Read data from the global buffer with Direct DMA

• Higher speed but more difficult to design & debug than local buffer

• Final Q module will be designed with global buffer