Preliminary Datasheet Revision: April 2019...Vd = 24.0 V, Id1 + Id1a = 220 mA, Id2 + Id2a = 440 mA, Id3 + Id3a = 960 mA. Page 4 Drain Current vs. Input Power Simulated Performance-10

Preliminary Information: The data contained in this document describes new products in the sampling or preproduction phase of development and is for information only. Northrop Grumman reserves the right to change without notice the characteristic data and other specifications as they apply to this product. The product represented by this datasheet is subject to U.S. Export Law as contained in the Export Administration Regulations (EAR). Export out of the U.S. may require a U.S. Bureau of Industry and Security export license.

Preliminary Datasheet Revision: April 2019

APN31847.2-51.4 GHz GaN Power Amplifier

Web: http://www.as.northropgrumman.com/mps©2019 Northrop Grumman Systems Corporation

Phone: (310) 814-5000 • Fax: (310) 812-7011 • E-mail: [email protected]

Product Features RF frequency: 47.2 to 51.4 GHz

Linear Gain: 15-18 dB across the band

Psat: 10-12 Watt across the band

Die Size: 6.4 mm2.

0.15um GaN HEMT Process

4 mil SiC substrate

DC Power: 24 VDC @ 200 mA/mm

Product DescriptionThe APN318 GaN HEMT Power/Driver

amplifier is a three-stage Single-ended

power device, designed for use in 5G

wireless and SatCom Terminals. To ensure

rugged and reliable operation, HEMT devices

are fully passivated. Both bond pad and

backside metallization are Au-based that is

compatible with epoxy and eutectic die

attach methods.

Applications 5G Wireless

Internet of Things (IoT)

SatCom Terminals

Page 1

X = 3.2mm Y = 2.0mm

Specification Min Typ Max UnitFrequency 47.2 51.4 GHzLinear Gain 15 15.5 18 dBInput Return Loss 12 dBOutput Return Loss 8 10 dBPsat (Simulation*) 10 12 WattPAE (Simulation*) 20 %Vd1=Vd1a=Vd2=Vd2a=Vd3=Vd3a 20 24 28 VVg1, Vg1a, Vg2, Vg2a, Vg3, Vg3a -3.5 VId1+Id1a 220 mAId2+Id2a 440 mAId3+Id3a 960 mA

Parameter Min Max UnitDC Pwer 7 W/mmVd1=Vd1a=Vd2=Vd2a=Vd3=Vd3a 20 28 VId1+Id1a 385** 275*** mAId2+Id3a 770** 550*** mAId3+Id3a 1680 1200 mAVg1, Vg1a, Vg2, Vg2a, Vg3, Vg3a -5 0 VAssy. Temperature 300 deg. C

* Simulation Performance

Parameter Min Max UnitOperational Ambient Temp -65 125 deg. COperational Junction Temp -65 200 deg. CStorage Temp -65 150 deg. C

** Calculated With Vd=20V *** Calculated With Vd=28V

Maximum SOA Ratings (Ta = 25°C)

Bare Die Temperature Conditions

Performance Characteristics (Ta = 25°C)

Approved for Public Release; NG19-0583






0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80Frequency (GHz)

Circuit Gain (Wideband)

-10

-5

0

5

10

15

20

25

30

Gain

(dB

)

Circuit Gain vs. Frequency (Narrow Band)

Simulated Performance Characteristics (Typical Performance at 25°C) Vd = 24.0 V, Id1 + Id1a = 220 mA, Id2 + Id2a = 440 mA, Id3 + Id3a = 960 mA

Circuit Gain vs. Frequency (Wide Band)

Return Loss vs. Frequency (Wide Band)

Page 2

Return Loss vs. Frequency (Narrow Band)

45 46 47 48 49 50 51 52 53 54Frequency (GHz)

Circuit Gain (Narrowband)

02468

101214161820222426

Gain

(dB

)

45 46 47 48 49 50 51 52 53Frequency (GHz)

Circuit Return Loss

-30

-25

-20

-15

-10

-5

0

Retu

rn L

oss

(dB

)

Blue: InputRed: Output

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80Frequency (GHz)

Circuit Return Loss (Wideband)

-30

-25

-20

-15

-10

-5

0

Retu

rn L

oss

(dB

)








Circuit Gain vs. Frequency (Narrow Band)

Simulated Performance Characteristics (Typical Performance at 25°C) * Uncorrelated Monte Carlo for Distribution Vd = 24.0 V, Id1 + Id1a = 220 mA, Id2 + Id2a = 440 mA, Id3 + Id3a = 960 mA

Circuit Gain vs. Frequency (Wide Band)

Return Loss vs. Frequency (Wide Band)

Page 3

Return Loss vs. Frequency (Narrow Band)



45 46 47 48 49 50 51 52 53 54Frequency (GHz)

Circuit Gain (Narrowband)

02468

101214161820222426

Gain

(dB

)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80Frequency (GHz)

Circuit Gain (Wideband)

-10

-5

0

5

10

15

20

25

30

Gain

(dB

)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80Frequency (GHz)

Circuit Return Loss (Wideband)

-30

-25

-20

-15

-10

-5

0

Retu

rn L

oss

(dB

)

45 46 47 48 49 50 51 52 53Frequency (GHz)

Circuit Return Loss

-30

-25

-20

-15

-10

-5

0

Retu

rn L

oss

(dB

)







Output Power vs. Input PowerSimulated Performance

Simulated Power Performance Characteristics (Typical Performance at 25°C) Vd = 24.0 V, Id1 + Id1a = 220 mA, Id2 + Id2a = 440 mA, Id3 + Id3a = 960 mA

Page 4

Drain Current vs. Input PowerSimulated Performance

-10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28Power (dBm)

PIPO

0

5

10

15

20

25

30

35

40

45

50

Pout (d

Bm

), G

ain

(dB

)

0

5

10

15

20

25

30

35

40

45

50

PA

E (%

)

m4:24.06 dBm21.96Freq = 49 GHz

m3:24.07 dBm41.22 dBmFreq = 49 GHz

m2:24.04 dBm17.18 dBFreq = 49 GHz

m1:-9.591 dBm23.24 dBFreq = 49 GHz

46 47 48 49 50 51 52 53Frequency (GHz)

Power Frequency Sweep (@6dB Comp.)

0

5

10

15

20

25

30

35

40

45

50

Pout (d

Bm

), G

ain

(dB

)

0

5

10

15

20

25

30

35

40

45

50

PA

E (%

)

Blue: GainRed: PoutGreen: PAE

Blue: GainRed: PoutGreen: PAE

@ Psat (6dB comp.)

Output Power and Gain vs. Frequency Simulated Performance

-10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28Power (dBm)

PIPO Current (49 GHz)

0

50

100

150

200

250

Curre

nt (m

A)

p14p4p13p3

p12p11p10p2p9p8p7p1

p6p5

m1:16.05 dBm147 mAFreq = 49 GHz

m3:25.02 dBm117.9 mAFreq = 49 GHz

m2:20.25 dBm122.3 mAFreq = 49 GHz

Stage 1Stage 2Stage 3

Stages compress in order from last to first

20% current increase points marked






Phone: (310) 814-5000 • Fax: (310) 812-7011 • E-mail: [email protected] Page 5

Die Size and Bond Pad Locations(Not to Scale)

Biasing/De-Biasing Details:Bias for 1st must be from both sides.

Listed below are some guidelines for GaN device testing and wire bonding:a. Limit positive gate bias (G-S or G-D) to < 1Vb. Know your devices’ breakdown voltagesc. Use a power supply with both voltage and current limit.d. With the power supply off and the voltage and current levels at minimum, attach the ground lead to

your test fixture.i. Apply negative gate voltage (-5 V) to ensure that all devices are offii. Ramp up drain bias to ~10 Viii. Gradually increase gate bias voltage while monitoring drain current until 20% of the operating

current is achievediv. Ramp up drain to operating biasv. Gradually increase gate bias voltage while monitoring drain current until the operating current

is achievede. To safely de-bias GaN devices, start by debiasing output amplifier stages first (if applicable):

i. Gradually decrease drain bias to 0 V.ii. Gradually decrease gate bias to 0 V.iii. Turn off supply voltages

X = 3200 µm ± 25 µmY = 2000 ± 25 µmDC Bond Pad = 100 x 100 ± 0.5 µmRF Bond Pad = 100 x 100 ± 0.5 µmChip Thickness = 101 ± 5 µm

3200 µm

1000 µm

RFINGND

GNDRFOUT

GND

GND

VG

1A

VD

1AG

ND

GN

DG

ND

198 µm

1000 µm

2000 µm

VG

2A

VD

2AG

ND

VG

3A

VD

3A

GN

DG

ND

GN

D

809 µm1218 µm

1617 µm2026 µm

2737 µm

VG

1

VD

1G

ND

GN

DG

ND

198 µm

VG

2

VD

2G

ND

VG

3

VD

3

GN

DG

ND

GN

D

809 µm1218 µm

1617 µm

2026 µm

2737 µm






Phone: (310) 814-5000 • Fax: (310) 812-7011 • E-mail: [email protected] Page 6

Recommended Assembly Notes1. Bypass caps should be 100 pF (approximately) ceramic (single-layer) placed no farther than 30 mils

from the amplifier.2. Best performance obtained from use of <10 mil (long) by 3 by 0.5 mil ribbons on input and output.3. Part must be biased from both sides as indicated.4. The 0.1uF, 50V capacitors are not needed if the drain supply line is clean. If Drain Pulsing of the device

is to be used, do NOT use the 0.1uF , 50V Capacitors.Mounting ProcessesMost NGAS GaN IC chips have a gold backing and can be mounted successfully using either a conductive

epoxy or AuSn attachment. NGAS recommends the use of AuSn for high power devices to provide a good

thermal path and a good RF path to ground. Maximum recommended temp during die attach is 320oC for 30

seconds.

Note: Many of the NGAS parts do incorporate airbridges, so caution should be used when determining the

pick up tool.

CAUTION: THE IMPROPER USE OF AuSn ATTACHMENT CAN CATASTROPHICALLY DAMAGE GaN

CHIPS.

Suggested Bonding Arrangement

RFOutput

Substrate

RFInput

Substrate

= 100 pF, 15V (Shunt)

= 10 Ohms, 30V (Series)

= 0.01uF, 15V (Shunt)

VG1VD1

VG1AVD1A

PLEASE ALSO REFER TO OUR “GaN Chip Handling Application Note” BEFORE HANDLING, ASSEMBLING OR BIASING THESE MMICS!

= 0.1uF, 15V (Shunt)

= 100 pF, 50V (Shunt)

= 0.01uF, 50V (Shunt)

= 0.1uF, 50V (Shunt) [4] [4]

[4]

RFINGND

GNDRFOUT

GND

GND

VG

1A

VD

1AG

ND

GN

DG

ND

VG

2A

VD

2AG

ND

VG

3A

VD

3A

GN

DG

ND

GN

D

VG

1

VD

1G

ND

GN

DG

ND

VG

2

VD

2G

ND

VG

3

VD

3

GN

DG

ND

GN

D

VD3

[4]

VG3[4]VD2

VG2

VD3A

[4]

VG3AVD2AVG2A


Documents

Preliminary Datasheet Revision: April 2019...Vd = 24.0 V, Id1 + Id1a = 220 mA, Id2 + Id2a = 440 mA, Id3 + Id3a = 960 mA. Page 4 Drain Current vs. Input Power Simulated Performance-10