Pre-Encoded Multipliers Based onNon-Redundant Radix-4 Signed-Digit

Encoding

K. Tsoumanis, N. Axelos, N. Moschopoulos, G. Zervakis,and K. Pekmestzi

Abstract—In this paper, we introduce an architecture of pre-encoded multipliers

for digital signal processing applications based on off-line encoding of

coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD)

encoding technique, which uses the digit values f�1; 0;þ1;þ2g orf�2;�1; 0;þ1g, is proposed leading to a multiplier design with less complex

partial products implementation. Extensive experimental analysis verifies that the

proposed pre-encoded NR4SDmultipliers, including the coefficients memory, are

more area and power efficient than the conventional Modified Booth scheme.

Index Terms—Multiplying circuits, modified Booth encoding, pre-encoded

multipliers, VLSI implementation

Ç

1 INTRODUCTION

MULTIMEDIA and digital signal processing (DSP) applications (e.g.,fast Fourier transform (FFT), audio/video CoDecs) carry out alarge number of multiplications with coefficients that do notchange during the execution of the application. Since the multiplieris a basic component for implementing computationally intensiveapplications, its architecture seriously affects their performance.

Constant coefficients can be encoded to contain the least non-zero digits using the canonic signed digit (CSD) representation [1].CSD multipliers comprise the fewest non-zero partial products,which in turn decreases their switching activity. However, the CSDencoding involves serious limitations. Folding technique [2], whichreduces silicon area by time-multiplexing many operations intosingle functional units, e.g., adders, multipliers, is not feasible asthe CSD-based multipliers are hard-wired to specific coefficients.In [3], a CSD-based programmable multiplier design was proposedfor groups of pre-determined coefficients that share certain fea-tures. The size of ROM used to store the groups of coefficients issignificantly reduced as well as the area and power consumptionof the circuit. However, this multiplier design lacks flexibility sincethe partial products generation unit is designed specifically for agroup of coefficients and cannot be reused for another group. Also,this method cannot be easily extended to large groups of pre-determined coefficients attaining at the same time high efficiency.

Modified Booth (MB) encoding [4], [5], [6], [7] tackles the afore-mentioned limitations and reduces to half the number of partialproducts resulting to reduced area, critical delay and power con-sumption. However, a dedicated encoding circuit is required andthe partial products generation is more complex. In [8], Kim et al.proposed a technique similar to [3], for designing efficient MB mul-tipliers for groups of pre-determined coefficients with the samelimitations described in the previous paragraph.

In [9], [10], multipliers included in butterfly units of FFT pro-cessors use standard coefficients stored in ROMs. In audio [11],[12] and video [13], [14] CoDecs, fixed coefficients stored in

memory, are used as multiplication inputs. Since the values ofconstant coefficients are known in advance, we encode the coeffi-cients off-line based on the MB encoding and store the MBencoded coefficients (i.e., 3 bits per digit) into a ROM. Usingthis technique [15], [16], [17], the encoding circuit of the MBmultiplier is omitted. We refer to this design as pre-encoded MBmultiplier. Then, we explore a Non-Redundant radix-4 Signed-Digit (NR4SD) encoding scheme extending the serial encodingtechniques of [6], [18]. The proposed NR4SD encoding schemeuses one of the following sets of digit values: f�1; 0;þ1;þ2g orf�2;�1; 0;þ1g. In order to cover the dynamic range of the 2’scomplement form, all digits of the proposed representation areencoded according to NR4SD except the most significant one thatis MB encoded. Using the proposed encoding formula, we pre-encode the standard coefficients and store them into a ROM in acondensed form (i.e., 2 bits per digit). Compared to the pre-encoded MB multiplier in which the encoded coefficients need 3bits per digit, the proposed NR4SD scheme reduces the memorysize. Also, compared to the MB form, which uses five digit valuesf�2;�1; 0;þ1;þ2g, the proposed NR4SD encoding uses four digitvalues. Thus, the NR4SD-based pre-encoded multipliers include aless complex partial products generation circuit. We explore theefficiency of the aforementioned pre-encoded multipliers takinginto account the size of the coefficients’ ROM.

2 MODIFIED BOOTH ALGORITHM

Modified Booth is a redundant radix-4 encoding technique [6], [7].Considering the multiplication of the 2’s complement numbers A,B, each one consisting of n = 2k bits, B can be represented in MBform as:

B ¼ hbn�1 . . . b0i20s ¼ �b2k�122k�1 þ

X2k�2

i¼0

bi2i

¼ �bMBk�1 . . .b

MB0

�MB

¼Xk�1

j¼0

bMBj 22j:

(1)

Digits bMBj 2 f�2;�1; 0;þ1;þ2g; 0 � j � k� 1, are formed as

follows:

bMBj ¼ �2b2jþ1 þ b2j þ b2j�1; (2)

where b�1 ¼ 0. Each MB digit is represented by the bits s, one andtwo (Table 1). The bit s shows if the digit is negative (s = 1) orpositive (s = 0). One shows if the absolute value of a digit equals 1(one = 1) or not (one = 0). Two shows if the absolute value of a digitequals 2 (two = 1) or not (two = 0). Using these bits, we calculate the

MB digits bMBj as follows:

bMBj ¼ ð�1Þsj � ðonej þ 2twojÞ: (3)

Equations (4) form the MB encoding signals.

sj ¼ b2jþ1; onej ¼ b2j�1 � b2j;

twoj ¼ ðb2jþ1 � b2jÞ ^ onej:(4)

3 NON-REDUNDANT RADIX-4 SIGNED-DIGIT

ALGORITHM

In this section, we present the Non-Redundant radix-4 Signed-Digit(NR4SD) encoding technique. As in MB form, the number of partialproducts is reduced to half. When encoding the 2’s complementnumber B, digits bNR�

j take one of four values: f�2;�1; 0;þ1g or

bNRþj 2 f�1; 0;þ1;þ2g at the NR4SD� or NR4SDþ algorithm,

respectively. Only four different values are used and not five as in

� The authors are with the Department of Electrical and Computer Engineering,National Technical University of Athens, Athens, Greece.E-mail: {kostastsoumanis, njaxel, nikos, zervakis, pekmes}@microlab.ntua.gr.

Manuscript received 14 Jan. 2014; revised 31 Mar. 2015; accepted 28 Apr. 2015. Date ofpublication 30 Apr. 2015; date of current version 15 Jan. 2016.Recommended for acceptance by A. Nannarelli.For information on obtaining reprints of this article, please send e-mail to: reprints@ieee.org, and reference the Digital Object Identifier below.Digital Object Identifier no. 10.1109/TC.2015.2428691

0018-9340� 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

670 IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016

MB algorithm, which leads to 0 � j � k� 2. As we need to cover thedynamic range of the 2’s complement form, the most significant

digit is MB encoded (i.e., bMBk�1 2 f�2;�1; 0;þ1;þ2g). The NR4SD�

and NR4SDþ encoding algorithms are illustrated in detail in Figs. 1and 2, respectively.

NR4SD� AlgorithmStep 1. Consider the initial values j ¼ 0 and c0 ¼ 0.Step 2. Calculate the carry c2jþ1 and the sum nþ

2j of a half adder(HA) with inputs b2j and c2j (Fig. 1a).

c2jþ1 ¼ b2j ^ c2j; nþ2j ¼ b2j � c2j:

Step 3. Calculate the positively signed carry c2jþ2 (+) and the nega-tively signed sum n�

2jþ1 (-) of a HA* with inputs b2jþ1 (+) and c2jþ1

(+) (Fig. 1a). The outputs c2jþ2 and n�2jþ1 of the HA* relate to its

inputs as follows:

2c2jþ2 � n�2jþ1 ¼ b2jþ1 þ c2jþ1:

The following Boolean equations summarize the HA* operation:

c2jþ2 ¼ b2jþ1 _ c2jþ1; n�2jþ1 ¼ b2jþ1 � c2jþ1:

Step 4. Calculate the value of the bNR�j digit.

bNR�j ¼ �2n�

2jþ1 þ nþ2j: (5)

Equation (5) results from the fact that n�2jþ1 is negatively signed and

nþ2j is positively signed.

Step 5. j :¼ jþ 1.Step 6. If (j < k� 1), go to Step 2. If (j ¼ k� 1), encode the most sig-nificant digit based on the MB algorithm and considering the threeconsecutive bits to be b2k�1, b2k�2 and c2k�2 (Fig. 1b). If (j ¼ k), stop.

Table 2 shows how the NR4SD� digits are formed. Equations (6)

show how the NR4SD� encoding signals oneþj , one�j and two�j of

Table 2 are generated.

oneþj ¼ n�2jþ1 ^ nþ

2j;

one�j ¼ n�2jþ1 ^ nþ

2j;

two�j ¼ n�2jþ1 ^ nþ

2j:

(6)

The minimum and maximum limits of the dynamic range inthe NR4SD� form are �2n�1 � 2n�3 � 2n�5 � � � � � 2 < �2n�1 and

2n�1 þ 2n�4 þ 2n�6 þ � � � þ 1 > 2n�1 � 1. We observe that the NR4SD�

form has larger dynamic range than the 2’s complement form.

NR4SDþ AlgorithmStep 1. Consider the initial values j ¼ 0 and c0 ¼ 0.Step 2. Calculate the positively signed carry c2jþ1 (+) and the nega-tively signed sum n�

2j (-) of a HA* with inputs b2j (+) and c2j (+)

(Fig. 2a). The carry c2jþ1 and the sum n�2j of the HA* relate to its

inputs as follows:

2c2jþ1 � n�2j ¼ b2j þ c2j:

The outputs of the HA* are analyzed at gate level in the followingequations:

c2jþ1 ¼ b2j _ c2j; n�2j ¼ b2j � c2j:

Step 3. Calculate the carry c2jþ2 and the sum nþ2jþ1 of a HA with

inputs b2jþ1 and c2jþ1.

c2jþ2 ¼ b2jþ1 ^ c2jþ1; nþ2jþ1 ¼ b2jþ1 � c2jþ1:

TABLE 1Modified Booth Encoding

b2jþ1 b2j b2j�1 bMBj

sj onej twoj

0 0 0 0 0 0 00 0 1 +1 0 1 00 1 0 +1 0 1 00 1 1 +2 0 0 11 0 0 �2 1 0 11 0 1 �1 1 1 01 1 0 �1 1 1 01 1 1 0 1 0 0

Fig. 1. Block diagram of the NR4SD� encoding scheme at the (a) digit and (b) wordlevel.

Fig. 2. Block diagram of the NR4SDþ encoding scheme at the (a) digit and (b) wordlevel.

TABLE 2NR4SD� Encoding

2’s complement NR4SD� form Digit NR4SD� Encoding

b2jþ1 b2j c2j c2jþ2 n�2jþ1 nþ

2j bNR�j

oneþj one�j two�j0 0 0 0 0 0 0 0 0 00 0 1 0 0 1 +1 1 0 00 1 0 0 0 1 +1 1 0 00 1 1 1 1 0 �2 0 0 11 0 0 1 1 0 �2 0 0 11 0 1 1 1 1 �1 0 1 01 1 0 1 1 1 �1 0 1 01 1 1 1 0 0 0 0 0 0

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Step 4. Calculate the value of the bNRþj digit.

bNRþj ¼ 2nþ

2jþ1 � n�2j: (7)

Equation (7) results from the fact that nþ2jþ1 is positively signed and

n�2j is negatively signed.

Step 5. j :¼ jþ 1.Step 6. If (j < k� 1), go to Step 2. If (j ¼ k� 1), encode the mostsignificant digit according to MB algorithm and considering thethree consecutive bits to be b2k�1, b2k�2 and c2k�2 (Fig. 2b). If (j ¼ k),stop.

Table 3 shows how the NR4SDþ digits are formed. Equations (8)

show how the NR4SDþ encoding signals oneþj , one�j and twoþj of

Table 3 are generated.

oneþj ¼ nþ2jþ1 ^ n�

2j;

one�j ¼ nþ2jþ1 ^ n�

2j;

twoþj ¼ nþ2jþ1 ^ n�

2j:

(8)

The minimum and maximum limits of the dynamic range in theNR4SDþ form are �2n�1 � 2n�4 � 2n�6 � � � � � 1 < �2n�1 and

2n�1 þ 2n�3 þ 2n�5 þ � � � þ 2 > 2n�1 � 1. As observed in theNR4SD� encoding technique, the NR4SDþ form has largerdynamic range than the 2’s complement form.

Considering the 8-bit 2’s complement number N, Table 4exposes the limit values �28 ¼ �128, 28 � 1 ¼ 127, and two typicalvalues of N, and presents the MB, NR4SD� and NR4SDþ digitsthat result when applying the corresponding encoding techniquesto each value of N we considered. We added a bar above the nega-tively signed digits in order to distinguish them from the positivelysigned ones.

4 PRE-ENCODED MULTIPLIERS DESIGN

In this section, we explore the implementation of pre-encoded mul-tipliers. One of the two inputs of these multipliers is pre-encodedeither in MB or in NR4SD�/NR4SDþ representation. We considerthat this input comes from a set of fixed coefficients (e.g., the coeffi-cients for a number of filters in which this multiplier will be usedin a dedicated system or the sine table required in an FFT imple-mentation). The coefficients are encoded off-line based on MB orNR4SD algorithms and the resulting bits of encoding are stored ina ROM. Since our purpose is to estimate the efficiency of the

proposed multipliers, we first present a review of the conventionalMB multiplier in order to compare it with the pre-encodedschemes.

4.1 Conventional MB Multiplier

Fig. 3 presents the architecture of the system which comprises theconventional MB multiplier and the ROM with coefficients in 2’scomplement form. Let us consider the multiplication A � B. Thecoefficient B ¼ hbn�1 . . . b0i20s consists of n = 2k bits and is driven to

the MB encoding blocks from a ROM where it is stored in 2’s com-plement form. It is encoded according to the MB algorithm(Section 2) and multiplied by A ¼ han�1 . . . a0i20s, which is in 2’s

complement representation. We note that the ROM data bus widthequals the width of coefficient B (n bits) and that it outputs onecoefficient on each clock cycle.

The k partial products are generated as follows:

PPj ¼ A � bMBj ¼ �pj;n2

n þXn�1

i¼0

pj;i2i: (9)

The generation of the ith bit pj;i of the partial product PPj is illus-trated at gate level in Fig. 4a [6], [7]. For the computation of theleast and most significant bits of PPj , we consider a�1 ¼ 0 and

an ¼ an�1, respectively.After shaping the partial products, they are added, properly

weighted, through a carry save adder (CSA) tree along with thecorrection term (COR):

P ¼ A � B ¼ CORþXk�1

j¼0

PPj22j; (10)

COR ¼Xk�1

j¼0

cin;j22j þ 2n 1þ

Xk�1

j¼0

22jþ1

!; (11)

where cin;j ¼ ðonej _ twojÞ ^ sj (Table 1). The CS output of the treeis leaded to a fast carry look ahead (CLA) adder [19] to form thefinal result P ¼ A � B (Fig. 3).

4.2 Pre-Encoded MB Multiplier Design

In the pre-encoded MB multiplier scheme, the coefficient B isencoded off-line according to the conventional MB form (Table 1).The resulting encoding signals of B are stored in a ROM. Thecircled part of Fig. 3, which contains the ROM with coefficients in2’s complement form and the MB encoding circuit, is now totallyreplaced by the ROM of Fig. 5. The MB encoding blocks of Fig. 3are omitted. The new ROM of Fig. 5 is used to store the encodingsignals of B and feed them into the partial product generators (PPj

Generators—PPG) on each clock cycle.Targeting to decrease switching activity, the value ‘1’ of sj in the

last entry of Table 1 is replaced by ‘0’. The sign sj is now given by

the relation:

TABLE 3NR4SDþ Encoding

2’s complement NR4SDþ form Digit NR4SDþ Encoding

b2jþ1 b2j c2j c2jþ2 nþ2jþ1 n�

2j bNRþj

oneþj one�j twoþj0 0 0 0 0 0 0 0 0 00 0 1 0 1 1 +1 1 0 00 1 0 0 1 1 +1 1 0 00 1 1 0 1 0 +2 0 0 11 0 0 0 1 0 +2 0 0 11 0 1 1 0 1 �1 0 1 01 1 0 1 0 1 �1 0 1 01 1 1 1 0 0 0 0 0 0

TABLE 4Numerical Examples of the Encoding Techniques

2’s Complement 10000000 10011010 01011001 01111111

Integer �128 �102 +89 +127Modified Booth �2 0 0 0 �2 2 �1 �2 1 2 �2 1 2 0 0 �1NR4SD� �2 0 0 0 �1 �2 �1 �2 2 �2 �2 1 2 0 0 �1NR4SDþ �2 0 0 0 �2 1 2 2 1 1 2 1 2 0 0 �1

Fig. 3. System architecture of the conventional MB multiplier.

672 IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016

sj ¼ b2jþ1 � ðb2jþ1 ^ b2j ^ b2j�1Þ: (12)

As a result, the PPG of Fig. 4a is replaced by the one of Fig. 4b.Compared to (4), (12) leads to a more complex design. However,due to the pre-encoding technique, there is no area/delay over-head at the circuit.

The partial products, properly weighted, and the COR of (11)are fed into a CSA tree. The input carry cin;j of (11) is computed ascin;j ¼ sj based on (12) and Table 1. The CS output of the tree is

finally merged by a fast CLA adder.However, the ROMwidth is increased. Each digit requests three

encoding bits (i.e., s, two and one (Table 1)) to be stored in the ROM.Since the n-bit coefficient B needs three bits per digit when encodedin MB form, the ROM width requirement is 3n/2 bits per coeffi-cient. Thus, the width and the overall size of the ROM areincreased by 50 percent compared to the ROM of the conventionalscheme (Fig. 3).

4.3 Pre-Encoded NR4SD Multipliers Design

The system architecture for the pre-encoded NR4SD multipliersis presented in Fig. 6. Two bits are now stored in ROM:

n�2jþ1, n

þ2j (Table 2) for the NR4SD� or nþ

2jþ1, n�2j (Table 3) for the

NR4SDþ form. In this way, we reduce the memory requirementto n + 1 bits per coefficient while the corresponding memoryrequired for the pre-encoded MB scheme is 3n/2 bits per coeffi-cient. Thus, the amount of stored bits is equal to that of the con-ventional MB design, except for the most significant digit thatneeds an extra bit as it is MB encoded. Compared to the pre-encoded MB multiplier, where the MB encoding blocks are omit-ted, the pre-encoded NR4SD multipliers need extra hardware togenerate the signals of (6) and (8) for the NR4SD� and NR4SDþ

form, respectively. The NR4SD encoding blocks of Fig. 6 imple-ment the circuitry of Fig. 7.

Each partial product of the pre-encoded NR4SD� andNR4SDþ multipliers is implemented based on Figs. 4c and 4d,respectively, except for the PPk�1 that corresponds to the mostsignificant digit. As this digit is in MB form, we use the PPG ofFig. 4b applying the change mentioned in Section 4.2 for the sjbit. The partial products, properly weighted, and the COR of(11) are fed into a CSA tree. The input carry cin;j of (11) is calcu-

lated as cin;j ¼ two�j _ one�j and cin;j ¼ one�j for the NR4SD� and

NR4SDþ pre-encoded multipliers, respectively, based on Tables 2

and 3. The carry-save output of the CSA tree is finally summedusing a fast CLA adder.

5 IMPLEMENTATION RESULTS

We implemented in Verilog the multiplier designs of Table 5.The PPGs for the NR4SD�, NR4SDþ multipliers (Figs. 4c and4d, respectively) contain a large number of inverters since allthe A bits are complemented in case of a negative digit. Inorder to avoid these inverters and, thus, reduce the area/power/delay of NR4SD�, NR4SDþ pre-encoded multipliers, thePPGs for the NR4SD�, NR4SDþ multipliers were designedbased on primitive NAND and NOR gates, and replaced byFigs. 4e and 4f, respectively.

The CSA tree and CLA adder were imported from SynopsysDesignWare library. The ROM for the 2’s complement or pre-encoded coefficients is a synchronous ROM of 512 words often metat DSP systems, e.g., speech CoDecs or audio filtering [20]. Thewidth of each ROM depends on the multiplier architecture(Table 5). A finite state machine synchronized the data flow andthe multiplier operation but was not considered in the area/powercalculations.

We used Synopsys Design Compiler and the Faraday 90 nmstandard cell library to synthesize the evaluated designs, consid-ering the highest optimization degree and keeping the hierarchy

Fig. 4. Generation of the ith Bit pj;i of PPj for a) Conventional, b) Pre-Encoded MB Multipliers, c) NR4SD�, d) NR4SDþ Pre-Encoded Multipliers, and e) NR4SD�,f) NR4SDþ Pre-Encoded Multipliers after reconstruction.

Fig. 5. The ROM of pre-encoded multiplier with standard coefficients in MB Form.

Fig. 6. System architecture of the NR4SD multipliers.

Fig. 7. Extra circuit needed in the NR4SD multipliers to complete the (a) NR4SD�

and (b) NR4SDþ encoding.

IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016 673

of the designs. The memory compiler of the same library pro-vided the physical ROMs for the coefficients. Since the ROMsrequired for the pre-encoded multipliers are larger than the onefor the conventional MB scheme, access time is increased. How-ever, the pre-encoded designs may achieve lower clock periodsthan the conventional MB one because the encoding circuits thatare included in the critical path, are omitted or less complex. Wefirst synthesized each design at the lowest achievable clockperiod and then, each pre-encoded design at the clock periodachieved by the conventional MB scheme. We also synthesizedall designs at higher clock periods targeting to explore theirbehavior under different timing constraints in terms of area andpower consumption. For each clock period, we simulated alldesigns using Modelsim and 20 different sets of 512 ROMwords. For the conventional MB multiplier, the 2’s complementinputs were randomly generated with equal possibility of a bitto be 0 or 1. Using a high level programming language, we gen-erated the pre-encoded values of B which we then stored in theROMs of pre-encoded designs. Finally, we used SynopsysPrimeTime to calculate power consumption.

The performance of the proposed designs is considered withrespect to the width of the input numbers, i.e., 16, 24 and 32 bits.Table 6 summarizes the performance of each architecture at mini-mum possible clock period. We observe that the pre-encodedNR4SD architectures are more area efficient than the conventionalor pre-encoded MB designs with respect to their performance inthe lowest possible clock periods. Regarding power dissipation,the pre-encoded NR4SD� scheme consumes the least power which,

in the cases of 16 and 24 bits of input width, is equal to the powerconsumed by the pre-encoded MB design.

With respect to the input width, Figs. 8, 9, and 10 depict thearea and power gains that the system (i.e., ROM + multiplier),the multiplier and the PPG of the pre-encoded MB, NR4SD�

and NR4SDþ designs present over the conventional MB scheme.The comparison among the designs starts at the lowest commonachievable clock period for all designs and continues at higherclock periods by increasing the clock period by step 0.2 ns untilit reaches 4 ns. We first compare the entire designs incorporatingthe required ROMs. Then, we make a comparison among themultipliers of all schemes as they are implemented based on dif-ferent encoding techniques. Also, we compare the PPGs of themultipliers because they are key subcomponents occupying sig-nificant area in the multipliers.

TABLE 5Multiplier Designs

TABLE 6Performance at Lowest Clock Periods

Fig. 8. Area / power gains of the pre-encoded designs over the conventional MB scheme at 16 Bits.

674 IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016

In Figs. 8, 9, and 10, the pre-encoded MB scheme delivers lossesin area complexity (�9:47, �7:71 and �6:44 percent on average1 at16, 24 and 32 bits, respectively) and power consumption (�7:25,�9:08 and �7:01 percent on average at 16, 24 and 32 bits, respec-tively). This was expected considering that the size of the ROMrequired by the pre-encoded MB design is by 50 percent largerthan the ROM of the conventional MB scheme. However, the pro-posed pre-encoded NR4SD designs (ROM and multiplier) deliverimprovements in area complexity (up to 7:28 percent on averagefor the pre-encoded NR4SD� design at 32 bits) and power dissipa-tion (up to 9:46 percent on average for the pre-encoded NR4SDþ

design at 24 bits) compared to the conventional MB scheme. Wenote that the gains that concern the multipliers of the pre-encodedNR4SD designs over the one of the conventional MB scheme aremuch higher. This is mainly due to the less complex PPG circuit ofthe NR4SD designs (Figs. 4e and 4f) compared to the one of theconventional MB design (Fig. 4a) considering that the partial prod-ucts generation largely contributes to the area complexity andpower dissipation of a multiplier. Figs. 8, 9, and 10 verify the areaand power gains of the PPG of the NR4SD designs over the one ofthe conventional MB scheme.

As clock period increases, the datapath of the multiplication cir-cuit changes and the standard cells used for its synthesis becomeless complex regarding area occupation, internal capacitance andports’ load. However, the ROM used in each evaluated design is astandard cell and its critical delay, area occupation and both

Fig. 10. Area/power gains of the pre-encoded designs over the conventional MB scheme at 32 bits.

Fig. 9. Area/power gains of the pre-encoded designs over the conventional MB scheme at 24 bits.

1. The average gains/losses for a specific input width are calculated consider-ing the gains/losses over the conventional MB scheme for all clock periods thatconcern the input width of interest.

IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 2, FEBRUARY 2016 675

internal and ports’ load remain unchanged as clock periodincreases. Thus, the multiplier changes sharply as clock periodincreases but the ROM does not change. The power dissipation ofthe multiplier is sharply decreased as clock period increases sinceboth frequency and overall load charge decrease, while the powerconsumption of the ROM is linearly decreased following the fre-quency reduction. Also, the experimental analysis is based onROMs generated using the memory compiler of the Faraday 90 nmstandard cell library, but the measurements of the systems (i.e.,ROM +Multiplier) could change using memories of emerging tech-nologies [21]. Thus, the area and power values for the multipliersof the designs are useful for explorations of the proposed pre-encoded designs based on different memory technologies.

6 CONCLUSION

In this paper, new designs of pre-encoded multipliers are exploredby off-line encoding the standard coefficients and storing them insystem memory. We propose encoding these coefficients in theNon-Redundant radix-4 Signed-Digit (NR4SD) form. The proposedpre-encoded NR4SD multiplier designs are more area and powerefficient compared to the conventional and pre-encoded MBdesigns. Extensive experimental analysis verifies the gains of theproposed pre-encoded NR4SD multipliers in terms of area com-plexity and power consumption compared to the conventional MBmultiplier.

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