Practically Realizing Random Access Scan Anand S. Mudlapur Department of Electrical and Computer Engineering Auburn University, AL 36849 USA

Practically Realizing Practically Realizing Random Access ScanRandom Access Scan

Anand S. Mudlapur

Department of Electrical and Computer EngineeringAuburn University, AL 36849 USA

11/15/2005 MS Thesis Defence 2

Motivation for This Work• Serial scan (SS) test sequence lengths

and test power consumption are increasing rapidly.– Reduction of test power and test time are

complementary objectives in serial scan.• Scope of increasing delay fault coverage

is limited in serial scan. • In spite of the advantages (test time,

test volume, test power, and ease of testing for delay faults), random access scan (RAS) is not popular due to high overhead.


Outline

• Introduction to scan based testing– Advantages– Limitations

• Introduction to RAS• Design of a new toggle RAS Flip-

Flop• Highlight the uniqueness and

feasibility of our design due to the reduction of two global signals


Outline (contd.)

• A new scan-out structure• Analytical formulation of hardware

overhead• Algorithm to compact test vectors• ATPG targeted for toggle RAS• Results on ISCAS Benchmark Circuits• Case study on an industrial circuit• Conclusion and future work


Serial Scan: Most Popular DFT Method

Combinational Circuit

FFFFFFScan-inScan-in Scan-outScan-out

PIPI POPO

Test controlTest control(TC)(TC)


Introduction to Serial Scan (contd.)

• Advantage: Enables application of combinational vectors to sequential circuits

• Problems:– Clock cycles prohibitive as number of flip-flops

increases– Scan-in often performed at a slow scan clock

compared to functional clock of the circuit– Scan-in and scan-out cause undesirable circuit

activity resulting in excessive power dissipation


Test Power and Time of Serial Scan

• Test power may exceed critical design limits.• All flip-flops are controlled and observed

although a test may need those operation only on a subset of flip-flops.

• Example: A circuit with 5,000 Flip-Flops and 10,000 combinational test vectorsTotal scan cycles = 5,000 × 10,000

+ 10,000 + 5,000 = 50,015,00050,015,000 ! !


Solutions for Test Time Problem of Serial Scan

• Partial scan [Agrawal et. al. 88] provides a trade off between ease of test generation and hardware cost of scan. Test power may still be a concern.

• Vector compaction [Touba et. al. 00], may cause increased circuit activity resulting in higher power consumption.

• Cross-Check [Gheewala et. al. 91] was a comprehensive test method for sequential circuits but the technology required dedicated routing layers for test wiring.


Cross-Check

• A grid architecture as shown in the adjoining figure

• Flip-flops contents read out row-wise

• Data from the flip-flops fed into a MISR


Solutions for Test Power Problems of Serial Scan

• Test scheduling for SOCs using power constraint [Chou et. al. 91]: Test parallelism reduces, increasing the test time.

• Slow scan-clock [Chandra et. al. 94]: Test time increases.

• ATPG based methods [Wang et. al. 94, Kajihara et. al. 02]: Result in lengthy test sequences.

Contd.


Further Solutions for Test Power (contd.)

• Modification of the order of scan cells or inserting inversion logic between scan cells after the test generation [Dabholkar et al. 98]; limited effect on test power.

• Blocking hardware methods: Hold latch, blocking gates; have additional overhead.


Delay Testing in Serial Scan

• Delay testing in serial scan is highly constrained; may result in low fault coverage.

• Enhanced scan flip-flops can make the application of arbitrary vectors possible.

• This technique requires a hold-latch connected to each Flip-Flop in addition to a “HOLD” signal routed to every hold latch resulting in increased area overhead and signal delay in the scan path.


Delay Testing in Serial Scan


SFF

SFF

PIPI POPO

HL

HL

Scan-out

HOLDScan-in

CK TC

CK TC

CK

TC

HOLD

V1 s-in V2 state scan-in

Scan-out

V1 V2

Test result latched

V1 settles


Introduction to RAS• Random Access Scan (RAS) offers a single

solution to the problems faced by serial scan (SS):– Each RAS cell is uniquely addressable for read

and write.– RAS addresses both test application time and

test power problems simultaneously• Previous and current publications on RAS:

• Ando, COMPCON-80• Wagner, COMPCON-83• Ito, DAC-90• Baik et al., VLSI Design-04, ITC-05, ATS-05, VLSI Design-06• Mudlapur et al., VDAT-05, ITC-05

• Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops.


Contributions of Present Work

• Eliminate scan-in signal from circuit by using a new toggling RAS flip-flop.

• Eliminate test control signal to flip-flops.

• Provide a new scan-out architecture:– A hierarchical scan-out bus– An option of multi-cycle scan-out


Random Access Scan (RAS)

During every test, only a subset of all Flip-flops needs to be set and observed for

testing the targeted faults


FFFFFF

PIPI POPO

Scan-outScan-out busbus

Decoder

Address Address InputsInputs

Scan-inScan-in

TCTC

These signals are eliminated in our design


Conventional RAS

M S

ClockClock

Combinational Combinational Logic DataLogic Data

Address Decoder


RAS-FFRAS-FF

MUX

MUX

Address Register

Scan-inScan-in

ModeMode

ACLK


New “Toggle” RAS Flip-Flop

M S

ClockClock

MUX


Row DecoderColumn Decoder


To Output To Output BUSBUS

Address (logAddress (log22nnffff))

yyxx

√√nnff ff LinesLines √√nnff ff LinesLines

RAS-FFRAS-FF

0

1

Output Output BUSBUS

ControlControl


Toggle RAS Flip-Flop Operation

Function Clock

Address decoder outputs

Row (x)Column

(y)

Normal Data

Active 0 0

Toggle Data

Inactive 1Active Clock

InactiveActive Clock

1

Hold Data

Inactive 1 0

Inactive 0 1

Inactive 0 0


Toggle Flip-Flop Operation (contd.)

RASFF1

Unaddressed FFsUnaddressed FFsAddressed FFAddressed FF

RASFF0

Decodedaddress

lines

RASFF0

RASFF1

x4x4

y1y1 y2y2 y3y3


Macro Level Idea of Signals to RAS-FF

x1x1

x2x2

x3x3

x4x4

y1y1 y2y2 y3y3 y4y4

RASFF11

RASFF14

RASFF12

RASFF13

RASFF11

RASFF14

RASFF12

RASFF13

RASFF21

RASFF24

RASFF22

RASFF23

RASFF31

RASFF32

RASFF33

RASFF34

RASFF41

RASFF42

RASFF43

RASFF44 To Next

Level

RASFF22

4-to-1 Scan-out

Macrocell


Scan-out Macrocell

• A 4x4 block scan-out data flow and control logic

• D-FFs may be inserted at the two outputs of macrocell for multi-cycle scan-out.

To Next LevelTo Next LevelOutput BUSOutput BUS

Control Signal toControl Signal toNext Level BUSNext Level BUS

Data Bus FromData Bus From4 RAS FFs4 RAS FFs

{Control FromControl From4 RAS FFs4 RAS FFs


Routing of Decoder Signals in RAS

COLUMN DECODER

ROW

DECODER

Flip-FlopsPlaced on a GridStructure

Address Address (log(log2 2 √√ nnffff))

Address Address (log(log2 2 √√ nnffff))


Gate Area Overhead

%nn

n

ffg

ff100

10

4

%nn

nn

ffg

ffff100

10

6

Gate area overhead of Gate area overhead of Serial ScanSerial Scan

==

Gate area overhead of Gate area overhead of Random Access ScanRandom Access Scan

==

wherewhere n nff ff – Number of Flip-Flops– Number of Flip-Flopsnng g – Number of Gates– Number of Gates

Assumption: D-FF contains 10 logic gates.


Gate Area Overhead (Examples)

1. A circuit with 100,000 gates and 5,000 FFsGate overhead of serial scan = 13.3 %

Gate overhead of RAS = 20.0 %(Typical example from an industrial circuit.

Details in later slide)

2. A circuit with 500,000 gates and 5,000 FFsGate overhead of serial scan = 3.6 %

Gate overhead of RAS = 5.5 %


Overhead in Terms of Transistors

%nn

n

fft

ff100

28

10

Transistor overhead of Transistor overhead of

Serial ScanSerial Scan ==

%nn

n

fft

ff100

28

26

Transistor overhead of Transistor overhead of

Random Access ScanRandom Access Scan==

Where Where nntt is number of transistors in comb. is number of transistors in comb. logic.logic.

D-flip-flop (28 transistors), serial scan FF D-flip-flop (28 transistors), serial scan FF (28+10) and RAS FF (28+26) were (28+10) and RAS FF (28+26) were

designed in 0.5designed in 0.5μμ CMOS CMOStechnologytechnology using Mentor Graphics Design using Mentor Graphics Design

Architect.Architect.


Algorithm to Compact Test Vectors

• Obtain the combinational vectors along with good circuit responses and store the results in a stack

• Find the Flip-Flops where the faults are propagated at each vector

• While number of vectors > 0 or remaining faults > 0– Read all Flip-Flops where the faults are detected– Choose the next vector from stack that is at least

hamming distance from current Flip-Flop states• End While


RAS-FF

Compaction of Test Vectors


RAS-FFRAS-FFRAS-FF

PIPI POPO

Scan-outScan-out busbus

Decoder

Address Address InputsInputs

Stack101000010110111100001100

0 001 10


Test Time

0

200

400

600

800

Tes

t cl

ock

cycl

es

(thousa

nds)

s3271 s3384 s5378 s13207

Circuits

Scan RAS


Test Power

0.001

0.01

0.1

1

Tes

t Pow

er

(Nor

mal

ized

to

seri

al s

can)

s3271 s3384 s5378 s13207

Circuits

Scan RAS


Case Study on an Industrial Circuit

• A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd.

• The preliminary results were as follows:1. The gate area overhead of RAS for a chip

with ~5500 Flip-Flops and ~100,000 NAND equivalent gates was of the order of 18%.

2. 4X reduction in test time was estimated. A speed-up of up to 10X was considered possible using ATPG heuristics.

3. Estimated routing and device area overhead of RAS in physical layout was 10.4%.


Conclusion

• New design of a “Toggle” Flip-Flop reduces the RAS routing overhead.

• Proposed RAS architecture with new FF has several other advantages:– Algorithmic minimization reduces test

cycles by 60%.– Power dissipation during test is reduced by

99%.

• A novel RAS scan-out method presented.• For details on “Toggle” Flip-Flop, see

Mudlapur et al., VDAT-05.


Backup Slides

Thank you!

Documents

Practically Realizing Random Access Scan Anand S. Mudlapur Department of Electrical and Computer Engineering Auburn University, AL 36849 USA