PowerPoint 프레젠테이션eyeontech.1004hp.com/product/images/POA030D.pdf · 2013-02-28 · Rev 0.1 POA030D 1/4 inch VGA Single Chip CMOS Image Sensor with 640 X 480 Pixel Array

1/4 inch VGA Single Chip CMOS Image Sensor with

640 X 480 Pixel Array

Rev 0.1

Last update : 06. FEB. 2009

6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,

Suwon-si, Gyeonggi-do, 443-766, Korea

Tel : 82-31-888-5300, FAX : 82-31-888-5398

Copyright ⓒ 2009, Pixelplus Co.,Ltd

ALL RIGHTS RESERVED

Preliminary

Brief

Data sheet

POA030D

Rev 0.1

POA030D



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CrystalImage & ImagingInnovation

▶ Revision History

Version Date [D/M/Y] Notes Writer

0.0 04/02/2009 (Preliminary) Seungpyo Hong

0.1 06/02/2009 Added device information Chang hui Ye

Caution : This datasheet can be changed without prior notice !! If you want to get up-to-date version,

please send a mail to [email protected].

Rev 0.1

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▶ Features

▷ 656x496 effective pixel array with

RGB bayer color filters and micro-lens.

▷ Power supply :

AVDD : 2.8V, DVDD : 1.5V/1.8V,

HVDD : 1.8 ~ 3.3V

▷ Output formats : CCIR656, 8bit YCbCr422,

8bit RGB565, 9bit RGB Bayer, 9bit Mono.

▷ Image processing on chip : lens shading,

gamma correction, defect correction,

low pass filter, color interpolation,

edge enhancement, color correction,

brightness, contrast, saturation,

auto black level compensation,

auto white balance, auto exposure control

and back light compensation.

▷ Max. 30 frames/sec progressive scan

@ 27 MHz master clock for VGA.

▷ Frame size, window size and position can

be programmed through a 2-wire serial

interface bus.

▷ VGA / CIF / QVGA / QCIF / QQVGA Scaling.

▷ Horizontal / Vertical mirroring.

▷ 50Hz, 60Hz flicker automatic cancellation.

▷ Soft reset.

▷ High Image Quality and High low light

performance.

▷ I2C Master.

▷ LED Control.

POA030D

[ Fig. 1 ] PIN Description

[ Table 1 ] Typical Parameters

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

AV

DD

1

AG

ND

1

TE

DG

ND

D0

D1

D2

D3

D4

HG

ND

X1

X2

HV

DD

PC

LK

DV

DD

XO

UT

DG

ND

RS

DA

T

RS

CL

K

NT

SC

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

AV

DD

AG

ND

TE

ST

ISIN

ST

DB

Y

RS

TB

VS

YN

C

D8

D7

D6

D5

HV

DD

HS

YN

C

HG

ND

SS

DA

T

SS

CL

K

LE

D1

DV

DD

DG

ND

LE

D0

Effective Pixel Array 656 x 496

Pixel Size 5.55 um x 5.55 um

Effective Image Area 3.64 mm x 2.752 mm

Optical Format 1/4 inch

Max. Clock frequency 27 Mhz

Max. Frame Rate30fps @ 27MHz

60fps @ 27MHz (bayer only)

Dark Signal 25.2 [ mV/sec ]

Sensitivity 2.93 [V/Lux.sec]

Power Consumption67[mW] @ Dynamic

6.8[uW] @ Standby

Operating Temp.-40 ~ 105 [℃]

(Fully Functional Temp)

Dynamic Range 51 [dB] @ 60 degree

SNR 44.2 [dB] @ 60 degree

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▶ PIN Descriptions

[ Table 2 ] Pin Descriptions

Pin No. Name I/O Type Functions / Descriptions

1 AVDD1 P Analog power supply1 : 2.8V DC. 0.1uF to AGND

2 AGND1 P Analog power ground1.

3 TE I Chip Test Mode enable. User have to connect this terminal to DGND

4 DGND P Digital power ground for core circuits.

5 D0 O Bit 0 of data output.





10 HGND P I/O power ground.

11 X1 I Crystal input pad. To use Crystal, HVDD must be 2.8~3.3V

Do not leave this PIN floating. If user want to use external master clock or

oscillator instead of using crystal, please connect this PIN to HVDD or HGND.

12 X2 I/O Crystal output pad or master clock input pad.

To use Crystal, HVDD must be 2.8~3.3V

13 HVDD P I/O Power supply: 1.8~3.3V DC with 100nF capacitor to HGND.

Voltage range for all output signals is 0V ~ HVDD.

HVDD must be higher than or equal to DVDD


14 PCLK O Pixel clock. Data can be latched by external devices at the rising or falling

edge of PCLK. The polarity can be controlled anyway.

15 DVDD P Digital power supply : DC 1.5/1.8V.

16 XOUT O Master clock output for encoder chip.

17 DGND P Digital ground for core circuits.

18 RSDAT I/O 2-wire serial interface master data bus.

19 RSCLK O 2-wire serial interface master clock.

20 NTSC I NTSC/PAL mode selection pin for I2C master.

This PIN must be connected to HVDD or HGND

21 LED0 O LED control bit 0. LED[1:0] provide 2bit combination of enable signal which

can turn-on LED device when low light condition.

22 DGND P Digital ground for core circuits.

23 DVDD P Digital power supply : DC 1.5/1.8V.

24 LED1 O LED control bit 1. LED[1:0] provide 2bit combination of enable signal which

can turn-on LED device when low light condition.

25 SSCLK I 2-wire serial interface slave clock

26 SSDAT I/O 2-wire serial interface slave data bus.

27 HGND P I/O power ground.

28 HSYNC O Horizontal synchronization pulse. HSYNC is high ( or low ) for the horizontal

window of interest. It can be programmed to appear or not outside the vertical

window of interest.

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▶ PIN Descriptions

Pin No. Name I/O Type Functions / Descriptions

29 HVDD P I/O Power supply: 1.8~3.3V DC with 100nF capacitor to HGND.

Voltage range for all output signals is 0V ~ HVDD.

HVDD must be higher than or equal to DVDD






34 VSYNC O Vertical sync : Indicates the start of a new frame.

35 RSTB I System reset must remain low for at least 8 master clocks after power is

stabilized. When the sensor is reset, all registers are set to their default values.

36 STDBY I Power standby mode. When Standby=‘1’ there’s no current flow in any analog

circuit branch, neither any beat of digital clock. D<8:0> and PCLK, HSYNC,

VSYNC pins can be programmed to tri-state or all ‘1’ or all ‘0’. But it is possible

to control internal registers through 2-wire serial interface bus in Standby

mode. All registers retain their current values.

37 ISIN I Illumination sensor input pin for LED control function.

38 TEST O Analog test pin.

39 AGND P Analog power ground.

40 AVDD P Analog power supply : 2.8V DC. 0.1uF to AGND

[ Table 2 ] Pin Descriptions (continued)

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▶ Signal Environment

▶ Chip Architecture

POA030D has 3.3V tolerant Input pads. Input signals must be higher than or equal to HVDD but cannot be

higher than 3.3V. POA030D input pad has built in reverse current protection circuit, which makes it possible to

apply input voltage even if the HVDD is disconnected or floating. Voltage range for all output signals is 0V ~

HVDD.

POA030D has 656 x 496 effective pixel array and column/row driver circuits to read out the pixel data

progressively. CDS circuit reduces noise signals generated from various sources mainly resulting from process

variations. Pixel output is compared with the reset level of its own and only the difference signal is sampled,

thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain factors to

balance the color of images in various light conditions. The analog signals are converted to digital forms one

line at a time and 1 line data are streamed out column by column. The Bayer RGB data are passed through a

sequence of image signal processing blocks to finally produce YCbCr 4:2:2 output data. Image signal

processing includes such operations as gamma correction, defect correction, low pass filter, color interpolation,

edge enhancement, color correction, contrast stretch, color saturation, white balance, exposure control and

back light compensation. Internal functions and output signal timing can be programmed simply by modifying

the register files through 2-wire serial interface.

[ Fig. 2 ] Block Diagram

ST

DB

Y

Effective Pixel array

690 × 512

CDS<0:803>

Column decoder

Row

decoder

ADC<0:803>

…

…

2-w

ire s

erial

inte

rface

Regis

ters

SSDA

SSCL

Timing control

Bia

s / A

DC

contr

ol

…

Image S

ignal

Pro

cessin

gBaye

r R

GB

8bits Y/UV or 9bits Bayer

RS

TB

X1

9

Analog Control signal

Digital Control signal

PCLK

HSYNC

VSYNC

Digital Control signal

pclk

Hsync

Vsync

Data

9

Contr

ol re

gis

ter

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[ Fig. 3 ] Default data structure of frame and window. ( Top view )

Origin ( 0, 0 ) of the frame is at the upper right corner. Size of the frame is determined by two registers :

framewidth( Reg.A-04h, A-05h ) and frameheight( Reg.A-06h, A-07h ). One frame consists of framewidth + 1

columns and frameheight + 1 rows. framewidth and frameheight can be programmed to be larger than total

array size. Default window array of 640 x 480 pixels is positioned at ( 110, 16 ). It is possible to define a

specific region of the frame as a window. Pixel scanning begins from ( 0, 0 ) and proceeds row by row

downward, and for each line scan direction is from right to the left. Hsync signal indicates if the output is from a

pixel that belongs to the window or not. There are two counters to indicate the present coordinate of frame

scanning : Frame row counter and frame column counter. Counter values repeat the cycle of 0 to frameheight ,

and 0 to framewidth respectively. The counter values increase at the pace of pixel clock (PCLK), which does

not change as the frame size is altered. The pixel data rate is fixed and is independent of frame size(frame

rate). [ Table 3 ] shows windowx, y start/stop( Reg.A-08h ~ A-0Fh ) registers value for default window and

maximum window.

▶ Frame Structure and Windowing

POA030D VGA Frame Structure

(0,0)

(857,523)

Effective window(640 x 480)

Effective Pixel(656 x 496)

102

(102,0)

(757,503)

8

8

8

8

640

480

8 8

Row OBP66

12

(102,8)

(110,16)

(749,495)

(757,511)

* Total Pixel : 656 x 512

34

Column OBP

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▶ Data Formats

[ Fig. 4 ] Bayer Color filter pattern

R G R G R G

G B G B G B

R G R G R G

G B G B G B

R G R G R G

G B G B G B

Y1 V1U1 Y2 U3 Y3 V3 Y4 …

[ Fig. 5 ] 4:2:2 YUV data sequence.

Pixel array is covered by Bayer color filters as can be seen in

the [ Fig. 4 ]. Since each pixel can have only one type of filter on it,

only one color component can be produced by a pixel. POA030D

provides this Bayer pattern RGB data through an 8bit channel. It takes

one PCLK to pass one pixel RGB data to output bus. But since it is

necessary to know all 3 color components R, G, B to produce a color

for a pixel, the other two components must be inferred from other pixel

data. For example, G component for a B pixel is calculated as an

average of its four nearest G neighbors, and its R component as an

average of its four nearest R neighbors. This operation of inferring

missing data from existing ones is called the color interpolation. Color interpolation produces an

undesirable artifact in image. Sampling nature of color filter can leave an interference pattern around

an area with repetitive fine lines. POA030D adopts a low pass filter to prevent the interference patterns

( called Moire pattern) from degrading the image quality too much. After color interpolation, every pixel

has all three color components. These three color components R, G, B can be routed to 8 bits output

pins in such a way RGB565. It takes two PCLK’s to pass one pixel RGB data to output bus.

It is possible to extract monochrome luminance data from RGB color components and the conver-

sion equation is : Y = 0.299R + 0.587G + 0.114B where R,G and B are gamma corrected color

components. And the color information is separated from luminance information according to following

equations.

U = 0.492 ( B – Y ), V = 0.877 ( R – Y )

Since human eyes are less sensitive to color variation than to luminance, color components can be

sub-sampled to reduce the amount of data to be transmitted, but preserving almost the same image

quality. POA030D supports 4:2:2 YUV data format where

U and V components are horizontally sub-

sampled such that U and V for every other pixel

are omitted. POA030D also supports ITU-R

BT.601 YCBCR format which is a scaled, offset

version of YUV. Y is the same in both formats but

the CBCR is formed as follows.

CB = 0.564 ( B – Y ) + 128

CR = 0.713 ( R – Y ) + 128

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▶ Data and Synchronization Timing

[ Fig. 6 ] shows the default data sequence of POA030D. In [ Fig. 6 ] Hsync / PCLK polarity can have any

combinations possible. Data can be latched at the rising or falling edge of PCLK. Hsync can be set to be active

high or active low. The sequence default YUV data is [ U,Y, V, Y, …] for common even / odd rows.

The width of Hsync can be programmed by windowx1 / x2( Reg.A-08h, 09h, 0Ch, 0Dh )

and given by

Hsync Width = windowx2 - windowx1 + 1

Data value can be selected in Invalid or blanking region . ( Reg.B-AEh ~ B6h )

The default sequence Bayer data is [RGRG…] for even rows and [GBGB…] for odd rows.

[ Fig. 7 ] Timing diagram for Hsync, MCLK, PCLK and Data ( Bayer mode )

[ Fig. 6 ] Timing diagram for Hsync, MCLK, PCLK and Data ( YUV mode : default )

Hsync Width = window x2 – window x1 + 1 (pclk)

U Y V Y U Y V YYAB FFU

Hsync

MCLK

PCLK

DATA

Hsync Width = window x2 – window x1 + 1 (pclk)

Hsync

MCLK

PCLK

RAB FFDATA(E) G R G

GAB FFDATA(O) B G B

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In [ Fig. 8 ], Vsync polarity also can have any combinations possible and can be set to be active high

or active low. The width of Vsync can be programmed by vsyncstart / vsyncstop( Reg.A-10h ~ 13h ) and

given by

Vsync Width = ( vsyncstop – vsyncstart ).

The width of Vreference can be programmed by register windowy1 / y2( Reg.A-0Ah, 0Bh, 0Eh, 0Fh )

and given by

Vreference width = ( windowy2 - windowy1 ).

[ Fig. 8 ] Timing diagram for Vsync and Hsync

Vreference

Vsync(def.)

Vreference width = ( window y2 –window y1 )

Vsync width = ( vsyncstop – vsyncstart )

Hsync

1 line time

= ( framewidth + 1 ) x pclk

Hsync Width =

window x2 – window x1

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POA030D



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▶ Scaling

Effective Image. # of columns = reg_window_x2 - reg_window_x1 +1

Effective Image. # of rows = reg_window_y2 - reg_window_y2 + 1

( reg_window_x1, reg_window_y1 )

minimum = (1, 1)

( reg_window_x2, reg_window_y2 )

maximum = (648, 488)

# of columns

# of rows

0 32 64

0

32

64

Scaled image sampling points

X Sampling points = reg_scale_X * P

Y Sampling points = reg_scale_Y * Q

Where, P, Q is integer (0, 1, 2, ...)

Example

Reg_scale_x = 40

Reg_scale_y = 48

Full image pixel locations

X points = 32 * M

Y points = 32 * N

Whrere, M & N is integer ( 0, 1, 2, ...)

[ Fig. 9 ] Free Scaling

[ Fig. 10 ] Effective Image Size

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[ VGA / CIF scaling case : default ]

[ QVGA / QCIF scaling case ]

VSYNC

HSYNC

VSYNC

HSYNC

[ Fig. 11 ] Timing diagram for VSYNC and HSYNC ( scaling modes )

[ QQVGA scaling case ]

VSYNC

HSYNC

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[ Fig. 12 ] Timing diagram for PCLK and Data ( scaling modes )

[ VGA / CIF scaling case : default ]

U Y V YAB U U Y V YY U

MCLK

PCLK

DATA U Y V YY FF

[ QVGA / QCIF scaling case ]

UAB

MCLK

PCLK

DATA V V Y FFY Y U

[ QQVGA scaling case ]

UAB

MCLK

PCLK

DATA Y Y FFV

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▶ I2C Master

POA030D supports I2C mater function. User tuning registers of POA030D and NTSC/PAL encoder

can be set by I2C EEPROM initially. After reset time POA030D tries to access I2C EEPROM whether it has

connected. If the connection has accomplished POA030D reads data from I2C EEPROM and sets its

registers. [Fig. 13] shows how to connect POA030D and I2C EEPROM.

[Fig. 13] Connection of I2C EEPROM and NTSC / PAL Encoder

User can select NTSC or PAL mode using NTSC pin. If NTSC pin is connected to VCC, I2C master

operate NTSC mode. If NTSC pin is connected to ground, I2C master operate PAL mode. [Fig. 19] shows

that example of configuration I2C EEPROM.

VCC

POA030DI2C EEPROM

NTSC/PAL

Encoder

VCC

SSDA

SSCL

RSDA

RSCL

SCL

SDA

SCL

SDA

VCC

NTSC

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ADDRESS

(HEX)CONTENT

EXAMPLE

(HEX)

000 Device_ID_O (MSB 7bit) DC

001 Device_ID_1 (MSB 7bit) 66

002 Dev_0_global_seg_start_addr_h 01

003 Dev_0_global_seg_start_addr_l 00

004 Dev_0_global_seg_stop_addr_h 01

005 Dev_0_global_seg_stop_addr_l FF

006 Dev_0_ntsc_seg_start_addr_h 02

007 Dev_0_ntsc_seg_start_addr_l 00

008 Dev_0_ntsc_seg_stop_addr_h 02

009 Dev_0_ntsc_seg_stop_addr_l FF

00A Dev_0_pal_seg_start_addr_h 03

00B Dev_0_pal_seg_start_addr_l 00

00C Dev_0_pal_seg_stop_addr_h 03

00D Dev_0_pal_seg_stop_addr_l FF

00E Dev_1_global_seg_start_addr_h 04

00F Dev_1_global_seg_start_addr_l 00

010 Dev_1_global_seg_stop_addr_h 04

011 Dev_1_global_seg_stop_addr_l FF

012 Dev_1_ntsc_seg_start_addr_h 05

013 Dev_1_ntsc_seg_start_addr_l 00

014 Dev_1_ntsc_seg_stop_addr_h 05

015 Dev_1_ntsc_seg_stop_addr_l FF

016 Dev_1_pal_seg_start_addr_h 06

017 Dev_1_pal_seg_start_addr_l 00

018 Dev_1_pal_seg_stop_addr_h 06

019 Dev_1_pal_seg_stop_addr_l FF

01A Dev0_wait_command 03

01B Dev_1_wait_command E4

01C~0FF ... -

100~1FF Dev_0_global_seg -

200~2FF Dev0_ntsc_seg -

300~3FF Dev0_pal_seg -

400~4FF Dev_1_global_seg -

500~5FF Dev1_ntsc_seg -

600~6FF Dev1_pal_seg -

700~7FF ... -

[Fig. 14] Example of Configuration I2C EEPROM

I2C slave address for POA030D

I2C slave address for NTSC/PAL Encoder

EEPROM address for turning registers of POA030D

► global_seg means that segments which is used in

both NTSC & PAL mode.

► ntsc_seg means that segments which is used in

just NTSC mode.


just PAL mode.

► Rom address should be smaller than 7FFh (HEX)

In addition, start address should be smaller than stop

address.

EEPROM address for turning registers of NTSC / PAL encoder


both NTSC & PAL mode.

► ntsc_seg means that segments which is used in

just NTSC mode.


just PAL mode.

► Rom address should be smaller than 7FFh (HEX)

In addition, start address should be smaller than stop

address.

Wait command for POA030D

Wait command for NTSC / PAL encoder

Segments of tuning registers for POA030D

Segments of tuning registers for NTSC / PAL encoder

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▶ LED Control

POA030D provides LED control function with ambient light sensor (analog current output type) and IR

LED. [Fig 15] shows that connection of illumination sensor and IR LED.

ADC

LED Control

Block

POA030D

ISIN

LED1

LED0

Ambient Light Sensor

(Analog Current Output Type)

IR

LED

[Fig. 15] Connection of illumination sensor and IR LED

There is several tuning registers for LED control block. For more information of tuning registers,

please refer to register descriptions (Reg. B-54h~59h).

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Absolute Maximum Ratings *

Table 3. DC Characteristics

* Excessive stresses may cause permanent damage to the device.

HVDD,AVDD Supply Voltage ------------------------------------------------ -0.3V to 4.5V

DVDD Supply Voltage --------------------------------------------------------- -0.3V to 2.5V

DC Voltage at any input pin ---------------------------------------------------- -0.3V to HVDD+0.3V

DC Voltage at any output pin --------------------------------------------------- -0.3V to HVDD+0.3V

Storage Temperature ------------------------------------------------------------ -40C to + 125 C

Symbol Descriptions Min Typ Max Unit

VDDD Digital VDD voltage relative to GND( DGND) level. 1.5

1.8V

VDDA Analog voltage relative to GND(AGND) level. 2.8 V

HVDD High VDD(HVDD) voltage relative to GND(DGND) level.

1.5

1.8

2.8

3.3

V

IDDD

Supply current at 30 fps. Currents are programmable through 2-

wire serial interface. TBD mA

DVDD=1.8V(1.5V) TBD mA

AVDD=2.8V TBD mA

HVDD=2.8V TBD mA

IDDS

Standby supply current@

DVDD=1.8V(1.5V)/AVDD=2.8V/HVDD=2.8VTBD uA

VIL1 Input voltage LOW level0.2*HV

DDV

VIH1 Input voltage HIGH level 0.8*HVDD V

VIL2 Input voltage LOW level for rClk, rData.0.2*HV

DDV

VIH2 Input voltage HIGH level for rClk, rData 0.8*HVDD V

CIN Input pin capacitance 10 pF

VOL1 Output Voltage LOW 0.1*HV

DDV

VOH1 Output Voltage HIGH 0.9*HVDD V

VOL2 Output Voltage LOW level for rClk, rData. 0.2 V

VOH2 Output Voltage HIGH level for rData. HVDD-0.2 V

IIN Input leakage current 0.005 1 uA

IOT Output leakage current 0.005 1 uA

▶ Electrical Characteristics

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Table4. AC Characteristics (In case of HVDD=2.8V)


fMCLK Master clock Frequency TBD MHz

duty Master clock duty cycle TBD %

t1 Master clock rise/fall time TBD ns

t2 PCLK rise/fall time TBD ns

t3 PCLK rising edge to HSYNC TBD ns

t4 PCLK rising edge to digital output TBD ns

t5 MCLK rising edge to PCLK rising edge TBD ns

t6 PCLK rising edge to VSYNC TBD ns

Cload=16pF

t5

t1 t1

50%

90%

10%t2

t3t3

t4

MCLK

PCLK

HSYNC

Digital

Output

t5

t1 t1

50%

90%

10%t2

t6t6

t4

MCLK

PCLK

VSYNC

Digital

Output

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Symbol Parameter Notes Min Typ Max Unit

Sens Sensitivity 1) TBD V/Lux.sec

Vsat Saturation Level 2) TBD V

Vdrk Dark Signal 3) TBD mV/sec

DR Dynamic range 4) TBD dB

Table 5. Electro-Optical Characteristics ( @ 60degree )

Notes :

1) This value comes from the wafer test. The calculation sequence is as follows.

(1) read the saturation level from evaluation pad

(2) calculate One LSB.

(3) Read output signal of Green pixels under illumination with output signal equal to 50% of

saturation signal.

(4) Read the Luminance and Integration Time when 50% of saturation signal.

(5) Calculate the sensitivity using (1)~(4)

= (the signal of Green pixels * one LSB ) / (luminance * integration time)

2) Read the value of evaluation pad when all pixels are saturated in condition

3) Measured at the zero illumination.

(1) read the dark signal average of all pixels for minimum integration time

(2) read the dark signal average of all pixels for maximum integration time

(3) [Dark signal @ maximum integration time] – [Dark signal @ minimum integration time]

(4) convert to mV/sec unit

4) For frame rate=7.5 fps

20*Log [Saturation Signal /Dark signal] [dB]

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Power-On Sequence

DVDD

HVDD

AVDD

MCLK •••

RSTB

t1

t2

t7 t9

DATA<8:0>,

HSYNC,

VSYNC, PCLKunknown

STDBY

Output=Hi-Z Normal operation

Standby Mode

SCLK,

SDATA(Reg.B-1Ah[3] = ‘0’)

Sensor initialization

Output=Hi-Z

Output Hi-Z release

Power-Off Sequence

DVDD

HVDD

AVDD

t6

t5

Table6. Recommended Power-On/Off sequence


t1 From DVDD rising to HVDD rising 0 ns

t2 From HVDD rising to AVDD rising 0 ns

t5 From AVDD falling to HVDD falling 0 ns

t6 From HVDD falling to DVDD falling 0 ns

t7 From HVDD rising to initial mclk rising 0 ns

t8 From RSTB falling to AVDD falling 0 ns

t9 Minimum reset time 8 x MCLK period

(2) To make output Hi-Z state in power-down mode, set Reg.A-59h[7] to ‘1’ before starting power-down mode

(2)

(1) Output state is Hi-Z in default. To release output Hi-Z state, set Reg.A-59h[6] to ‘0’

(1)

t8RSTB

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PowerPoint 프레젠테이션eyeontech.1004hp.com/product/images/POA030D.pdf · 2013-02-28 · Rev 0.1 POA030D 1/4 inch VGA Single Chip CMOS Image Sensor with 640 X 480 Pixel Array