PLX Confidential 1

Silicon without Software is Just Sand

Potential PLX Gen2 Flip-Chip Device PLL Interaction with PCB

REXT Link Issue

PEX8648 & PEX8696 Families of Products

April - 2012

PLX Confidential 2

Products Impacted

PCIe Gen 2 Switches with Flip-chip BGA Package

PEX 8648 Family

• PEX 8648, 8647, 8632, 8624, 8616, 8612

PEX 8696 Family

• PEX 8696, 8680, 8664, 8649, 8636, 8625

PEX 8619 family NOT IMPACTED (wire-bond package)

PLX Confidential 3

Issue Overview

What has been Observed

A link condition causing bit errors, and or link drops in

which the root cause has been isolated to 5Ghz noise

injected into the PLL tank circuit.

Reason for Injection

Underlying root-cause is a trace within the device that

allows SerDes PLL (5Ghz) coupling.

Identified trace is a low frequency, low bandwidth BIAS

circuit that is not affected by (5Ghz) PLL energy.

This circuit trace, however, extends outside the device

and on the customer PCB where it is terminated by an off

chip calibration resistor - REXT

The external path allows for 5Ghz coupling back into the

PLL. Coupling level a function of PCB design and external

source injection.

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Root Cause – REXT

PLX Gen2 devices use an LC tank for TX and

RX data clocking

Tank operates at 5Ghz

One tank for every SerDes Octal

Routing of REXT thru SerDes IP allows for

coupling of 5Ghz tank energy onto the rext

trace that extends onto PCB

The 5Ghz energy in itself not a problem

Mixing of any external 5Ghz sources of proper

phase/frequency can cause loop instability

Instability leads to link errors

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Observed Failure Modes

Two injection modes

First mode: Close proximity REXT resistor placement

• REXT resistors in close proximity allow 5Ghz energy of one PLL to

couple another

• Solution – do not consolidate REXT PCB trace routes

Second mode: High frequency common mode from

external transmitters

• Common mode is the result of distortion and/or trace imbalance of

signals at the PLX receiver balls as RX package balls are in close

proximity to REXT balls, injection can occur

• Injection magnitude is a function of PCB design, external

transmitter distortion, PLX device PCBs in excess of 0.062”

standard PCIe add-in thickness more susceptible.

• Solution – Alter PCB design and via placement. Short high

frequency signal path for exiting designs. (see PLX design

guide/notes)

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Customer Symptom

Link Error Symptoms

Although all boards are same but only a percentage of

cards failed

• Failure did not track card swap or chip swap

• Temp, voltage variation, chip variation, power plane

variance, etc masked problem – ‘affect one not the other’

• Synchronous operation masked failure mode

• Phase rotation improved observation problem

Root Cause

• REXT resistor placement in close proximity to each other

resulted in 5 GHz tank octals mixing/steering and link

instability

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Customer Symptom Link Error Symptoms

Although all boards same, only a percentage of cards fail

• Pre-Production test flagged system link training issue.

• Degree varied. Some cards had RX errors. Others Link down.

• RX/Link errors most prominent on receiver opposite PLX device.

• Small adjustments to power plane, signal vias, etc effect failing system.

Could ‘fix’ one board, but not another.

Root Cause

• Identified a particular add-in card increased link errors

• Card TX produced higher amounts of high frequency (5Ghz) common

mode (TX) noise back into system board.

• via coupling of these High-speed signal lines transferred this energy into

nearby REXT traces and into tank.

• Phase rotation / capacitor test confirmed PLL tank issue

Production solution included new layout to reduce coupling

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Example of External Tank Disturbance

Idea of Acceptable operation Poor Jitter performance - unacceptable

High Impedance probe of REXT(-)

Comparison of operational card versus failed card under proper phase

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Test Methods

Creating Failure Condition

Synchronous links can make observation difficult –

disturbance is phase and magnitude dependent

• Perform a phase rotation of the 100Mhz reference clock to

check for link instability. (requires separating each side of

the link onto different 100Mhz clock domains)

• Failure can be both PCB and opposite link partner

dependent – to validate, ensure same link components.

• Low level link instability will show RX correctable errors as a

function of phase. This is improper link operation.

• Lower levels of instability typically result in bit errors on side

of link opposite the PLX device (tank instability).

Ground REXT_B near chip ball, rotate phase and confirm

link error free.

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Short Term – PCB Mitigation

Issue can be mitigated in the following ways

Existing PCB rework

• Shorting the injection path by either grounding or placing a

0.1uf capacitor near the REXT_B ball location.

• Capacitor keeps the exact same DC path, however

grounding the device ball results in minimal change (ie

typically 5-10mV ) to TX output of the chip and is an

effective alternate solution for manufacturing.

New PCB design

• Keep REXT bias resistors separated.

• Use alternate via placement with additional ground shielding

to improve rejection of external coupling – PLX Design

Guidelines - PCB Layout Review Guide

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Long term Mitigation - Package

PCB

Pkg Substrate

Die

PCB

Pkg Substrate

Die

Package fix

PCB

Pkg Substrate

Die RextB

PCB fix Before

Package change to minimize ability

of external sources to corrupt PLL

• Change requires no modifications

to existing PCB designs

PLX Confidential 12

Maximizing Detection / Correction Production level chip screening

Conditions to create tank resonance combination of chip and

board(s)

No chip level production screen possible

System Inventory retro fit

REXT capacitor retrofitted to present system inventory and/or

available cards (…likely manufacturing concerns)

Grounding a simpler manufacturing option

Early detection

Monitor field for higher levels of RX errors

Quick validation Stress test ( New Design)

Can expedite the QA process by testing design of new

cards/system with similar phase check.

Exposes ability of synchronous systems to mask issue