Post-layout PCB Check and Simulations for Signal

Integrity Jiang Li

1, Yingzhi Wu

2

Cadence Design Systems

2655 Seely Ave., San Jose, CA 95134, USA 1 joyli@cadence.com

2 yzwu@cadence.com

Abstract — Overviews of comprehensive geometry-based and

electrical-based PCB layout checks are given. Layout check

results are then compared with signal integrity simulations at

various levels: with vs. without trace couplings; with vs. without

via couplings; ideal PDN vs. non-ideal PDN; partial channel vs.

full channel. A DDR3 memory design is used as an example.

I. INTRODUCTION

Today‟s PCB designers and signal integrity engineers have

a variety of design and analysis technology choices from

many different tools. When it comes to ensuring the signal

integrity performance of their design, one question they ask a

lot is, “Which one should I use?”

The answer is it depends.

There are two primary categories of methods for evaluating

the electrical performance of PCB layouts as shown in Figure

1. The first is the geometry-based physical layout check, or

simulation-based electrical layout check; the second is the

signal integrity simulations in time-domain using the device

models.

From application point of view, layout geometry check (G-

check) should be considered first when it comes to large scale,

board-level signal integrity assurance. G-check is relatively

easy to set up and get results. The disadvantage of G-check is

that it cannot determine the impact if some violations exist.

This often leads to unnecessary over-design or inadequate

under-design.

Layout electrical check (E-check) can also be applied to

large scale PCB signal integrity applications. The advantage

of E-check is that the results are accumulative, and combined

checking results are presented in time-domain terms of „mv‟

and „ps.‟

Signal integrity simulations with device models can provide

more accurate results if all the couplings between traces, vias

and planes are considered with non-ideal power and ground

supplies also taken into account. But the user time and

computer resources required for board level time-domain

simulation can make this approach impractical for time

constrained product development flows.

Generally speaking, PCB E-check is more desirable than G-

check; results are more accurate for full bus simulation, with

trace/via coupling and non-ideal PDN all considered. But not

all design decisions need the most accurate results from the

most comprehensive and most complicated simulations.

Our experiences show that all levels of PCB layout checks

and simulations are useful, if used correctly when designers

know what they are looking for. Therefore, it is important for

designers to know what signal integrity effects are, and are not,

included when they setup layout checks or signal integrity

analysis.

Fig. 1. PCB layout check and simulations at different levels

In this paper, PCB layout checks and simulations are

reviewed with results showing

Layout geometry check (G-check) vs. electrical

check (E-check)

Trace/via coupling included vs. not included

Ideal PDN vs. non-ideal PDN

Partial channel SSO vs. full channel SSO

A memory subsystem design is used as an example. It has 1

controller, 4 DRAMs and 77 nets as shown in Figure 2.

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Fig. 2. PCB layout check example

II. THE ADVANTAGE OF PCB LAYOUT CHECKS

Performed at a single layout level without IC device models,

PCB layout checks can be done at 2 levels: geometry-based

physical checks and simulation-based electric checks, with

details shown in Figure 3.

Fig. 3. PCB layout physical-check and electrical-check

Using layout checks, users can screen boards to identify

potential problems for further analysis, to investigate signal

integrity impact of design rule violations and trade-offs, and to

compare against part of the design that has been fully analysed.

PCB layout checks are widely used to enable designers to

quickly analyse the performance of their design relative to

known-good designs without the overhead of involving silicon

models. In such cases, despite the lengthy design guidelines

and availability of reference designs, customers‟ designs often

deviate from the reference design, sometimes due to pressure

of cost cutting, or due to human error.

Compared with simulations, the major advantages for

layout checks are

1. No device models are needed

2. Relatively easier to setup, and faster to get results

3. Most likely to be performed by layout engineers

and less experience Signal integrity engineers

4. Practical for channel-level, even board-level

checks.

Due to these advantages, more and more users are

integrating PCB layout checks into design and sign-off

process.

III. GEOMETRY-BASED PHYSICAL LAYOUT CHECK

DRC in the layout tool is the starting point of PCB layout

checks. Although it is well integrated with the layout, it

cannot be used as a good layout performance indicator due to

limited layout factors affecting signal integrity that are

considered in DRC.

Designers often want more comprehensive geometry based

layout checks with additional information, for example

Not just trace impedance, but also trace reference,

reference discontinuities, impedance threshold and

violations

Not just trace couplings based on spacing, but coupling

with dielectric material property considered, coupling

threshold and

Not just trace physical length, but also trace electrical

length

Easy to read tables and chart showing results with easy

reference to layout such as cross probing

Using the memory sub-system example, the G-check

results are shown in Figure 4 – 6. The trace discontinuity and

the resulting high impedance trace section would be next to

impossible to find without G-check.

Fig. 4. G-check results for trace impedance

Fig. 5. G-check results for trace coupling

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Fig. 6. G-check results for trace impedance/impedance overlay in layout

Highly desirable features for G-check are easy to setup,

easy to compare results amongst similar nets, and shareable

G-check report.

IV. SIMULATION-BASED ELECTRICAL LAYOUT CHECK

Once violations are identified by a G-check, users have 2

choices: fix it, or ignore it. Even though most users want to fix

the violations, not all violations can be easily fixed. For

example, trace coupling violation fix needs more routing real

estate, reference discontinuity fix needs solid power/ground

planes, both pointing to adding layers as solution which will

increase cost.

When adding additional layers is not an option, designers

want to quantify the impact of impedance/coupling violations

in terms of “mv” and “ps,” so they can make possible

tradeoffs and decide if the violation can be ignored. This is

when they need an E-check.

E-check is based on time-domain simulations that consider

crosstalk and non-ideal power/ground. Since silicon models

are not involved, E-checks are relatively easier to do for a

large number of nets, making them practical for complex real-

world PCB designs. E-check results include:

Tx/Rx waveforms and worst case NEXT/FEXT

waveforms;

SI performance metrics based on signal magnitudes, ISI

(inter-symbol interference) and crosstalk at receivers.

Figure 7 shows E-check results for one data Byte net group.

Figure 8 shows that G-check identified tight coupling of

DQ10, and the subsequent E-check quantifies that as

additional 100mv xtalk compared with loosely coupled net

DQ13.

Highly desirable features for E-check are also easy to set up,

easy to compare results amongst similar nets, and shareable E-

check reports.

Fig. 7. E-check results

Fig. 8. Quantify tight couplings using FEXT/NEXT in mv

V. SIGNAL INTEGRITY SIMULATIONS

The signal integrity performance of a PCB design cannot be

determined by PCB design alone without the context of

devices. In signal integrity analysis, a device model is used in

simulation, and a device data sheet is used to determine if

results meet the requirements.

There are many different ways designers run their signal

integrity simulations. From PCB design point of view, we can

put these simulations in 3 levels as shown in Figure 9.

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Fig. 9. PCB design signal integrity simulation levels

Power supply locations are in Figure 10 and Figure 11. In

Level-1 and Level-2 simulations, the ideal VDD voltage

sources are assumed to be at the devices pins, and ideal VTT

voltage sources are assumed to be at the pull-up resistor pins.

In Level-3 simulations, ideal power supply is at the where

VRM component is.

Fig. 10. Ideal vs. Non-ideal VTT power supply

Fig. 11. Ideal vs. Non-ideal VDD power supply

Using the memory sub-system example, our DDR3-1600

simulations range from level-1 single-line no-coupling

simulations for a few signals, to level-3 full blown simulations

for full channels with none-ideal PDN.

The results in Figure 12 show that

Trace coupling had only small effect to signal

The noise on the power rail is larger with full data bus

switching, SSO push out is about 80ps

The major factor affected signal quality is non-ideal

PDN

Fig. 12. Simulation results for level-1, level-2, and level-3 partial & full bus

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Figure 13 showed comparison of level-3 full channel

simulation results for DQ10 and DQ13. Similar as in E-check,

it also showed DQ13 signal quality is better compared with

that of DQ10.

Fig. 13. DQ10 and DQ13 results comparison from full channel simulation

VI. CONCLUSION

Today‟s PCB designers and signal integrity engineers have

a variety of design and analysis technology choices from

many different tools: from geometry-based PCB layout check,

to simulation-based electrical layout check, to complicated

full blown simulations for the entire channel considering all

couplings and non-ideal pwr/gnd effects.

All levels of checks and simulations can be useful if used

correctly. So it is extremely important for designers to know

what they are looking for, and how to get what they want

using the PCB checks and simulations at the adequate levels,

no more, no less.

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