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CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Advances in 3D Simulations of
Chip/Package/PCB Co-Design
Richard Sjiariel, CST AG
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Signal Integrity and timing
Power Integrity
and noise
analysis
EMC/EMI and radiation
Thermal analysis
and stress
Co-design environment
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Analysis across Chip/Package/PCB
Nanometer scale Multi Gb PCB systems
Need for co-design
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Co-design
Simplistic approach to CPB co-simulation may miss critical physics of the
chip-package and package-board interactions.
High-order electromagnetic interactions in the CPB system have a critical
impact on the system integrity.
Board/Package
Chip/interposer
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
1) Cascading approaches
• field based (continuity of E/H field and reference
plane where propagating more is TEM) - “PCB and
Package Co/Design and Co/Optimization”
• S-parameters based considering all pins
(signal/PWR/GND vias)
2) Simulation of the full system (Full 3D EM solvers or hybrid
solvers)
Co-design methodologies
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
S-Parameter Based
Source: Zhaoqing Chen, “General Co-Design Approach to Multi-Level Package Modeling based on Individual
Single-Level Package Full-Wave S-Parameter Modeling Including Signal and Power/Ground Ports”, ECTC 2012
Electric wall and ports at the interface
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Test Case (1/2) PCB + Package
Package PCB
Signal vias PWR/GND vias PWR/GND vias
Signal vias
Signal vias
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Test Case (2/2) Package
PCB
The effect of the discrete port is de-embedded from the S-parameters of both PCB
and package using c=-0.11pF
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Results: Full Model vs. Cascaded
(+) Very small difference between full model vs. cascaded model
(-) Methodology difficult to use (prone to errors) when dealing with realistic
models with many signal/power/GND vias
Ins./return loss NEXT/FEXT
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
PCB/Package Co-Design
Pkg1: 2.5x2.5cm 21 layers
Pkg2: 2.8x2.5cm, 21 layers
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Geometry Details
1
2
3
4
1, 2 input-output
3, NEXT
4, FEXT
Multiple 3D geometries and RPDs: PTH BGA and bumps Micro vias ..etc
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
PCB vs Channel (PCB + Package)
S11 full channel
S21 full channel
S21 PCB
only
S11 PCB
only
Insertion loss – S21 - 5 to 8dB difference in attenuation
Return loss – S11 – large discrepancy in range 2-8GHz showing
underestimation of impedance match for PCB model
pkg1
pkg2
PCB
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Statistics
Hardware(Nehalem) GPU Simulation Time/h Speed-up factor
1 node 0 96 1
8 node cluster 0 19 5.1
4 node cluster 8 3.2 30
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Chip Modeling
CAD EM modeling
CPM/SPICE
SPICE
IBIS
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Chip/Package/Board (CPB) Co-Design
The anti-resonance peak occurs at the cross point of package inductance
and chip capacitance. This is called “chip-package anti-resonance.”
Source: R. Kobayashi et al, “Effects of Critically Damped Total PDN Impedance in Chip-Package-Board Co-Design”,
IEEE EMC Conference, Pittsburgh 2012.
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
IBIS/SPICE Workflow Example
PKG Socket PCB Fixtures DIE
Power
Plane
Signal
Net Pogo
Pin
SPICE
IBIS
Power
Plane
Signal
Trace
Scope
SMA
Cable
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
3D Model
372x205mm large, 17 layers PCB
Epsr=3.9, tgδ0.035
6 layers package with bond wires
Victim Line
Aggressor Lines
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Full System simulation
PCB + package+ pogo
pin
Chip/ASIC
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Comparison: Insertion Loss (Single Ended)
Package + board + all nets
Package + board + single net
Package only
Package + board + all nets = 3.16db
Package + board + single net +-2.9db
Package + board + all nets = 3.16db
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Transient Response – Co-Simulation
Port 17 represents an output result at PCB More realistic result helps
to find the correct parameter for equalizer
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Surface Currents
Surface current at 1GHz
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Time Domain Field Monitor
Strong coupling
with neighbor
nets
Package/pogo
pin to PCB
(vertical)
coupling
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
A CPM™ (Chip Power Model) is a compact SPICE model of the full-chip power
delivery network (PDN).
It contains spatial and temporal current switching profiles, as well as
parasitic of the non-linear on-chip devices
SPICE/CPM
+
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
CPM model validation
Automatic assignment
of current
profiles/ports
CST DS results SPICE results
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
SPICE/CPM Workflow Example
PCB package
die
86x86mm
6 layer PCB
epsr=3.57, tgδ=0.025
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
CPB System Co-Simulation
PCB + package
SPICE + Current
profiles
Drivers (IBIS)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Current Profiles
Switching current at chip
Currents feeding into package
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Field Monitor
Current seems to
be confined in
island, but it
progressively
couples to the
rest of the
structure
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Surface Current Distribution
f=1GHz f=1GHz
f=10GHz f=10GHz
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
EMC/EMI Analysis
Farfield
monitor
probes at 3m
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Importance of chip/package/board (CPB) co-design is highlighted and its integration into various simulation workflows is discusses True transient co-simulation is a key feature for CPB
co-design 3D packages with embedded chips
3D system integration
3D full wave simulation is only choice for accurate results
Summary