Post-Layout Leakage Power MinimizationBased on Distributed Sleep Transistor

Insertion

Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii

ISLPED’04

Outline

Introduction Previous Work Algorithm Experimental Results Conclusion

Introduction

Bellow .13 process leakage dominates power consumption– Leakage power = exp(-q*Vt / K*T)

Leakage reduction methods– Dual Vt partition

– MTCMOS– State assignment

Low Vt logic module

sleep Virtual ground

high Vt

Outline

IntroductionPrevious Work Algorithm Experimental Results Conclusion

sleep

Previous Works

MTCMOS– Take a non-negligible amount of time to wake up

and re-activate sleep transistor. (long re-activation time)

Virtual ground

Low Vt logic module

Vdd

ONOFF

VDD-Vth 0DischargeRe-activation time

Stand by mode

Active mode

Previous Works

Distributed sleep transistor– Multiple sleep transistors are initiated.– A faster re-activation time

Most techniques presented at the logic and circuit level, and do not take placement information into account.

Cause severe wiring congestion

Outline

Introduction Previous WorkAlgorithm Experimental Results Conclusion

Sleep Transistor Insertion in row-based layout

Low Vt logic module

sleep Virtual ground

high Vt

Vdd

local wiring

Row Compaction & Area Penalty

Row Compaction

Area PenaltyAdd sleep transistor

Gate Clustering

Get Timing & floorplan Information from Layout

Select a sleep transistor

Check all rows?

Yes

No

Row Compaction

Select a cell

Update maximum current available at sleep transistor

Add cell to cluster

Timing violation?No

Yes

sleep Virtual ground

Gate1

Gate2

Gaten

available current at sleep transistor

According to available space

A gate by gate exploration of each row

How to Select Cell?

sleepVirtual ground

Gate1

Gate2

Gaten

ON Re-activation time

If Arrival time > Re-activation time, zero re-activation delay overhead are paid.

From primary output to primary input

OFF

Vdd

Discharge

Check whether the cell can be power-gated?

2.Current? 3.Timing? RT>RT_OH?1.Leakage Power?

Sleep Transistor Sizing

sleep

Virtual ground

Gate1

Gate2

GateN

CL

Outline

Introduction Previous Work AlgorithmExperimental Results Conclusion

Experimental Results(1/2)

Delay overhead constraint is set to 5% Area overhead constraint is set to 5%

Benchmark

Orig Opt ∆

PL[m

W]

Pdyn[m

W]

Ptot[m

W]

PL[mW]

Pdyn[mW]

Ptot[mW]

PL [%]

Pdyn[%]

Ptot[%]

Block1 0.11 0.29 0.4 0.02 0.32 0.34 78.9 -9.0 15.0

Block2 0.19 0.220.4

10.04 0.24 0.28 80.0 -10.1 31.0

Block3 0.16 0.310.4

70.04 0.33 0.37 74.6 -8.8 21.2

Block4 0.26 0.60.8

60.05 0.63 0.68 82.7 -5.0 18.6

Block5 0.12 0.290.4

10.03 0.32 0.35 78.9 -9.7 12.5

Block6 0.46 0.881.3

40.09 0.98 1.07 83.5 -12.4 20.1

Avg. 　 79.7 -9.6 18.9

Experimental Results(2/2)

Area Penalty

Benchmark Gates SleepArea_Orig [µm2]

Area_Opt

[µm2]∆[%]

Block1 1852 14 64912 66794 2.9

Block2 1916 14 65210 66710 2.3

Block3 2215 22 65053 66550 2.3

Block4 2267 13 65412 66524 1.7

Block5 2302 26 65918 68159 3.4

Block6 2612 20 70298 71703 2.0

Experimental Results(3/3)

Delay penalty

CellNo Leak Control Leak Control

∆Power[%]

∆Delay[%]PLk[mW] Delay[ps] PLk[mW] Delay[ps]

G1 7.761 132.3 2.717 137.0 65.0 -3.5

G2 7.881 132.2 2.371 135.0 69.0 -2.1

G3 11.278 120.8 1.466 126.1 87.0 -4.3

G4 1.951 161.3 0.547 166.3 71.9 -3.1

G5 1.988 158.3 0.467 165.3 76.5 -4.4

G6 2.161 161.0 0.737 168.3 65.8 -4.5

G7 4.967 130.3 0.745 135.1 85.0 -3.6

G8 5.704 185.0 1.254 189.0 78.0 -2.1

G9 1.136 146.7 0.353 152.5 68.9 -3.9

G10 1.968 240.0 0.446 248.0 77.3 -3.3

G11 4.967 182.6 0.745 188.2 85.1 -3.0

G12 3.054 369.6 0.916 385.7 70.0 -4.3

Outline

Introduction Previous Work Algorithm Experimental ResultsConclusion

Conclusion

Sleep Transistor Insertion :– Driven by a layout-aware cost function– Done with tunable performance and area penalty