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Point of Sale Terminal Design GuideApplication Note
May 1998
Order Number: 273170-001
Application Note
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Point of Sale Terminal Design Guide
Contents1.0 Introduction ..................................................................................................................5
1.1 Design Overview ...................................................................................................51.2 POS Terminal Design Features ............................................................................5
2.0 POS Terminal Design Overview ...........................................................................6
2.1 Core Components .................................................................................................72.1.1 Intel Embedded Processor Module EMBMOD133 ...................................72.1.2 Intel 82371SB PCI ISA IDE Xcelerator.....................................................72.1.3 Dynamic Random Access Memory (DRAM) ............................................72.1.4 Flash BIOS ...............................................................................................7
2.2 Peripheral components .........................................................................................82.2.1 Video Controller........................................................................................82.2.2 PS/2 Keyboard .........................................................................................82.2.3 RTC/NVRAM ............................................................................................82.2.4 Application Flash Memory ........................................................................82.2.5 Serial and Parallel Ports...........................................................................92.2.6 IDE Port....................................................................................................92.2.7 PCMCIA Interface ....................................................................................92.2.8 PS/2 Mouse Port ......................................................................................9
3.0 POS Terminal Design Details ..............................................................................10
3.1 Intel Embedded Processor Module (EMBMOD133)............................................103.2 Intel 82371SB PCI ISA IDE Xcelerator................................................................103.3 PCMCIA Connector.............................................................................................10
3.3.1 PCMCIA Host Adapter ...........................................................................103.3.2 PCMCIA Voltage Control........................................................................11
3.4 Serial and Parallel Communications ...................................................................113.5 Application Flash .................................................................................................123.6 Video Controller...................................................................................................123.7 Power ..................................................................................................................12
4.0 Design Considerations ..........................................................................................13
5.0 Summary......................................................................................................................13
6.0 Related Documents .................................................................................................13
7.0 Contact Information ................................................................................................14
A Bill of Materials .........................................................................................................15
B BIOS Checklist ..........................................................................................................19
C Schematics .................................................................................................................21
C.1 POS Terminal Reference Design Schematics ....................................................21
Application Note iii
Point of Sale Terminal Design Guide
Figures
1 POS Terminal Design Block Diagram ................................................................... 6
Tables
1 Intel Documents .................................................................................................. 132 Third Party Vendor Documents........................................................................... 143 POS Design Guide Bill of Materials .................................................................... 154 Hardware Design Specification ........................................................................... 195 Items connected to Super I/O ............................................................................. 196 Onboard Peripherals ........................................................................................... 207 PCI Routing Information...................................................................................... 208 Connectors.......................................................................................................... 209 Software Design Specification – Feature List ..................................................... 20
iv Application Note
Point of Sale Terminal Design Guide
our ustomer board
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1.0 Introduction
The point of sale (POS) terminal is an embedded PC platform with custom features designed for a retail and service environment. The major difference between a POS terminal and a normal PC is that a POS terminal is a cost-effective custom design, with unneeded PC features removed.
More and more industries are switching to POS terminals to replace cash registers, causing the market for POS terminal systems to grow enormously. Because POS terminal systems are usually connected to a network and often require a graphical user interface, high performance POS terminal systems are in demand.
The design described in this document was created to reduce the development cycle for point of sale terminal designers. This design provides a head-start in product development which can result in faster time to market.
Caution: The design has not been implemented in hardware. This document is for reference only. Customers are responsible for validating designs created using the information in this document.
1.1 Design Overview
This design is based on the Intel Embedded Processor Module. The processor used in the Embedded Processor Module is either a 133 MHz Intel® Pentium® processor with VRT technology (for the EMBMOD133) or a 166 MHz Intel® Pentium® processor with MMX™ technology (for the EMBMOD166). The EMBMOD133 module is used in this design.
The design closely emulates a PC environment and uses common, standard components. Fserial ports support peripherals, such as barcode scanners, digital scales, card readers and cprice displays. A printer and cash drawer can be connected using the parallel port and a keycan be connected using the PS/2 connector provided in the design.
Designers should check for device availability before designing-in any of the components inclin the document. This document describes the operation of the POS terminal design from a hardware perspective. BIOS and operating system operation is not discussed. The design habeen implemented in hardware.
This design guide is meant to be used together with the Intel 430HX PCIset Design Guide (order number 297467) and AP-757, Intel Embedded Processor Module Design Guide (order number 273120). Design issues covered in those documents are not repeated here. See “Related Documents” on page 13 for more information on how to obtain documents referenced in thisdocument. The schematics for this design are provided in Appendix B, “Schematics.” They aalso available in OrCAD format from the Intel Developer’s web site at www.intel.com.
1.2 POS Terminal Design Features
Key features of the POS terminal described in this design include:
• Intel Embedded Processor Module (EMBMOD133)
• 4-Mbyte application flash memory
• 64-bit video graphics controller with 2 Mbytes of DRAM
• Four serial ports
Application Note 5
Point of Sale Terminal Design Guide
• One parallel port
• PCMCIA socket
The Intel Embedded Processor Module contains:
• 133 MHz Intel Pentium processor with VRT technology
• 82439HX System Controller
• 256 Kbytes of L2 cache
• Clock generator
• Voltage regulator
2.0 POS Terminal Design Overview
Figure 1 is the block diagram for the POS terminal design.
Figure 1. POS Terminal Design Block Diagram
Pentium®
Processor Cache Tag
82439HXSystem Controller
PIIX3
Data Bus
Address Bus
Control
Control
PCI
DRAM Bus
Bus
ITP
VoltageRegulator
Clock Generator66, 33 MHz
66 MHz
72-B
it D
IMM
72-B
it D
IMM
Video SubsystemUSB
Bus Master IDE
National 87307 Super I/O*
PS/2 Mouse
PS/2 KeyboardFloppy Drive
IEEE 1284 Parallel Port COM2COM1
ISA BusXD BusBootFlash
Intel EmbeddedProcessor Module
PCIConnector
ISAConnector
PCMCIA
COM3/COM4Application
Flash
6 Application Note
Point of Sale Terminal Design Guide
2.1 Core Components
The core components of this POS terminal design are:
• Intel Embedded Processor Module, EMBMOD133
• Intel 82371SB PCI ISA IDE Xcelerator
• DRAM
• BIOS ROM
2.1.1 Intel Embedded Processor Module EMBMOD133
The Intel Embedded Processor Module EMBMOD133 is a high performance subsystem for use in embedded, industrial and communication applications where flexibility and the ability to upgrade is important.
The Intel Embedded Processor Module contains a Pentium processor, an 82439HX system controller (TXC), a 256 Kbyte L2 cache, a clock generator and a voltage regulator for the Pentium processor, all incorporated in a single board.
2.1.2 Intel 82371SB PCI ISA IDE Xcelerator
The Intel 82371SB is the PCI south bridge. It connects to the Embedded Processor Module via the PCI bus. It integrates many common I/O functions found in ISA-based PC systems:
• Seven-channel DMA controller
• Two 82C59 interrupt controllers
• 8254 timer/counter
• Power management support
2.1.3 Dynamic Random Access Memory (DRAM)
The POS terminal in this design provides two connectors for two 168-pin JEDEC, DRAM DIMM modules. The DRAM DIMMs will either be 3.3 V FPM or 3.3 V EDO type memory. The DIMM will provide a 64-bit or 72-bit interface directly to the Embedded Processor Module.
2.1.4 Flash BIOS
Flash BIOS is used to boot the POS terminal during power-up. The system flash BIOS is a 128 Kbyte, 12 V programmable flash device. The system is set up for in-circuit reprogramming of the BIOS, and the flash device is socketed and writable. This device is addressable on the XD bus extension of the ISA bus. The ROM is controlled by the Intel 82371SB PCI to ISA bridge chip.
Application Note 7
Point of Sale Terminal Design Guide
2.2 Peripheral components
The peripheral components in this POS terminal design include:
• Video controller
• PS/2 keyboard
• RTC/NVRAM
• Application flash memory
• Four serial ports
• One parallel port
• PCI connector
• ISA connector
• IDE port
• PCMCIA socket
• PS/2 mouse port
This design is modular. Peripherals can be easily removed if they are not required in the final design.
2.2.1 Video Controller
The Cirrus Logic CL-GD7555* Video and Graphics Controller is capable of controlling a CRT, TFT, DSTN or TV display. It connects directly to the 32-bit PCI (v2.1) host bus with a 33 MHz clock rate.
2.2.2 PS/2 Keyboard
Keyboard support is provided by the National Semiconductor 87307 Super I/O* device. The keyboard connectors are PS/2 type.
2.2.3 RTC/NVRAM
The RTC and NVRAM is contained within the National Semiconductor 87307 Super I/O device. CMOS backup is provided by a 3 V battery.
2.2.4 Application Flash Memory
There are 4 Mbytes of application flash memory on the POS terminal motherboard. This flash memory serves as non-volatile memory. The operating system and POS software can be stored in this flash device. To use the application flash as a disk, appropriate software must be installed. To boot from a flash device, changes may be needed in the BIOS or the flash driver software.
8 Application Note
Point of Sale Terminal Design Guide
The design’s application flash memory consists of one Intel 28F320S5 from the Word-Wide FlashFile™ Memory Family. This 16-bit, word-wide FlashFile memory provides high-density,low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Key enhancements include:• Common Flash Interface (CFI) support
• Scalable Command Set (SCS) support
• S5 technology
• Enhanced suspend capabilities
2.2.5 Serial and Parallel Ports
There are four serial ports in the POS terminal design. COM1 and COM2 are generated and supported by the National Semiconductor 87307 Super I/O device. COM3 and COM4 are generated and controlled by the Exar ST16C452* Dual Asynchronous Receiver/Transmitter.
GD 75232* drivers/receivers from Texas Instruments provide the interface between the UART and the communication ports. This device provides a low-cost solution for this function and allows easy interconnection of the UART and communication ports. It also complies with the requirements of the EIA/TIA-232-E and ITU standards.
The parallel port on the POS terminal design is generated and controlled by the National Semiconductor 87307 Super I/O device. The parallel port uses a DB25 connector.
2.2.6 IDE Port
Two standard IDE interfaces are provided by the 82371SB. One 40-pin IDE connector is included in the design. This allows up to two IDE devices (one master and one slave) to be supported in a single connector.
2.2.7 PCMCIA Interface
The Cirrus Logic CL-PD6720* is used as the host adapter chip to control two PCMCIA sockets. Only one socket is implemented in this design. The chip is fully PCMCIA (v2.1) and JEIDA (v4.1) compliant. The CL-PD6720 provides fully buffered PCMCIA interfaces. No external logic is required for buffering signals to or from the interface. Power consumption can be controlled by limiting signal transitions on the PCMCIA bus.
2.2.8 PS/2 Mouse Port
A PS/2-type mouse port is provided by the National Semiconductor 87307 Super I/O device.
Application Note 9
Point of Sale Terminal Design Guide
ssor.
the
omes The
bus
3.0 POS Terminal Design Details
For more information about the POS terminal design, please refer to the schematics located in Appendix B, “Schematics.”
3.1 Intel Embedded Processor Module (EMBMOD133)
The Embedded Processor Module has two connectors and a heat sink for the Pentium proceThe two connectors carry power, clocks, the DRAM memory interface and the 33 MHz PCI interface. 3 V and 5 V power is provided to the Embedded Processor Module. The module generates the core voltage. This core voltage is provided to the POS terminal baseboard forpower-on sequencing circuitry.
For more information, please refer to the Intel Embedded Processor Module datasheet (order number 273105) and AP-757, Embedded Processor Module Design Guide (order number 273120).
3.2 Intel 82371SB PCI ISA IDE Xcelerator
The Intel 82371SB requests control of the PCI bus by asserting the PHOLD# signal, and becthe PCI master upon receipt of the PHOLDA# signal from the Embedded Processor Module.Intel 82371SB contains the PCI and ISA interrupt controller, along with various ISA legacy functions such as a DMA controller, a bus master IDE Interface, an ISA bus interface, an ISAclock control, an XD bus control, a USB interface and a BIOS ROM interface.
For more information on the Intel 82371SB PCI ISA IDE Xcelerator, please refer to the Intel 82371FB (PIIX) and 82371SB (PIIX3) PCI-TO-ISA/IDE Xcelerator datasheet (order number 290550) and the Intel 82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) Timing Specification (order number 272963).
3.3 PCMCIA Connector
The PCMCIA connector has three main components:
• PCMCIA host adapter (CL-PD6710)
• PCMCIA connector
• Analog power controller circuit
3.3.1 PCMCIA Host Adapter
The Cirrus Logic PCMCIA host adapter (CL-PD6720) is a single chip capable of controlling two PCMCIA sockets. One PCMCIA socket is implemented in the design. The CL-PD6720 is fully compliant with the PCMCIA (v2.1) and JEIDA (v4.1) specifications and is optimized for use in palmtops and laptops, in which the main design objectives are reduced form-factor and low-power consumption. This chip also provides fully buffered PCMCIA interfaces. No external logic is required for buffering signals to or from the interface, and power consumption can be controlled by limiting signal transitions on the PCMCIA bus.
10 Application Note
Point of Sale Terminal Design Guide
ART ingle 2
essive
The chip also supports fully mixed voltage operation, a key feature for low power system design and low-power card operation. The core, ISA interface, and the PCMCIA socket interface can all operate independent of each other at either 3.3 V or 5 V.
The design can support either 3.3 V or 5 V operation and can be switched back and forth between 3.3 V and 5 V operation. Automatic voltage sensing has not been implemented in this design; the correct voltage must be set by the driver.
3.3.2 PCMCIA Voltage Control
The Linear Technology (LTC 1472*) switching matrix routes power to both the +5V (VCC) and +12V (VPP) power supply pins on the individual PC Card sockets. The VCC output of the LTC 1472 is switched between three operating states: OFF, 3.3 V and 5 V. The VPP output is switched between four operating states: 0 V, VCC, 12 V and Hi-Z. The VCC output of the LTC 1472 can supply up to 1 A of current and the VPP output up to 120 mA. Both switches have built-in current limiting and thermal shutdown to protect the card, socket, and power supply against accidental short-circuit conditions.
3.4 Serial and Parallel Communications
COM1 and COM2 are generated and supported by the National Semiconductor 87307 Super I/O device. COM3 and COM4 are generated and controlled by the Exar ST16C452 Dual Asynchronous Receiver/Transmitter with Parallel Printer Port device.
COM3 occupies 03E8 - 03EF and COM4 occupies 02E8 - 02EF in the address range. An additional logic decoding circuit decodes COM3 and COM4 on ST15C452. This is performed by the CSA# and CSB# signals on the UART.
The Exar ST16C452 chip is a dual universal asynchronous receiver and transmitter (UART) with a bidirectional Centronics* compatible parallel printer port. A programmable baud rate generator is provided to select transmit and receive clock rates from 50 Hz to 1.5 MHz.
The ST16C452 on-board status registers indicate the error conditions, type and status of the transfer operation being performed. Additional features include:
• Complete MODEM control capability
• A processor interrupt system that may be software tailored to the user’s requirements
• Internal loop-back capability for on-board diagnostic testing
Connection to the LPT1 parallel port is made using a 25-pin female D-sub connector. This is a multi-mode IBM PC/XT*, PC/AT* and PS/2-compatible bidirectional parallel port. Since the ST16C452 does not supply another parallel port in this design, INTP and INTSEL can be “noconnect.”
The GD75232 driver/receiver from Texas Instruments is used as an interface between the Uand the communication ports. The GD75232 combines three drivers and five receivers in a schip, which decreases the device count and reduces the board space required. One GD7523supports one communication port, which makes the design modular.
Clamped diodes are added for port protection. This is an optional item but it ensures that excvoltage does not cause damage to the GD75232.
Application Note 11
Point of Sale Terminal Design Guide
ith
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E1#. nd
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n, a the 0S5
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uch ports lays
16 ates 0 x
e this
3.5 Application Flash
The Intel 28F320S5 flash device from the Word-Wide FlashFile™ memory family operates w5 V on both VCC and VPP.
The BYTE# pin allows either x8 or x16 read/program to the 28F320S5 flash device. When loBYTE# selects 8-bit mode, and address A0 selects between the low byte and the high byte. high, BYTE# enables 16-bit operation, address A1 becomes the lowest order address, and aA0 is not used (don’t care).
The 28F320S5 also incorporates a dual chip-enable function with two input pins, CE0# and CThese pins have exactly the same function as the regular chip enable pin, CE#. Both CE0# aCE1# must be active low to enable the device. If either signal becomes inactive, the chip is disabled. Device selection occurs with the falling edge of CE0# or CE1#. The first rising edgCE0# of CE1# disables the device. For minimum chip designs, CE1# may be tied to ground system logic may use CE0# as the chip enable input.
Memory holes must be used to address the flash. It can either be at 512 Kbyte – 640 Kbyte (080000H-0A0000H) or between 15 Mbyte and 16 Mbyte (F00000H-FFFFFFH). In this desig512-Kbyte window below 16 Mbyte (F80000H-FFFFFFH) is used. General purpose I/O fromNational Semiconductor 87307 Super I/O are used to select one of eight pages in the 28F32memory device.
If the application flash is required to act as a disk, suitable drivers should be used.
3.6 Video Controller
The CL-GD7555 Video and Graphics Controller can control a CRT, TFT, DSTN, or TV displaThe controller supports mixed voltage operation. Active power management provides power-control of selected unused internal functional blocks during display. The CL-GD7555 also connects directly to the 32-bit PCI (v2.1) host bus with a 33 MHz clock rate.
The CL-GD7555’s V-port allows cost-effective implementation of many multimedia features sas MPEG video playback, TV tuning, video capture and teleconferencing. The chip also supTFT flat panel displays (up to 1024 x 768 resolution) and color dual-scan STN flat panel disp(up to 800 x 600 resolution).
In this design, the CL-GD7555 is implemented with a 2-Mbyte frame buffer using four 256K xDRAMs. The TFT/DSTN display is not implemented in this design. The CRT controller generhorizontal and vertical signals (HSYNC and VSYNC) for a CRT monitor. It supports up to 1281024 resolution with 256 colors.
The IDSEL signal is routed to AD13. The INTR signal is connected to PIRQ1.
3.7 Power
Power is supplied to the board through an ATX power connector. ATX power supplies provid5 V, 3.3 V, +12 V, -5 V and -12 V outputs. All these values are used in the design. When usingpower supply there is no need for additional voltage regulators.
12 Application Note
Point of Sale Terminal Design Guide
4.0 Design Considerations
There should be decoupling capacitors for every schematic page and one bulk capacitor for the entire design. This provides a short between power and ground for high frequency signals and to reduce inductance.
If a part is to be removed from the design, the outputs can be left unconnected but the inputs should be pulled either high or low. Since the TFT/DSTN display is not implemented for this design, connect the video controller power pins to VCC.
5.0 Summary
This design was created to shorten the development cycle for POS terminal designs. It is intended to be implemented on a single board for reduced cost. Peripherals are designed in a modular fashion and can be easily removed for specific applications.
Caution: The design has not been implemented in hardware. This document is for reference only. Customers are responsible for validating designs created using the information included in this document.
6.0 Related Documents
Copies of Intel documents that have an order number referenced in this document (see Table 1) may be downloaded from the Intel web site at http://www.intel.com. To order printed copies, call 1-800-548-4725.
Table 2 lists documents available from other vendors.
Table 1. Intel Documents
Document Name Order Number
Intel Embedded Processor Module datasheet 273105
Intel Embedded Processor Module Design Guide 273120
Intel Embedded Processor Module (EMBMOD133) Thermal Design Guide 273143
Pentium® Processor datasheet 241997
Pentium® Processor Family Developer’s Manual 241428
Intel Architecture Software Developer’s Manual (Vols. 1, 2 and 3) 243190, 243191 and 243192
Intel 430HX PCIset 82439HX System Controller (TXC) datasheet 290551
Intel 430HX PCIset 82439HX System Controller (TXC) Timing Specification 272945
Intel 430HX PCIset Design Guide 297467
82371FB (PIIX) and 82371SB (PIIX3) PCI-TO-ISA/IDE Xcelerator datasheet 290550
82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) Timing Specification 272963
The Advantages of Using the 82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) with the Intel 430HX PCIset in Embedded Designs 273009
Intel Word-Wide FlashFile™ Memory 28F320S5 datasheet 290609
Application Note 13
Point of Sale Terminal Design Guide
7.0 Contact Information
Table 2. Third Party Vendor Documents
Document Name
National Semiconductor PC87307VUL Super I/O datasheet
Cirrus Logic CL-GD7555 Advance Hardware Reference Manual
Cirrus Logic CL-PD 6720 datasheet
Exar ST16C452 Dual UART with Parallel Printer Port datasheet
Specifications Lattice ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array Logic datasheet
Linear Technology LTC 1472 Protected PCMCIA Vcc and Vpp Switching Matrix datasheet
Texas Instruments GD75232 Multiple RS-232 Drivers and Receivers datasheet
Intel Corporation2200 Mission College Blvd.Santa Clara, CA 95052-8119Web site: http://www.intel.com
EXAR Corporation48720 Kato RoadFremont, CA 94538Web site: http://www.exar.com
National Semiconductor Corporation2900 Semiconductor DriveP.O. Box 58090Santa Clara, CA 95052-9959Web site: http://www.national.com
Siemens Microelectronics, Inc.10950 North Tantau AvenueCupertino, CA 95014Web site: http://www.siemens.com
Cirrus Logic31000 West Warren AvenueFremont, CA 94538Web site: http://www.cirrus.com
Texas Instruments IncorporatedP.O. Box 809066Dallas, TX 75244-9066Web site: http://www.ti.com
14 Application Note
Point of Sale Terminal Design Guide
Appendix A Bill of Materials
Note: Intel does not guarantee device availability. Designers should check for device availability before designing-in any of the components included in the document.
Table 3. POS Design Guide Bill of Materials (Sheet 1 of 4)
POS Design Guide: Embedded Processor Module Connectors Revised: Wednesday, March 11, 1998
Revision: 1.00
The estimated bill of material cost for this design is US$400, as of 3/20/98.
Bill Of Materials March 20,1998 8:19:09 Page1
Item Quantity Reference Part
1 1 BT1 HU 2032-1 SOCKET
2 10 C1, C2, C3, C36, C38, C39, C44, C45, C46, C47 0.001uF
3 37
C4, C24, C32, C33, C34, C35, C37, C48, C65, C73, C74, C85, C86, C112, C113, C124, C125, C149, C150, C151,
C213, C214, C215, C216, C230, C231, C232, C233, C237, C242, C267, C268, C288, C289, C290, C291, C292
0.01uF
4 124
C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C21, C22, C23, C25, C26, C27, C28, C29, C30, C31, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, C64, C66, C67, C68, C70, C71, C72, C76, C77, C79, C80, C82, C83, C84, C88, C89, C91, C92, C93,
C94, C95, C96, C100, C101, C103, C104, C106, C107, C109, C110, C111, C115, C116, C118, C119, C121, C122, C123, C128, C143, C144, C145, C146, C147, C148, C161, C162, C163, C164, C165, C166, C167, C168, C169, C207, C208, C209, C210, C211, C212, C225, C226, C227, C228, C229, C235, C236, C240, C241, C244, C247, C253, C260, C261, C262, C266, C269, C270, C272, C274, C277, C280, C282, C283,
C285, C293, C294
0.1uF
5 12 C19, C20, C245, C246, C248, C249, C254, C255, C275, C276, C278, C279 100uF
6 27C40, C41, C42, C43, C69, C75, C78, C81, C87, C90, C99,
C102, C105, C108, C114, C117, C120, C141, C142, C202, C203, C221, C222, C256, C263, C264, C271
10uF
7 17 RP1, R1, RP2, R2, RP3, RP4, R6, R8, R16, R23, R30, R31, C62, C63, C97, C126, C127 0
8 1 C98 100pF
9 14 C129, C130, C131, C132, C133, C134, C135, C136, C137, C138, C139, C140, C158, C159 10pF
10 25C152, C153, C154, C155, C156, C157, C172, C173, C174, C175, C177, C178, C179, C180, C184, C185,
C186, C187, C188, C189, C190, C191, C250, C251, C252470pF
11 2 C160, C259 22uF
12 16 C170, C171, C176, C181, C182, C183, C192, C193, C194, C195, C196, C197, C198, C199, C200, C201 220pF
13 12 C204, C205, C206, C217, C223, C224, C234, C239, C258, C265, C284, C287 1uF
14 6 C218, C219, C220, C238, C281, C296 CAP
15 1 C243 .1uF
Application Note 15
Point of Sale Terminal Design Guide
16 1 C257 4.7nF
17 1 C273 1000pF
18 1 C286 220uF
19 1 C295 0.0022uF
20 4 D1, D53, D54, D55 LGS260-DO
21 1 D2 FMMD914
22 40
D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46,
D47, D48, D49, D50, D51, D52
D1N916A
23 10 D23, D24, D25, D26, D27, D28, D29, D30, D31, D32 D1N916
24 1 D56 BZX84C2V7
25 1 D57 BZX84C2V4
26 1 D58 1N5817
27 6 FB1, FB2, FB3, FB4, FB5, FB6 BLM41A800S
28 2 FB8, FB7 CB70
29 2 F1, F2 SMD125-002
30 1 JP1 FLOPPY HEADER 17X2
31 1 JP2 1x4
32 1 J1 EPM DRAM Conn 140-Pin
33 1 J2 EPM PCI Conn 120-Pin
34 1 J3 Embedded Processor Module DRAM Conn 140-Pin
35 1 J4 Embedded Processor Module PCI Conn 120-Pin
36 2 J6, J5 Molex 71736-00011
37 1 J7 IDE Conn
38 2 J9, J8 PCI Conn
39 1 J10 ISA Conn A
40 1 J11 ISA Conn B
41 1 J12 PS2 STACK
42 4 J13, J14, J17, J23 1x2
43 3 J15, J24, J25 1x3
44 1 J16 1x1
45 1 J18 SERIAL STACK
46 1 J19 DB25
47 1 J20 CONNECTOR DB15HD
48 1 J21 JUMP3
49 1 J22 ATX POW CONN
50 1 J26 PCMCIA Connector
51 2 L1, L2 INDUCTOR
52 2 P2, P1 DB9
53 2 Q1, Q2 NDS9953A
54 8 R4, RP5, RP6, R7, RP45, RP49, R53, R59 22
Table 3. POS Design Guide Bill of Materials (Sheet 2 of 4)
16 Application Note
Point of Sale Terminal Design Guide
55 25R5, RP7, R14, RP17, RP18, RP20, RP21, RP25, RP30,
RP32, RP34, RP36, RP38, RP39, RP40, RP41, R46, R47, R48, R49, R50, R51, R55, R77, R78
10K
56 14 RP8, RP9, RP10, RP11, RP12, RP13, R13, RP14, RP15, RP16, RP46, RP47, R68, R69 33
57 20 R10, R11, RP19, RP28, R33, R34, R36, R38, R39, R41, RP42, R42, RP43, R43, RP44, R44, R45, R58, R70, R76 4.7K
58 4 RP22, RP26, R37, R40 330
59 11 RP23, RP24, R25, R26, RP27, R27, R28, RP29, RP31, RP33, R35 2.7K
60 2 RP35, RP37 5.6K
61 8 R3, R18, R19, R29, R32, RP48, R60, R79 1K
62 5 R9, R21, R22, R67, R72 220
63 3 R12, R15, R17 47
64 2 R20, R73 215
65 1 R24 10
66 1 R52 22M
67 1 R54 120K
68 1 R56 8.2K
69 1 R57 20K
70 3 R61, R62, R63 150
71 1 R64 180
72 2 R66, R65 R
73 1 R71 51K
74 1 R74 130
75 1 R75 110
76 1 S1 RESET SWITCH
77 2 TP2, TP1 12MHZ
78 1 TP3 MWE#
79 1 TP4 MRAS2#
80 1 TP5 MRAS0#
81 1 TP6 MCAS0#
82 1 TP7 MCAS1#
83 1 TP8 MCAS2#
84 1 TP9 MCAS3#
85 1 TP10 MCAS4#
86 1 TP11 MCAS5#
87 1 TP12 MCAS6#
88 1 TP13 MCAS7#
89 1 TP14 14MHZ
90 1 TP15 PCLK_PIIX3
91 1 TP16 24MHZ
92 1 TP17 BIOSCS#
93 1 TP18 PDIAG#
94 1 TP19 SYSCLK
Table 3. POS Design Guide Bill of Materials (Sheet 3 of 4)
Application Note 17
Point of Sale Terminal Design Guide
95 1 TP20 14MHZ_ISA
96 1 TP21 P12
97 1 TP22 P16
98 1 TP23 P17
99 1 TP24 P20
100 1 TP25 P21
101 1 TP26 X1
102 1 TP27 G10
103 1 TP28 G11
104 1 TP29 G12
105 1 TP30 G13
106 1 TP31 G14
107 1 TP32 G15
108 1 TP33 G16
109 1 TP34 G17
110 1 TP35 G20
111 1 TP36 G21
112 1 TP37 G22
113 1 U1 82371SB (PIIX3)
114 1 U2 74ACT04
115 3 U3, U5, U6 74ALS245
116 1 U4 74HCT14
117 1 U7 74ALS08
118 1 U8 74ALS00
119 1 U9 74ACT05
120 1 U10 PC87307IBU-VUL
121 1 U11 28F001BX-T150
122 4 U12, U13, U27, U29 GD75232SOP
123 1 U14 CL-GD7555
124 4 U15, U16, U17, U18 HYB514171BJ-60
125 1 U19 27C512
126 1 U20 74LS30
127 1 U21 74LS04
128 1 U22 ispGAL22V10
129 1 U23 28F320S5
130 1 U24 74LS08
131 1 U25 74LS260
132 1 U28 ST16C452
133 1 U30 TLC393C
134 1 U31 7404
135 1 U32 CL-PD6720
136 1 U33 LTC1472
137 1 Y1 32.768KHZ
Table 3. POS Design Guide Bill of Materials (Sheet 4 of 4)
18 Application Note
Point of Sale Terminal Design Guide
Appendix B BIOS Checklist
This section is a checklist to specify the hardware configuration for a BIOS vendor to customize the BIOS.
Table 4. Hardware Design Specification
Intel 430HX chipset
Manufacturer Intel Corporation
Bus Host
Embedded Processor Module
Manufacturer Intel Corporation
Speed 133 MHz
Memory - System
Configuration EDO, FPM
Speeds Supported 60, 70
Memory - Cache (External)
Configuration 256 Kbyte
ROM
Manufacturer Intel Corporation
Part # 28F001BX-T150
Size 128 Kbyte
Super I/O
Manufacture / Part # National Semiconductor 87307
Table 5. Items connected to Super I/O
IDE
Floppy
Serial
Parallel
Keyboard Controller
Real Time Clock
Application Note 19
Point of Sale Terminal Design Guide
Table 6. Onboard Peripherals
Onboard Peripherals
Manufacturer and Part Number
ResidentBus
If PCI, specify Vendor/
Device ID
If PCI, specify Dev.# or IDSEL
Option ROM
Embed-ded in BIOS?
Supported IRQs Address Range
VideoCirrus LogicCL-GD7555 PCI AD13 -
PC Card Controller
Cirrus LogicCL-PD6720
ISA - - -
3, 4, 5, 7, 9, 12, 14
(Program-mable)
I/O address:0000-FFFFH
(Programmable)
Memory address:010000-FFFFFFH(Programmable)
UART (Com3, Com4)
Exar ST16C462 ISACOM3: IRQ4
COM4: IRQ3
I/O address:
COM3:03E8-03EFH
COM4: 02E8-02EFH
OTHER
Table 7. PCI Routing Information
Physical Slot #
or Onboard Device
IDSEL #or
DEV. #PCI BUS #
INT or PIRQ pins from the chip set are connected to these INT pins coming from each slot
PIRQ 0 or INT A
PIRQ 1or INT B
PIRQ 2 or INT C
PIRQ 3 or INT D
Slot 0 AD28 0 x x
Slot 1 AD29 0 x x
Table 8. Connectors
Serial
Parallel
PS/2 Mouse
PS/2 Keyboard
Video
Other
Table 9. Software Design Specification – Feature List
USB
Enhanced IDE
PCI v2.1 Spec
PNP Spec
Other
20 Application Note
Point of Sale Terminal Design Guide
Appendix C Schematics
C.1 POS Terminal Reference Design Schematics
Schematics are provided for the following items:
• Embedded Processor Module Connectors
• DRAM DIMM socket
• 82371SB PCI to ISA Bridge
• ISA interface
• PCI slots 0 and 1
• ISA sockets
• ISA pullup/pulldown
• Super I/O
• Flash BIOS
• I/O connectors
• Video controller
• Video DRAM and VGA BIOS ROM
• PCMCIA connector
• Application flash
• Serial and parallel communications
• Power
Application Note 21
DRAM
ADDRESS/DATA/CLOCKS
PCICLK_0 (B19) De-Skew Loopback
PCICLK_1/PCLK_PIIX3 (A13) PIIX3
PCICLK_2/PCLK_VIDEO (B14) Video (Virge GX)
PCICLK_3/PCLK_SLOT0 (A16) PCI Expansion Slot 0
PCICLK_4/PCLK_SLOT1 (B17) PCI Expansion Slot 1
PCICLK_5/PCLK_SLOT23 (A18) PCI Expansion Slots 2/3
Clock De-Skew Loop Back
(see Note 3)
PCI Clock Distribution (33MHZ)
24MHZ (3v): PIIX3(USBCLK),
X1(Super I/O)
14MHZ (3v): PIIX3(OSC), ISA
Slots (OSC)
SYSCLK 8.25MHZ (PIIX3) ->
ISA Slots
24MHZ/14MHZ/SYSCLK
J1 GND:
A01, A09, A21, A29, A37, A45, A53, A61, A69
B15, B31, B39, B47, B55, B63, B70
J1 V5_0:
A05, A13, A17, A25
B03, B07, B11,
B19, B23
J1 V3_3:
A33, A41, A49, A57, A65
B27, B35, B43, B51,
B59, B67
J2 V3_3:
A03, A11, A19, A27, A35, A43, A51, A55, A59
B01, B08, B16, B24, B32, B40, B48, B56
J2 GND:
A07, A15, A23, A31, A39, A47
B12, B20, B28, B36, B44,
B52, B60
NOTE 0: Connectors are female
NOTE 4: Split PCLK_SLOT23 to supply both PCI SLOT 2 and PCI SLOT 3 as close to the PCI slots as possible. Stubs must be of equal length.
NOTE 1: PCLK_PIIX3, PCLK_VIDEO, PCLK_SLOT0, PCLK_SLOT2, PCLK_SLOT23 must be equal length.
NOTE 5: Separate all clocks from any other trace by 10 mil. (SYSCLK, 25MHZ, 14MHZ, PCLK_PIIX3, PCLK_VIDEO, PCLK_SLOT0, PCLK_SLOT1,
PCLK_SLOT23
NOTE 3: PCLK_0 to PCICLK_IN roundtrip must be same length as signals in NOTE 1.
Embedded Processor Module Connectors
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PC
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MA
2
MA
11
MA
10
MA
8
MA
5M
A4
MA
3
MA
7M
A6
MA
9
AD
2
AD
4A
D6
AD
10
AD
12
AD
14
AD
16A
D18
AD
24A
D20
AD
22
AD
25
AD
27A
D29
AD
31A
D30
AD
28
AD
26
AD
23
AD
21A
D19
AD
17
AD
15
AD
13
AD
11
AD
9A
D8
AD
7
AD
5
AD
3
AD
1
AD
0
-C/B
E1
-C/B
E0
-C/B
E2
-C/B
E3
AD
5
AD
10A
D9
AD
21
AD
30
AD
20
AD
15
AD
8
AD
19A
D18
AD
11
AD
17
AD
6
AD
29
AD
12A
D13
AD
16
AD
24A
D25
AD
26
AD
7
AD
2A
D3
AD
4
AD
0A
D1
AD
27A
D28
AD
23A
D22
AD
14
AD
31
-C/B
E0
-C/B
E1
-C/B
E2
-C/B
E3
12M
HZ
MP
D1
MD
14
MD
30
MD
34
MD
54
MD
38
MD
37
MD
51
MP
D4
MP
D4
MP
D7
MD
29
MD
22
MP
D5
MP
D3
MD
59
MP
D6
MD
33
MD
2
MA
11
MD
47
MD
62
MD
61
MD
12
MD
7
MD
36
MA
3
MD
42
MD
11
MD
39
MD
46
MD
57
MD
53M
D21
MD
49
MD
17
MA
8M
A2
MA
4M
A5
MA
6
MD
9
MD
15M
D31
MD
63M
D13
MD
27
MD
41
MD
3
MA
9
MD
56
MD
25
MP
D0
MP
D2
MD
44
MD
50
MD
52
MD
19
MD
16
MP
D6
MD
26
MD
24
MD
10
MP
D1
MP
D2
MD
35
MD
32
MA
7
MP
D7
MD
45
MP
D3
MD
43
MP
D0
MD
4
MD
6
MD
58M
D60
MD
23
MD
5
MD
1
MD
18
MD
40
MD
55
MD
20
MA
10
MP
D5
MD
8
MD
28
MD
48
MD
42
MD
11
MD
31
MD
40
MD
38
MD
51M
D50
MD
2
MD
58
MD
3
MD
21
MD
47
MD
16
MD
35
MD
7
MD
13
MD
29
MD
57
MD
14
MD
36
MD
1
MD
41
MD
27
MD
12
MD
32
MD
6
MD
63
MD
17
MD
62
MD
44M
D45
MD
9
MD
28
MD
18
MD
5
MD
39
MD
49
MD
23M
D24
MD
48
MD
4
MD
19
MD
34
MD
52
MD
43
MD
61
MD
25
MD
37
MD
56
MD
0
MD
46
MD
54
MD
30
MD
53
MD
8
MD
33
MD
0
MD
22
MD
60
MD
55
MD
26
MD
15
MD
59
MD
10
MD
20-D
EV
SE
L5,
7,9,
13-P
RE
Q1
7
24M
HZ
5
PC
LK_S
LOT
17
-PR
EQ
07
-FR
AM
E5,
7,9,
13
-PLO
CK
7,9
CP
UR
ST
5,9
-PG
NT
17
PC
LK_S
LOT
07
PC
LK_V
IDE
O13
-FE
RR
5,9
-PH
LDA
5
-IG
NN
E5,
9
-PG
NT
07
PA
R5,
7,9,
13
-PH
LD5
14M
HZ
5,8,
13
INT
R5,
9
-SM
I5,
9
INIT
9
-SE
RR
5,7,
9
-ST
OP
5,7,
9,13
-PC
IRS
T5,
7,13
NM
I5,
9
PC
LK_P
IIX
35
-ST
PC
LK
5,9
V2_
918
MP
D[7
:0]
4
MD
[63:
0]4
MA
[11:
2]4
-IR
DY
5,7,
9,12
AD
[31:
0]5,
7,13
-C/B
E[3
:0]
5,7,
13
-A20
M12
-TR
DY
5,7,
9,13
DB
RE
SE
T18
-MR
AS
04
-MR
AS
24
-MC
AS
24
-MC
AS
74
-MC
AS
14
-MC
AS
04
-MC
AS
64
-MC
AS
34
MA
B0
4
MA
B1
4M
AA
14
-MC
AS
54
-MW
E4
MA
A0
4
-MC
AS
44
-MR
AS
14
-PG
NT
27
-PR
EQ
37
-PG
NT
37,
13
-PR
EQ
27
TP
112
MH
ZT
P
J1
EP
M D
RA
M C
onn
140-
Pin
MW
E#
B01
GN
DA
01
MA
B1
B02
V5_
0B
03M
AA
1A
02
MA
6B
04M
AA
0A
03
MA
5B
05
MA
3B
06
MA
B0
A04
V5_
0B
07
V5_
0A
05
MA
11B
08
MA
7B
09
MA
4A
06
MA
9B
10
MA
2A
07
V5_
0B
11
MD
48B
12
MA
8A
08
MD
16B
13
GN
DA
09
MD
17B
14
GN
DB
15
MA
10A
10
MD
02B
16
MD
0A
11
MD
34B
17
MD
18B
18
MD
32A
12
V5_
0B
19
V5_
0A
13
MD
19B
20
MD
36B
21
MD
33A
14
MD
51B
22
MD
01A
15
V5_
0B
23
MD
05B
24
MD
49A
16
MD
52B
25
V5_
0A
17
RA
S6#
B26
V3_
3B
27
MD
35A
18
MD
21B
28
MD
50A
19
MD
37B
29
CA
S3#
B30
MD
03A
20
GN
DB
31
GN
DA
21
MD
06B
32
CA
S1#
B33
MD
04A
22
MD
07B
34
RA
S7#
A23
V3_
3B
35
CA
S0#
B36
RA
S5#
A24
MP
D2
B37
V5_
0A
25
MD
23B
38
GN
DB
39
MD
20A
26
MP
D4
B40
RA
S4#
A27
MP
D0
B41
CA
S6#
B42
MD
53A
28
V3_
3B
43
GN
DA
29
MP
D1
B44
MP
D5
B45
CA
S7#
A30
RA
S1#
B46
MD
22A
31
GN
DB
47
MP
D3
B48
MD
38A
32
RA
S3#
B49
V3_
3A
33
MD
41B
50
V3_
3B
51
MD
39A
34
MD
30B
52
MD
54A
35
MD
44B
53
MD
57B
54
CA
S5#
A36
GN
DB
55
GN
DA
37
MD
11B
56
MD
10B
57
MD
55A
38
MD
12B
58
CA
S4#
A39
V3_
3B
59
MD
60B
60
CA
S2#
A40
MD
27B
61
V3_
3A
41
MD
28B
62
GN
DB
63
MP
D6
A42
MD
45B
64
RA
S0#
A43
MD
13B
65
MD
63B
66
MP
D7
A44
V3_
3B
67
GN
DA
45
MD
31B
68
MD
15B
69
RA
S2#
A46
GN
DB
70
MD
08A
47
MD
40A
48
V3_
3A
49
MD
25A
50
MD
24A
51
MD
56A
52
GN
DA
53
MD
26A
54
MD
09A
55
MD
46A
56
V3_
3A
57
MD
42A
58
MD
59A
59
MD
58A
60
GN
DA
61
MD
43A
62
MD
61A
63
MD
29A
64
V3_
3A
65
MD
62A
66
MD
14A
67
MD
47A
68
GN
DA
69
N/C
A70
J2
EP
M P
CI C
onn
120-
Pin
V3_
3B
01IN
ITA
01
ST
PC
LK#
B02
SM
I#B
03C
PU
RS
TA
02
GN
DB
04V
3_3
A03
NM
IB
05
FE
RR
#B
06
A20
M#
A04
N/C
B07
V3_
3B
08
INT
RA
05
2.9V
_SE
NS
EB
09
IGN
NE
#A
06
N/C
B10
14.3
18M
HZ
B11
GN
DA
07
GN
DB
12
24M
HZ
A08
N/C
B13
PC
ICLK
_2B
14
N/C
A09
N/C
B15
V3_
3B
16
12M
HZ
A10
PC
ICLK
_4B
17
V3_
3A
11
N/C
B18
PC
ICLK
_0B
19
N/C
A12
GN
DB
20
PC
ICLK
_1A
13
PC
ICLK
_IN
B21
N/C
B22
N/C
A14
PC
IRS
T#
B23
V3_
3B
24
GN
DA
15
AD
31B
25
PC
ICLK
_3A
16
AD
29B
26
AD
27B
27
N/C
A17
GN
DB
28
PC
ICLK
_5A
18
AD
25B
29
CB
E3#
B30
V3_
3A
19
AD
22B
31
V3_
3B
32
DB
RS
TA
20
LOC
K#
B33
N/C
A21
AD
20B
34
AD
24B
35
N/C
A22
GN
DB
36
GN
DA
23
AD
18B
37
AD
16B
38
N/C
A24
IRD
Y#
B39
V3_
3B
40
AD
30A
25
CB
E1#
B41
AD
28A
26
GN
T0#
B42
AD
14B
43
V3_
3A
27
GN
DB
44
AD
26A
28
AD
12B
45
DE
VS
EL#
B46
PH
LD#
A29
AD
10B
47
V3_
3B
48
AD
23A
30
GN
T#
B49
GN
DA
31
CB
E0#
B50
RE
Q2#
B51
PH
LDA
#A
32
GN
DB
52
AD
21A
33
AD
6B
53
AD
4B
54
AD
19A
34
PA
RB
55
V3_
3B
56
V3_
3A
35
AD
2B
57
FR
AM
E#
A36
SE
RR
#B
58
GN
T3#
B59
AD
17A
37
GN
DB
60
RE
Q0#
A38
GN
DA
39
CB
E2#
A40
AD
15A
41
TR
DY
#A
42
V3_
3A
43
AD
13A
44
RE
Q1#
A45
AD
11A
46
GN
DA
47
AD
9A
48
AD
8A
49
AD
7A
50
V3_
3A
51
ST
OP
#A
52
AD
5A
53
GN
T2#
A54
GN
DA
55
AD
3A
56
RE
Q3#
A57
AD
1A
58
V3_
3A
59
AD
0A
60
J3/J4 V3_3:
A06, A18, A26, A40, A41, A49, A59, A73, A84
B90, B102, B110, B124, B133, B143, B157, B168
J3/J4 GND:
A01, A12, A23, A32, A43, A54, A64, A68, A78 | A31, A44, A82, A83
B85, B96, B107, B116, B127, B138, B148, B152, B162 | B165, B166,
B167
J3/J4 NC:
A24, A25, A39, A50, A51, A61, A63, A79, A80, A81
B108, B109, B114, B123, B129, B135, B145, B147, B163, B164
J3/J4 DU: A42, A62
B111, B115, B125, B126, B128, B132, B134, B135, B146
NOTE 1: Place Test Points close to J3/J4 DIMM Connectors
Note: Termination resistors already on Mohave for MRAS#/MCAS#
Note: Termination resistors already on Mohave for MRAS#/MCAS#
SEE NOTE 2
NOTE 2: Use R-PACK pad geometry. Shunt pads with trace. Route on surface (cuttable)
DO NOT
STUFF
DO NOT
STUFF
DRAM (DIMM) SOCKETS
{Doc
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RA
M D
IMM
Soc
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A4
418
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
-MC
AS
5
MD
12M
D11
MD
9
MD
21
MD
2
-MW
E
MD
1
MD
16
MD
53
MD
16
MD
25
MD
45
-MW
E
-MC
AS
3
-MC
AS
3
MD
0
MD
52
MD
57
MD
42
MD
13
MD
43
MD
47
MD
44
-MC
AS
3
MD
30
MD
56
MD
2
MD
47
MD
10
MD
55
MD
1
MD
31
MD
29
MD
38
MD
34
MD
52
MD
31
MD
56
MD
8
MD
5
MD
15M
D14
MD
50
-MC
AS
7
MD
49
MD
45
MD
40
MD
37
-MC
AS
1
-MC
AS
2
MD
23
MD
5
MD
14
MD
35
MD
4
MD
0
-MR
AS
0
MD
41
MD
44
MD
36
MD
62
-MC
AS
6-M
CA
S6
MD
33
MD
28
MD
27
MD
24
-MR
AS
2
-MW
E
MD
42
MD
7
MD
32
MD
3
MD
59
MD
20
MD
22
MD
11
-MC
AS
5
-MC
AS
6
-MC
AS
0
MD
53
MD
59
MD
8
MD
4
MD
17
MD
61
MD
26
MD
30
MD
18
MD
12
MD
60
MD
63
MD
48
MD
35
MD
32
-MC
AS
4
MD
57
MD
18
MD
15
MD
27
MD
19
MD
63
MD
58
MD
19
MD
7
MD
51
MD
10
MD
26
MD
24
MD
36
MD
48
MD
34M
D33
MD
17
MD
6
MD
46
-MC
AS
7
-MC
AS
4-M
WE
MD
55
MD
58
MD
22
MD
6
MD
54
MD
39
-MC
AS
2
-MC
AS
7
MD
21
MD
43
MD
60
MD
62
MD
46
MD
49
MD
23
MD
61
MD
9 -MC
AS
2
MD
54
MD
20
MD
25
MD
29
MD
37
MD
50M
D51
MD
41
MD
3
MD
40
MD
13
MD
39M
D38
MD
28
MP
D1
MP
D0
MP
D4
MP
D3
MP
D7
MP
D6
MP
D3
MP
D4
MP
D2
MP
D0
MP
D5
MP
D7
MP
D1
MP
D2
MP
D5
MP
D6
-MC
AS
0-M
CA
S4
-MC
AS
0-M
CA
S5
RA
S-M
CA
S1
-MC
AS
1
MA
6
MA
11
MA
4
MA
A0
MA
8M
A8
MA
4
MA
A1
MA
7M
A6
MA
2
MA
9M
A11
MA
3M
A3
MA
4M
A5
MA
5
MA
7
MA
10
MA
10
MA
9
MA
8
MA
10
MA
10
MA
6
MA
9
MA
5
MA
6
MA
2
MA
9
MA
2
MA
11
MA
7
MA
3M
A3
MA
4M
A5
MA
8M
A7
MA
2
MA
11 MA
A0
MA
A1
MA
B1
MA
B1
MA
B0
MA
B0
MD
[63:
0]
MP
D[7
:0]
MA
[11:
2]
-MC
AS
23
-MC
AS
63
-MW
E3
MD
[63:
0]3
-MR
AS
03
-MC
AS
33
-MC
AS
73-M
RA
S2
3
MP
D[7
:0]
3
-MC
AS
03
-MC
AS
43
MA
[11:
2]3
-MC
AS
13
-MC
AS
53 -M
RA
S1
3
MA
A1
3M
AA
03
MA
B0
3M
AB
13
V3_
3V
3_3
C30
0.1u
FC
290.
1uF
C28
0.1u
FC
310.
1uF
C33
0.01
uFC
320.
01uF
C35
0.01
uFC
340.
01uF
TP
7M
CA
S1#
TP
TP
4M
RA
S2#
TP
TP
5M
RA
S0#
TP
TP
6M
CA
S0#
TP
TP
12M
CA
S6#
TP
TP
13M
CA
S7#
TP
TP
9M
CA
S3#
TP
TP
10M
CA
S4#
TP
TP
3M
WE
#T
P
TP
8M
CA
S2#
TP
TP
11M
CA
S5#
TP
C12
0.1u
FC
140.
1uF
C13
0.1u
FC
170.
1uF
C16
0.1u
FC
150.
1uF
C18
0.1u
F
RP
2
0
18
27
36
45
RP
3
0
18
27
36
45
RP
1
0
18
27
36
45
R1
0 R2
0
RP
4
0
18
27
36
45
J6 Mol
ex 7
1736
-000
11GN
DB
85G
ND
A01
DQ
32B
86
DQ
33B
87
DQ
0A
02
DQ
34B
88
DQ
1A
03
DQ
35B
89
V3_
3B
90
DQ
2A
04
DQ
36B
91
DQ
3A
05
DQ
37B
92
DQ
38B
93
V3_
3A
06
DQ
4A
07
DQ
5A
08
DQ
6A
09
DQ
7A
10
V3_
3B
157
GN
DB
148
GN
DB
152
V3_
3B
143
V3_
3A
41
DU
A42
GN
DA
43
OE
2A
44
RA
S2
A45
CA
S2
A46
CA
S3
A47
WE
2A
48
V3_
3A
49
NC
A50
NC
A51
CB
2A
52
CB
3A
53
GN
DA
54
DQ
16A
55
DQ
17A
56
DQ
18A
57
DQ
19A
58
V3_
3A
59
DQ
20A
60
NC
A61
DU
A62
NC
A63
GN
DA
64
DQ
21A
65
DQ
22A
66
DQ
23A
67
GN
DA
68
DQ
24A
69
DQ
25A
70
DQ
26A
71
DQ
27A
72
V3_
3A
73
DQ
28A
74
DQ
29A
75
DQ
30A
76
DQ
31A
77
GN
DA
78
NC
A79
NC
A80
NC
A81
SD
AA
82
SC
LA
83
V3_
3A
84
DQ
49B
140
DQ
50B
141
DQ
51B
142
DQ
52B
144
NC
B14
5
DU
B14
6
NC
B14
7
DQ
53B
149
DQ
54B
150
DQ
55B
151
DQ
56B
153
DQ
57B
154
DQ
58B
155
DQ
59B
156
DQ
60B
158
DQ
61B
159
DQ
62B
160
DQ
63B
161
GN
DB
162
NC
B16
3
NC
B16
4
SA
0B
165
SA
1B
166
SA
2B
167
V3_
3B
168
DQ
8A
11
GN
DA
12
DQ
9A
13
DQ
10A
14
DQ
11A
15
DQ
12A
16
DQ
13A
17
V3_
3A
18
DQ
14A
19
DQ
15A
20
CB
0A
21
CB
1A
22
GN
DA
23
NC
A24
NC
A25
V3_
3A
26
WE
0A
27
CA
S0
A28
CA
S1
A29
RA
S0
A30
OE
0A
31
GN
DA
32
A0
A33
A2
A34
A4
A35
A6
A36
A8
A37
A10
A38
NC
A39
V3_
3A
40
DQ
39B
94
DQ
40B
95
GN
DB
96
DQ
41B
97
DQ
42B
98
DQ
43B
99
DQ
44B
100
DQ
45B
101
V3_
3B
102
DQ
46B
103
DQ
47B
104
CB
4B
105
CB
5B
106
GN
DB
107
NC
B10
8
NC
B10
9
V3_
3B
110
DU
B11
1
CA
S4
B11
2
CA
S5
B11
3
NC
B11
4
DU
B11
5
GN
DB
116
A1
B11
7
A3
B11
8
A5
B11
9
A7
B12
0
A9
B12
1
A11
B12
2
NC
B12
3
V3_
3B
124
DU
B12
5
DU
B12
6
GN
DB
127
DU
B12
8
NC
B12
9
CA
S6
B13
0
CA
S7
B13
1
DU
B13
2
V3_
3B
133
NC
B13
4
NC
B13
5
CB
6B
136
CB
7B
137
GN
DB
138
DQ
48B
139
J5 Mol
ex 7
1736
-000
11GN
DB
85G
ND
A01
DQ
32B
86
DQ
33B
87D
Q0
A02
DQ
34B
88D
Q1
A03
DQ
35B
89
V3_
3B
90
DQ
2A
04
DQ
36B
91
DQ
3A
05
DQ
37B
92
DQ
38B
93
V3_
3A
06
DQ
4A
07
DQ
5A
08
DQ
6A
09
DQ
7A
10
V3_
3B
157
GN
DB
148
GN
DB
152
V3_
3B
143
V3_
3A
41
DU
A42
GN
DA
43
OE
2A
44
RA
S2
A45
CA
S2
A46
CA
S3
A47
WE
2A
48
V3_
3A
49
NC
A50
NC
A51
CB
2A
52
CB
3A
53
GN
DA
54
DQ
16A
55
DQ
17A
56
DQ
18A
57
DQ
19A
58
V3_
3A
59
DQ
20A
60
NC
A61
DU
A62
NC
A63
GN
DA
64
DQ
21A
65
DQ
22A
66
DQ
23A
67
GN
DA
68
DQ
24A
69
DQ
25A
70
DQ
26A
71
DQ
27A
72
V3_
3A
73
DQ
28A
74
DQ
29A
75
DQ
30A
76
DQ
31A
77
GN
DA
78
NC
A79
NC
A80
NC
A81
SD
AA
82
SC
LA
83
V3_
3A
84
DQ
49B
140
DQ
50B
141
DQ
51B
142
DQ
52B
144
NC
B14
5
DU
B14
6
NC
B14
7
DQ
53B
149
DQ
54B
150
DQ
55B
151
DQ
56B
153
DQ
57B
154
DQ
58B
155
DQ
59B
156
DQ
60B
158
DQ
61B
159
DQ
62B
160
DQ
63B
161
GN
DB
162
NC
B16
3
NC
B16
4
SA
0B
165
SA
1B
166
SA
2B
167
V3_
3B
168
DQ
8A
11
GN
DA
12
DQ
9A
13
DQ
10A
14
DQ
11A
15
DQ
12A
16
DQ
13A
17
V3_
3A
18
DQ
14A
19
DQ
15A
20
CB
0A
21
CB
1A
22
GN
DA
23
NC
A24
NC
A25
V3_
3A
26
WE
0A
27
CA
S0
A28
CA
S1
A29
RA
S0
A30
OE
0A
31
GN
DA
32
A0
A33
A2
A34
A4
A35
A6
A36
A8
A37
A10
A38
NC
A39
V3_
3A
40
DQ
39B
94
DQ
40B
95
GN
DB
96
DQ
41B
97
DQ
42B
98
DQ
43B
99
DQ
44B
100
DQ
45B
101
V3_
3B
102
DQ
46B
103
DQ
47B
104
CB
4B
105
CB
5B
106
GN
DB
107
NC
B10
8
NC
B10
9
V3_
3B
110
DU
B11
1
CA
S4
B11
2
CA
S5
B11
3
NC
B11
4
DU
B11
5
GN
DB
116
A1
B11
7
A3
B11
8
A5
B11
9
A7
B12
0
A9
B12
1
A11
B12
2
NC
B12
3
V3_
3B
124
DU
B12
5
DU
B12
6
GN
DB
127
DU
B12
8
NC
B12
9
CA
S6
B13
0
CA
S7
B13
1
DU
B13
2
V3_
3B
133
NC
B13
4
NC
B13
5
CB
6B
136
CB
7B
137
GN
DB
138
DQ
48B
139
C4
0.01
uFC
50.
1uF
C6
0.1u
FC
70.
1uF
C8
0.1u
FC
90.
1uF
C10
0.1u
FC
110.
1uF
C21
0.1u
FC
220.
1uF
C23
0.1u
FC
240.
01uF
C25
0.1u
FC
260.
1uF
C27
0.1u
FC
10.
001u
FC
20.
001u
FC
30.
001u
FC
370.
01uF
C36
0.00
1uF
C39
0.00
1uF
C38
0.00
1uF
C19
100u
FC
2010
0uF
PIIX3: PCI DEVICE 1 (AD12)
SYSCLK=0 on PWROK ->PCICLK/4
33MHz/4=8.25MHz
DO NOT
STUFF
Place close to PIN 132 on
PIIX3
XBUS
Standard
Stuff
Option
U1 GND: 1,2,26,42,51,52,65,79,105,106,131,133,155,156,170,182,195 | 111, 147
U1 V5_0: 27, 53, 54,78, 103, 104, 157, 158, 183, 196, 207, 208
U1 V3_3: | 130, 134
NOTE1: 5 mil trace/space gives ~70 Ohm Zo for PCI bus as d-stripline
DO NOT
STUFF
Place close to
PIN 146 on
PIIX3
SCHMITT
DO NOT
STUFF
Push-Pull
INTEL 82371SB PCI ISA IDE XCELERATOR
{Doc
}1.
00
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S D
esig
n G
uide
: 82
371S
B P
CI t
o IS
A B
ridge
A4
518
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SA
[19:
0]
AD
[31:
0]
DD
[15:
0]
LA[2
3:17
]
-C/B
E[3
:0]
-PIR
Q[3
:0]
SD
[15:
0]
XD
[7:0
]S
D[1
5:0]
-PIR
Q0
AD
21
AD
17
AD
10
AD
25
DD
12
DD
6
-IO
W_R
AD
26
AD
20
AD
11
AD
6
DD
3
LA20
DD
14
-PIR
Q3
AD
13
AD
9
AD
18
AD
12
AD
7
-C/B
E3
SA
2
AD
12
PC
LK_P
IIX
3
AD
27
AD
16
LA17
SA
0
TC
_R
-SM
EM
R_R
AD
4
DD
13
AD
0
-C/B
E0
DD
1
LA18
-PIR
Q2
OS
C
AD
31
AD
8
DD
2
SA
1
AD
15
LA22
LA21
-PIR
Q1
-IO
R_R
AD
28
AD
19
-ME
MR
_R
AD
24A
D23
AE
N_R
AD
1
DD
15
AD
29
SY
S_C
LK
DD
11
DD
7
DD
4
LA19
AD
30
-SM
EM
W_R
AD
5
-C/B
E2
SA
5
SA
3
AD
22
AD
14
DD
8
SA
6
-ME
MW
_R
-C/B
E1
DD
10
LA23
SA
4
DD
0
AD
3A
D2
DD
9
DD
5
SA
7
BA
LE_R
-TE
ST
IN
TC
_R
-IO
R_R
-ME
MW
_R
-IO
W_R
AE
N_R
-SM
EM
W_R
-ME
MR
_R
PC
LK_P
IIX
3
SD
3
SD
5
SD
12
SD
4
SD
0
SD
14
SD
6
SD
8
SD
11
SD
1
SD
10
SD
13
SD
7
SD
15
SD
9
SD
2
SD
5X
D4
SD
1
SD
3S
D4
XD
5S
D6
XD
6
SD
2
SD
0
XD
2X
D3
XD
7S
D7
XD
1X
D0
BA
LE_R
-SM
EM
R_R 24
MH
Z
-C/B
E[3
:0]
3,7,
13
DD
[15:
0]6
AD
[31:
0]3,
7,13
-IO
W8,
9,10
-SM
EM
R8,
9
-SM
EM
W8,
9
SD
[15:
0]8,
9,10
,11
LA[2
3:17
]6,
8,9
SA
[19:
0]6,
8,9,
10,1
1
-PIR
Q[3
:0]
7,9,
13
-IO
CS
166,
8,9
-PH
LDA
3
-IR
DY
3,7,
9,13
NM
I3,
9
IOC
HR
DY
8,9,
10
-IG
NN
E3,
9
-SE
RR
3,7,
9
PC
LK_P
IIX
33
PA
R3,
7,9,
13
-FR
AM
E3,
7,9,
13
SD
IR6
-SM
I3,
9
-DD
AC
K0
6
-ME
MC
S16
8,9
-FE
RR
3,8
-ST
OP
3,7,
9,13
-0W
S8,
9,10
-DE
VS
EL
3,7,
9,13
-TR
DY
3,7,
9,13
-IO
CH
CK
8,9
INT
R3,
9
-DIO
R6
-ST
PC
LK3,
9
CP
UR
ST
3,9
SP
KR
18
-BIO
SC
S11
IOR
DY
6
PIIX
3_IN
IT
9
-PC
IRS
T3,
7,13
-RE
FR
ES
H8,
9
-SO
E6
PW
OK
18
-DIO
W6
AE
N8,
10,1
1
TC
8,10
IRQ
19,
10IR
Q3
8,9,
10IR
Q4
8,9,
10IR
Q5
8,9,
10IR
Q6
8,9,
10IR
Q7
8,9,
10-I
RQ
89,
10IR
Q9
8,9,
10IR
Q10
8,9,
10IR
Q11
8,9,
10IR
Q12
8,9,
10IR
Q14
6,8,
9,10
IRQ
158,
9,10
DD
RQ
06
RS
TD
RV
8,10
-RS
TD
RV
6
-ME
MR
8,9,
11
BA
LE8,
9
-IO
R8,
9,10
-ME
MW
8,9,
11
DR
Q3
8,9,
10D
RQ
28,
9,10
DR
Q1
8,9,
10D
RQ
08,
9,10
DR
Q7
8,9
DR
Q5
8,9
DR
Q6
8,9
-DA
CK
08,
10-D
AC
K1
8,10
-DA
CK
28,
10-D
AC
K3
8,10
-DA
CK
58
-DA
CK
68
-DA
CK
78
SY
SC
LK8
XD
[7:0
]11
14M
HZ
3,8,
13
24M
HZ
3
-PH
LD3
V5_
0
V3_
3
V5_
0
V5_
0
V5_
0
V5_
0
R5
10K
R7
22
R9
220
R4
22
R6
0
C62
0
TP
15
PC
LK_P
IIX
3
TP
TP
17B
IOS
CS
#
TP
TP
1414
MH
Z
TP
C63
0
TP
16
24M
HZ
TP
R11 4.
7K
R10
4.7K
C54
0.1u
FC
560.
1uF
C55
0.1u
FC
590.
1uF
C58
0.1u
FC
570.
1uF
C60
0.1u
FC
610.
1uF
U3
74A
LS2
45
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G19
DIR
1
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
U4A
74H
CT
14
12
C64
0.1u
F
C49
0.1u
FC
500.
1uF
C51
0.1u
FC
520.
1uF
C53
0.1u
FC
480.
01uF
C45
0.00
1uF
C46
0.00
1uF
C44
0.00
1uF
C47
0.00
1uF
RP
5
22
18
27
36
45
RP
6
22
18
27
36
45
C65
0.01
uF
C43
10uF
C42
10uF
C66
0.1u
F
C41
10uF
C40
10uF
R3
1K
R8
0
U1
8237
1SB
(P
IIX3)V5_0
27
GND 1
V5_053
IOR
DY
114
V5_054GND 2
V5_078
RT
CA
LE14
8
V5_0103 GND 26V5_0104
DIO
R11
3
V5_0157
GND 42
V5_0158
DA
CK
085
V5_0169
GND 51
V5_0183
DIO
W11
2
V5_0196
GND 52
V5_0207
BIO
SC
S13
7
V5_0208
GND 65
DD
AK
011
5
GND 79
SD
017
GND 105
DD
AK
111
6
GND 106R
TC
CS
138
GND 131
SO
E11
9
GND 133
DA
CK
129
GND 155
SD
IR11
8
GND 156
KB
CS
139
GND 170
US
BP
0-14
5
GND 182
RS
TD
RV
28
GND 195
DA
CK
260
SD
116
DA
CK
321
SA
069
DA
CK
589
SD
214
DA
CK
693
US
BP
0+14
4
DA
CK
797
SD
313
LA17
/DA
086
SD
411
US
BP
1-14
3
SD
59
SA
168
SD
68
US
BP
1+14
2
SD
77
DD
0/S
A8
55
SD
892
SA
267
SD
994
LA18
/DA
184
SD
1096
SA
366
SD
1198
DR
EQ
087
SD
1210
0
SA
463
SD
1310
1
LA19
/DA
282
SD
1410
2
SA
561
SD
1510
7
DD
1/S
A9
50
SA
659
LA20
/CS
3P80
SA
757
IRQ
14
LA21
/CS
1P76
DD
2/S
A10
49
LA22
/CS
3S74
DR
EQ
130
LA23
/CS
1S72
DD
3/S
A11
48
FR
AM
E17
9
DD
4/S
A12
47
DR
EQ
212
DD
5/S
A13
46
IRQ
358
DD
6/S
A14
45
DR
EQ
325
DD
7/S
A15
44
C/B
E0
198
DD
8/S
A16
43
DR
EQ
591
DD
9/S
A17
41
IRQ
456
DD
10/S
A18
40
DR
EQ
695
DD
11/S
A19
39
TR
DY
181
DD
12/S
BH
E38
DR
EQ
799
IRQ
534
AD
020
6
IRQ
633
IRD
Y18
0
IRQ
732
C/B
E1
187
IRQ
85
ST
OP
185
IRQ
910
PA
R18
6
IRQ
1073
C/B
E2
178
IRQ
1175
AD
120
5
IRQ
12/M
77
C/B
E3
167
IRQ
1483
PH
OLD
109
IRQ
1581
AD
220
4
SY
SC
LK15
3
AD
320
3
BA
LE64
AD
420
2
AE
N20
AD
520
1
AD
620
0
AD
719
9
AD
819
7
AD
919
4
AD
1019
3
AD
1119
2
AD
1219
1
AD
1319
0
AD
1418
9
AD
1518
8
AD
1617
7
AD
1717
6
AD
1817
5
AD
1917
4
AD
2017
3
AD
2117
2
AD
2217
1
AD
2316
8
AD
2416
6
MIR
Q0/
IRQ
014
7
AD
2516
5
ME
MC
S16
70
AD
2616
4
ME
MW
90
AD
2716
3
SM
EM
W22
AD
2816
2
ME
MR
88
AD
2916
1
SM
EM
R19
AD
3016
0
IOC
HR
DY
18
AD
3115
9
IOR
23
IOW
24
VC
C/V
CC
313
0
INT
R12
2
SM
I12
3
ST
PC
LK12
4
NM
I13
5
IGN
NE
121
TC
62
RE
FR
ES
H31
SP
KR
117
XD
IR14
1
XO
E14
0
CP
UR
ST
127
PC
IRS
T/A
PIC
AC
K12
8
TE
ST
IN/A
PIC
RE
Q13
4
INIT
129
PW
RO
K12
6
PC
ICLK
132
OS
C13
6
IDS
EL
154
DE
VS
EL
184
PIR
QA
149
PIR
QB
150
PIR
QC
151
PIR
QD
152
SE
RR
3
PH
LDA
110
FE
RR
120
EX
TS
MI
125
IOC
S16
71
IOC
HK
6
ZE
RO
WS
15
DD
1337
DD
14/A
PIC
CS
36
DD
15/P
CS
35
DD
RQ
010
8
DD
RQ
111
1
US
BC
LK14
6
U2A
74A
CT
04
12
IDE Interface
DIR=1 A to B
HD Active LED
DIR=1 A to B
V5_0 = VCC:
U4, U5 20
U6, U7 20
GND:
U4, U5 10
U6, U7 7 DO NOT STUFF
DD15/PCS# &
DD14/APICCS#
not used so
strap
NOTE 1: Cuttable trace RP7 to V5_0
{Doc
}1.
00
PO
S D
esig
n G
uide
: IS
A In
terf
ace
A4
618
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PD
D[1
5:0]
DD
[15:
0]
SA
[19:
0]
LA[2
3:17
]
DD
3P
DD
5S
A11
SA
8
DD
1
DD
6
DD
8
DD
3
D_S
A12
DD
5
D_S
A10
IOC
HR
DY
_0
SA
10
DD
7
DD
2
PD
D7
PD
D0
PD
D0
-HD
AC
T_0
DD
4
DD
1
PD
D12
PD
D13
PD
D10
PD
D13
PD
D14
D_S
A9
-DM
AC
K_0
SA
14
DD
15
PD
D11
PD
D4
PD
D3
PD
D4
PD
D7
PD
D8
PD
D6
PD
D10
PD
D3
PD
D2
PD
D8
A_D
A0
A_D
A1
DIR
Q_0
-DIO
R_0
DA
1 DA
0
-B_C
S1
DD
14
PD
D2
SA
12
SA
9
DR
EQ
_0
DD
2
DD
13
D_S
A13
D_S
A15
DD
4
PD
D9
PD
D15
PD
D15
DD
0
DD
11
DD
6
D_S
A14
SA
15
DD
12
-RE
SE
T
-CS
3
DD
5
DD
7
DD
10
DD
0
PD
D9
PD
D11
D_S
A8
-A_C
S1
-A_C
S3
PD
D1
PD
D1
DD
9
D_S
A11
-DIO
W_0
SA
13
PD
D5
PD
D14
PD
D6
PD
D12
DA
2
A_D
A2
-PD
IAG
SP
SY
NC
DD
12
SA
17D
_SA
17
SA
19D
_SA
19D
D10
DD
9D
D8
D_S
A18
DD
11
D_S
A16
DD
15
SA
18
SA
16
LA20
LA21
LA17
LA19
LA18
A_D
D15
V5_
OU
T
V5_
IN
-DD
AC
K0
5
-DIO
W5
-DIO
R5
-RS
TD
RV
5
LA[2
3:17
]5,
8,9
IOR
DY
5
-IO
CS
165,
8,9,
DD
RQ
05
IRQ
145,
8,9,
10
-SO
E5
SD
IR5
DD
[15:
0]5
SA
[19:
0]5,
8,9,
10,1
1
-SB
HE
8,9
V5_
0
V5_
0
V5_
0
V5_
0
V5_
0
V5_
0
V5_
0
TP
18P
DIA
G#
TP
RP
15
33
18
27
36
45
RP
16
33
18
27
36
45
RP
13
33
18
27
36
45
RP
11
33
18
27
36
45
RP
8
33
18
27
36
45
RP
9
33
18
27
36
45
RP
10
33
18
27
36
45
RP
12
33
18
27
36
45
RP
14
33
18
27
36
45
R12 47
R13 33
R17 47
R15 47
R14
10K
R18
1K
R20
215
J7 IDE
Con
n
RE
SE
T1
D7
3
D6
5
D5
7
D4
9
D3
11
D2
13
D1
15
D0
17
GN
D19
DR
EQ
21
DIO
W23
DIO
R25
IOC
HR
DY
27
DM
AC
K29
DIR
Q31
DA
133
DA
035
CS
137
HD
AC
T39
GN
D2
D8
4
D9
6
D10
8
D11
10
D12
12
D13
14
D14
16
D15
18
KE
Y20
GN
D22
GN
D24
GN
D26
SP
SY
NC
28
GN
D30
IOC
S16
32
PD
IAG
34
DA
236
CS
338
GN
D40
U8B
74A
LS0
0
4 56
U8A
74A
LS0
0
1 23
U7A
74A
LS08
1 23
U7B
74A
LS08
4 56
U7C
74A
LS08
9
108
U6
74A
LS2
45
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G19
DIR
1
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
U5
74A
LS2
45
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G19
DIR
1
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
D1
LGS
260-
DO
IN2
NC1
OUT 3
R16
0
RP
7
10K
18
27
36
45
C67
0.1u
F
C68
0.1u
F
R19
1K
PCI SLOT 0
PCI SLOT 1
DO NOT
STUFF
DO NOT
STUFF
Place close to PCI Slot 0
Place close to PCI Slot 1
J6/J7 V5_0:
A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4
B5, B6, B19, B22, B59, B61, B62
J6/J7 V3_3:
A21, A27, A33, A39 A45, A53
B25, B31, B36, B41, B43, B54
J6/J7 NC:
A9, A11, A14, A19
B10, B14
J6/J7 GND:
A12, A13, A18, A24, A30, A35, A37, A42, A48, A56
B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, B57 | B2
J6/J7 +12V: A2
-12V: B1
PCI SLOTS
{Doc
}1.
00
PO
S D
esig
n G
uide
: P
CI S
lots
0 &
1
A4
18W
edne
sday
, May
13,
199
8
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
-C/B
E[3
:0]
-PIR
Q[3
:0]
-C/B
E3
-C/B
E2
-C/B
E1
-C/B
E0
-PIR
Q1
-PIR
Q3
-PIR
Q0
-PIR
Q2
PC
IA2
-PR
SN
T1
-C/B
E3
-C/B
E2
-C/B
E1
-C/B
E0
-PIR
Q0
-PIR
Q2
-PIR
Q3
-PIR
Q1
-IR
DY
-DE
VS
EL
-PLO
CK
-PE
RR
-SE
RR
PC
IB2
SD
ON
E-S
BO
PA
R
PC
LK_S
LOT
1
-ST
OP
-TR
DY
-FR
AM
E
-PC
IRS
T
-PR
SN
T2
PC
LK_S
LOT
0
-PR
SN
T2
-PR
SN
T1
PC
LK_S
LO
T0
PC
LK_S
LOT
1
AD
26
AD
31
AD
7
AD
28
AD
22A
D20
AD
3
AD
12
AD
8
AD
17
AD
6
AD
18
AD
1A
D2
AD
15
AD
11
AD
19
AD
29
AD
23
AD
28
AD
3
AD
14
AD
21
AD
30
AD
2
AD
22
AD
27
AD
18
AD
10
AD
0
AD
25
AD
14
AD
23
AD
5A
D5
AD
13
AD
9
AD
17
AD
13
AD
29
AD
19
AD
15
AD
4A
D4
AD
25A
D24
AD
6
AD
10
AD
16
AD
8
AD
28
AD
21
AD
29A
D30
AD
26
AD
9
AD
20
AD
31
AD
1A
D0
AD
24
AD
27
AD
16
AD
11A
D12
AD
7
AD
[31:
0]3,
5,13
-C/B
E[3
:0]
3,5,
13
-PIR
Q[3
:0]
5,9,
13
PC
LK_S
LOT
03
-PR
EQ
03
-IR
DY
3,5,
9,13
-DE
VS
EL
3,5,
9,13
-PLO
CK
3,9
-PE
RR
9-S
ER
R3,
5,9
-PC
IRS
T3,
5,13
-PG
NT
03
-FR
AM
E3,
5,9,
13
-TR
DY
3,5,
9,13
-ST
OP
3,5,
9,13
SD
ON
E9
-SB
O9
PA
R3,
5,9,
13
PC
LK_S
LOT
13
-PG
NT
13
-PR
EQ
13
V3_
3V
5_0
V3_
3V
5_0
+12V
+12V
V5_
0
V5_
0V
5_0
V5_
0V
5_0
V5_
0
AD
[31:
0]
C76
0.1u
FC
770.
1uF
C96
0.1u
F
C93
0.1u
FC
950.
1uF
C94
0.1u
F
R21
220
R22
220
R24
10
C98
100p
F
R23
0
C97
0
C75
10uF
C72
0.1u
FC
700.
1uF
C69
10uF
C74 0.01
uFC
730.
01uF
C71
0.1u
F
J9 PC
I Con
n
V5_
0A
8
TR
ST
A1
NC
A9
V5_
0A
10
+12V
A2
-12V
B1
TM
SA
3
TD
IA
4
AC
K64
B6
0
V5_
0A
5
INT
AA
6
V3_
3B
36
INT
CA
7
NC
A11
V5_
0B
61
GN
DA
12
GN
DA
13
TC
KB
2
NC
A14
RS
TA
15
DE
VS
EL
B3
7
V5_
0A
16
GN
TA
17
GN
DB
3
GN
DA
18
GN
DB
38
NC
A19
V5_
0B
62
AD
[30]
A20
TD
OB
4
V3_
3A
21
LOC
KB
39
V5_
0B
5
PE
RR
B4
0
V5_
0B
6
V3_
3B
41
INT
BB
7
SE
RR
B4
2
INT
DB
8
V3_
3B
43
PR
SN
T1
B9
C/B
E1
B4
4
AD
[28]
A22
NC
B1
0
AD
[26]
A23
AD
[14]
B4
5
GN
DA
24
PR
SN
T2
B1
1
AD
[24]
A25
GN
DB
12
IDS
EL
A26
GN
DB
13
V3_
3A
27
NC
B1
4
AD
[22]
A28
GN
DB
46
AD
[20]
A29
GN
DB
15
GN
DA
30
CLK
B1
6
AD
[18]
A31
AD
[12]
B4
7
AD
[16]
A32
GN
DB
17
V3_
3A
33
RE
QB
18
FR
AM
EA
34
AD
[10]
B4
8
GN
DA
35
V5_
0B
19
TR
DY
A36
AD
[31]
B2
0
GN
DA
37
GN
DB
49
ST
OP
A38
AD
[29]
B2
1
V3_
3A
39
GN
DB
22
SD
ON
EA
40
AD
[08]
B5
2
SB
OA
41
AD
[27]
B2
3
GN
DA
42
AD
[25]
B2
4
PA
RA
43
AD
[07]
B5
3
AD
[15]
A44
V3_
3B
25
V3_
3A
45
C/B
E3
B2
6
AD
[13]
A46
V3_
3B
54
AD
[11]
A47
AD
[23]
B2
7
GN
DA
48
GN
DB
28
AD
[09]
A49
AD
[05]
B5
5
C/B
E0
A52
AD
[21]
B2
9
V3_
3A
53
AD
[19]
B3
0
AD
[06]
A54
AD
[03]
B5
6A
D[0
4]A
55
V3_
3B
31
GN
DA
56
AD
[17]
B3
2
AD
[02]
A57
GN
DB
57
AD
[00]
A58
C/B
E2
B3
3
V5_
0A
59
GN
DB
34
RE
Q64
A60
AD
[01]
B5
8
V5_
0A
61
IRD
YB
35
V5_
0A
62
V5_
0B
59
C88
0.1u
FC
890.
1uF
C87
10uF
C84
0.1u
FC
820.
1uF
C81
10uF
C86 0.01
uFC
850.
01uF
C83
0.1u
FC
790.
1uF
C80
0.1u
FC
7810
uFC
910.
1uF
C92
0.1u
FC
9010
uF
J8 PC
I Con
n
V5_
0A
8
TR
ST
A1
NC
A9
V5_
0A
10
+12V
A2
-12V
B1
TM
SA
3
TD
IA
4
AC
K64
B60
V5_
0A
5
INT
AA
6
V3_
3B
36
INT
CA
7
NC
A11
V5_
0B
61
GN
DA
12
GN
DA
13
TC
KB
2
NC
A14
RS
TA
15
DE
VS
EL
B37
V5_
0A
16
GN
TA
17
GN
DB
3
GN
DA
18
GN
DB
38
NC
A19
V5_
0B
62
AD
[30]
A20
TD
OB
4
V3_
3A
21
LOC
KB
39
V5_
0B
5
PE
RR
B40
V5_
0B
6
V3_
3B
41
INT
BB
7
SE
RR
B42
INT
DB
8
V3_
3B
43
PR
SN
T1
B9
C/B
E1
B44
AD
[28]
A22
NC
B10
AD
[26]
A23
AD
[14]
B45
GN
DA
24
PR
SN
T2
B11
AD
[24]
A25
GN
DB
12
IDS
EL
A26
GN
DB
13
V3_
3A
27
NC
B14
AD
[22]
A28
GN
DB
46
AD
[20]
A29
GN
DB
15
GN
DA
30
CLK
B16
AD
[18]
A31
AD
[12]
B47
AD
[16]
A32
GN
DB
17
V3_
3A
33
RE
QB
18
FR
AM
EA
34
AD
[10]
B48
GN
DA
35
V5_
0B
19
TR
DY
A36
AD
[31]
B20
GN
DA
37
GN
DB
49
ST
OP
A38
AD
[29]
B21
V3_
3A
39
GN
DB
22
SD
ON
EA
40
AD
[08]
B52
SB
OA
41
AD
[27]
B23
GN
DA
42
AD
[25]
B24
PA
RA
43
AD
[07]
B53
AD
[15]
A44
V3_
3B
25
V3_
3A
45
C/B
E3
B26
AD
[13]
A46
V3_
3B
54
AD
[11]
A47
AD
[23]
B27
GN
DA
48
GN
DB
28
AD
[09]
A49
AD
[05]
B55
C/B
E0
A52
AD
[21]
B29
V3_
3A
53
AD
[19]
B30
AD
[06]
A54
AD
[03]
B56
AD
[04]
A55
V3_
3B
31
GN
DA
56
AD
[17]
B32
AD
[02]
A57
GN
DB
57
AD
[00]
A58
C/B
E2
B33
V5_
0A
59
GN
DB
34
RE
Q64
A60
AD
[01]
B58
V5_
0A
61
IRD
YB
35
V5_
0A
62
V5_
0B
59R
26
2.7K
R25
2.7K
R27
2.7K
R28
2.7K
ISA Slots
J10/11 V5_0:
B03, B29,
B31, D16
J10/11 GND:
B01, B10, D18
J10/11: +12V B09
-12V B07
-5V B05
DO NOT
STUFF
Place close to connectors
Place close to connectors
Note Cap Direction
Note Cap Direction
NOTE 1: ISA Conn B is a shared slot with PCI slot 3
(see ATX spec)
Note Cap Direction
Note Cap Direction
Do Not Stuff
DO NOT
STUFF
{Doc
}1.
00
PO
S D
esig
n G
uide
: IS
A S
ocke
ts
A4
818
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
LA[2
3:17
]
SD
[15:
0]
SA
[19:
0]
SA
7
SA
12
LA21
SD
12D
RQ
7
-DA
CK
6
SA
14
AE
N
SD
9
SD
7R
ST
DR
V
SA
15
SA
5
-MA
ST
ER
IOC
HR
DY
SD
1
SA
17
SD
7
SD
11
SD
5
-IO
CH
CK
IRQ
14
SD
10
LA23
SA
9
DR
Q6
SD
15
-IO
CS
16
LA1
9
SD
13
SA
3
SD
8
-0W
S
LA2
3
SA
2
SD
1
LA17
DR
Q3
LA2
0
SA
16
LA19
SD
9
LA22
SA
6
SA
15S
A16
SA
17-I
OW
SD
6
-SB
HE
SA
0
LA20
IRQ
7
-ME
MW
-RE
FR
ES
H
-DA
CK
1
LA1
8
SA
0
SA
11
SD
13
IRQ
5
SD
2
LA2
1
SD
3
SD
6
SA
1
IRQ
6
LA1
7
-IO
R
-SM
EM
R
SD
2
SA
14S
A13
SD
15
-ME
MC
S16
SY
SC
LK
-DA
CK
3
SA
2
SA
4
SA
6
SA
18
-DA
CK
2
SD
4
SA
4
IRQ
12
14M
HZ
_IS
A
IRQ
4
SD
3
SD
8
SA
18
SD
14
-DA
CK
7
SA
10
SA
12
-DA
CK
5
-DA
CK
0
IRQ
15
SD
14
SD
12
SA
19
SD
11
TC
SD
5
SA
8S
A9
SA
11
SA
5
SA
13
-SM
EM
W
LA2
2
IRQ
9
SA
10
LA18
SD
0
SA
3
SA
1
SA
7S
A8
DR
Q5
DR
Q0
IRQ
11IR
Q10
BA
LE
IRQ
3
-ME
MR
DR
Q2
SA
19
SD
10
SD
0
DR
Q1
SD
4
SY
SC
LK14
MH
Z
14M
HZ
_IS
A
-MA
ST
ER
9
IRQ
105,
9,10
IOC
HR
DY
5,9,
10
-ME
MW
5,9,
11
IRQ
155,
9,10
-IO
CS
165,
6,9
-ME
MC
S16
5,9
TC
5,10
IRQ
145,
6,9,
10
IRQ
125,
9,10
AE
N5,
10,1
1
IRQ
115,
9,10
IRQ
95,
9,10
-IO
CH
CK
5,9
-0W
S5,
9,10
-ME
MR
5,9,
11
SA
[19:
0]5,
6,9,
10,1
1
SD
[15:
0]5,
9,10
,11
LA[2
3:17
]5,
6,9
-SB
HE
6,9
RS
TD
RV
5,10
BA
LE5,
9
-RE
FR
ES
H5,
9
IRQ
65,
9,10
IRQ
35,
9,10
IRQ
45,
9,10
IRQ
55,
9,10
IRQ
75,
9,10
DR
Q5
5,9
-DA
CK
55
DR
Q0
5,9,
10-D
AC
K0
5,10
DR
Q7
5,9
-DA
CK
75
DR
Q6
5,9
-DA
CK
65
-DA
CK
25,
10
DR
Q3
5,9,
10-D
AC
K1
5,10
DR
Q1
5,9,
10
DR
Q2
5,9,
10
SY
SC
LK5
-IO
R5,
9,10
-DA
CK
35,
10
-SM
EM
R5,
9-I
OW
5,9,
10,1
1
-SM
EM
W5,
9
14M
HZ
3,5,
13
+12
V+1
2V-1
2V-1
2V-5
V-5
V
V5_
0-1
2V+1
2V-5
VV
5_0
-12V
-5V
V5_
0
J11
ISA
Con
n B
GN
DB
01
SB
HE
C01
RS
TD
RV
B0
2S
D7
A02
V5_
0B
03
LA23
C02
IRQ
9B
04
SD
6A
03
-5V
B0
5
LA22
C03
DR
Q2
B0
6
LA21
C04
-12V
B0
7
SD
5A
04
0WS
B0
8
+12V
B0
9
LA20
C05
GN
DB
10
SD
4A
05
SM
EM
WB
11
LA19
C06
SM
EM
RB
12
SD
3A
06
IOW
B1
3
LA18
C07
IOR
B1
4
DA
CK
3B
15
SD
2A
07
DR
Q3
B1
6
LA17
C08
DA
CK
1B
17
ME
MR
C09
DR
Q1
B1
8
SD
1A
08
RE
FR
ES
HB
19
ME
MW
C10
CLK
B2
0
SD
0A
09
IRQ
7B
21
SD
8C
11
IRQ
6B
22
IRQ
5B
23
SD
9C
12
IRQ
4B
24
IOC
HR
DY
A10
IRQ
3B
25
SD
10C
13
DA
CK
2B
26
AE
NA
11
TC
B2
7
SD
11C
14
BA
LEB
28
V5_
0B
29
SA
19A
12
OS
CB
30
SD
12C
15
GN
DB
31
SD
13C
16
MC
S16
D01
SA
18A
13
IOC
S16
D02
SD
14C
17
IRQ
10D
03
SA
17A
14
IRQ
11D
04
SA
16A
15
IRQ
12D
05
SD
15C
18
IRQ
15D
06
SA
15A
16
IRQ
14D
07
DA
CK
0D
08
SA
14A
17
DR
Q0
D09
SA
13A
18
DA
CK
5D
10
SA
12A
19
DR
Q5
D11
DA
CK
6D
12
SA
11A
20
DR
Q6
D13
SA
10A
21
DA
CK
7D
14
SA
9A
22
DR
Q7
D15
V5_
0D
16
SA
8A
23
MA
ST
ER
D17
SA
7A
24
GN
DD
18
IOC
HC
KA
01
SA
6A
25
SA
5A
26
SA
4A
27
SA
3A
28
SA
2A
29
SA
1A
30
SA
0A
31
R30
0
C12
60
TP
19
SY
SC
LK
TP
TP
20
14M
HZ
_IS
A
TP
C12
70
C11
10.
1uF
C11
00.
1uF
C10
90.
1uF
C10
810
uFC
104
0.1u
FC
103
0.1u
FC
102
10uF
C10
60.
1uF
C10
510
uFC
107
0.1u
FC
9910
uFC
100
0.1u
FC
101
0.1u
F
J10
ISA
Con
n A
GN
DB
01
SB
HE
C01
RS
TD
RV
B02
SD
7A
02
V5_
0B
03
LA23
C02
IRQ
9B
04S
D6
A03
-5V
B05
LA22
C03
DR
Q2
B06
LA21
C04
-12V
B07
SD
5A
04
0WS
B08
+12V
B09
LA20
C05
GN
DB
10
SD
4A
05
SM
EM
WB
11
LA19
C06
SM
EM
RB
12
SD
3A
06
IOW
B13
LA18
C07
IOR
B14
DA
CK
3B
15
SD
2A
07
DR
Q3
B16
LA17
C08
DA
CK
1B
17
ME
MR
C09
DR
Q1
B18
SD
1A
08
RE
FR
ES
HB
19
ME
MW
C10
CLK
B20
SD
0A
09
IRQ
7B
21
SD
8C
11
IRQ
6B
22
IRQ
5B
23
SD
9C
12
IRQ
4B
24
IOC
HR
DY
A10
IRQ
3B
25
SD
10C
13
DA
CK
2B
26
AE
NA
11
TC
B27
SD
11C
14
BA
LEB
28
V5_
0B
29
SA
19A
12
OS
CB
30
SD
12C
15
GN
DB
31
SD
13C
16
MC
S16
D01
SA
18A
13
IOC
S16
D02
SD
14C
17
IRQ
10D
03
SA
17A
14
IRQ
11D
04
SA
16A
15
IRQ
12D
05
SD
15C
18
IRQ
15D
06
SA
15A
16
IRQ
14D
07
DA
CK
0D
08
SA
14A
17
DR
Q0
D09
SA
13A
18
DA
CK
5D
10
SA
12A
19
DR
Q5
D11
DA
CK
6D
12
SA
11A
20
DR
Q6
D13
SA
10A
21
DA
CK
7D
14
SA
9A
22
DR
Q7
D15
V5_
0D
16
SA
8A
23
MA
ST
ER
D17
SA
7A
24
GN
DD
18
IOC
HC
KA
01
SA
6A
25
SA
5A
26
SA
4A
27
SA
3A
28
SA
2A
29
SA
1A
30
SA
0A
31
C11
20.
01uF
C11
30.
01uF
C12
30.
1uF
C12
20.
1uF
C12
10.
1uF
C12
010
uFC
124
0.01
uFC
125
0.01
uFC
119
0.1u
FC
118
0.1u
FC
117
10uF
C11
410
uFC
115
0.1u
FC
116
0.1u
F
R29 1K
R31
0
U2B
74A
CT
04
34
ISA Pullup/Pulldown
PCI Pullup/Pulldown
SD[15:0]
SA[19:0]
CONTROL
+ -IRQ8
DRQ[0:3,5:7]
IRQ1,3:12,14,15
Note: Pullups on Mohave -PREQ/PGNT[3:0]
PIRQ
Note: 64-BIT PCI Strap Off At PCI Connectors
-TRDY/-IRDY/ETC
LA[23:17]
RE
Q/G
NT
Pul
l-ups
{Doc
}1.
00
PO
S D
esig
n G
uide
: IS
A P
ullu
p/P
ulld
own
A4
918
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SA
[19:
0]
LA[2
3:17
]
SD
[15:
0]
SA
13
SA
0
SA
15
SA
9
SA
17
SA
11
SA
16
SA
14
SA
5
SA
2
SA
18
SA
8
SA
10
SA
19
SA
7
SA
1
SA
6
SA
12
SA
3
SA
4
LA1
7LA
18
LA1
9LA
20
LA2
1LA
22
LA2
3
SD
12
SD
1S
D2
SD
7
SD
11
SD
3
SD
6
SD
10S
D9
SD
5
SD
14
SD
8
SD
13
SD
15
SD
0
SD
4
SA
[19:
0]5,
6,8,
10,1
1
SD
[15:
0]5,
8,10
,11
BA
LE5,
8-S
BH
E6,
8
-IO
R5,
8,10
-IO
W5,
8,10
,11
IRQ
15,
10IR
Q3
5,8,
10IR
Q4
5,8,
10IR
Q5
5,8,
10
IRQ
75,
8,10
IRQ
65,
8,10
IRQ
105,
8,10
IRQ
155,
8,10
-0W
S5,
8,10 -R
EF
RE
SH
5,8
-ME
MC
S16
5,8
-IO
CS
165,
6,8
-MA
ST
ER
8 IOC
HR
DY
5,8,
10
-IO
CH
CK
5,8
-PIR
Q2
5,7
-PIR
Q0
5,7
-PIR
Q3
5,7
-PIR
Q1
5,7,
13-S
BO
7
-PLO
CK
3,7
-PE
RR
7S
DO
NE
7
-DE
VS
EL
3,5,
7,13
-TR
DY
3,5,
7,13
-IR
DY
3,5,
7,13
PA
R3,
5,7,
13
-FR
AM
E3,
5,7,
13
-ST
OP
3,5,
7,13
-SE
RR
3,5,
7IN
TR
3,5 -F
ER
R3,
5N
MI
3,5
-SM
I3,
5 -IG
NN
E3,
5 CP
UR
ST
3,5
IRQ
115,
8,10
IRQ
145,
6,8,
10IR
Q12
5,8,
10
IRQ
95,
8,10
-IR
Q8
5,10
LA[2
3:17
]5,
6,8
DR
Q0
5,8,
10D
RQ
15,
8,10
DR
Q2
5,8,
10D
RQ
35,
8,10
DR
Q5
5,8
DR
Q6
5,8
DR
Q7
5,8
-SM
EM
R5,
8-S
ME
MW
5,8
-ME
MW
5,8,
11-M
EM
R5,
8,11
-ST
PC
LK
3,5
PIIX
3_IN
IT
5
-KB
DR
ST
10
INIT
3-PR
EQ
0-P
RE
Q1
-PR
EQ
2-P
RE
Q3
-PG
NT
0-P
GN
T1
-PG
NT
2-P
GN
T3
V5_
0
V5_
0V
5_0 V
5_0
V5_
0
V5_
0V
5_0
V3_
3
V5_
0
V5_
0V
5_0
V3_
3
V5_
0
V5_
0
V3_
3
RP
18
10K
18
27
36
45
RP
20
10K
18
27
36
45
RP
21
10K
18
27
36
45
RP
25
10K
18
27
36
45
RP
30
10K
18
27
36
45
RP
32
10K
18
27
36
45
RP
34
10K
18
27
36
45
RP
36
10K
18
27
36
45
RP
38
10K
18
27
36
45
RP
39
10K
18
27
36
45
RP
40
10K
18
27
36
45
RP
41
10K
18
27
36
45
RP
17
10K
18
27
36
45
RP
19
4.7K
18
27
36
45
RP
22
330
18
27
36
45
RP
26
330
18
27
36
45 RP
31
2.7K
18
27
36
45
RP
33
2.7K
18
27
36
45
RP
35
5.6K
18
27
36
45
RP
37
5.6K
18
27
36
45
RP
23
2.7K
18
27
36
45
RP
24
2.7K
18
27
36
45
RP
27
2.7K
18
27
36
45
RP
29
2.7K
18
27
36
45
RP
28
4.7K
18
27
36
45
C13
010
pF
C13
710
pFC
135
10pF
C12
910
pFC
132
10pF
C13
810
pFC
136
10pF
C13
110
pF
C14
010
pF
C13
410
pF
C13
910
pF
C13
310
pF
R33
4.7K
R35
2.7K
R34
4.7K
R37
330
R32
1K
R36
4.7K
U7D
74A
LS08
12 1311
R39
4.7K
R38
4.7K
R40
330
C12
80.
1uF
U9A
74A
CT
05
12
U2C
74A
CT
04
56
RP
50
2.7K
18
27
36
45
RP
51
2.7K
18
27
36
45
COM0
COM1
FLOPPY
KEYBOARD PARALLEL
(SPP/EPP)
SOUT1/CFG0 (Pin 138) 0 = FDC,KBC,RTC WAKEUP INACTIVE
*1 = FDC, KBC,RTC WAKEUP ACTIVE
-DTRB/CFG1 (Pin 144) *0 = X-BUS DISABLED
1 = X-BUS ENABLED
SOUT1/CFG3 (Pin 148) , RSTB/CFG2 (Pin 146)
00 = Clock Source 24MHZ AT PIN X1
01 = RESERVED
10 = Clock Source 48MHZ AT PIN X1
*11 = Clock Source 32KHZ INTERNAL
MULT
RTS1/BADDR1 (Pin 136), DTR1/BADDR0 (Pin 134)
00 = Full PNP ISA
01 = Wake in Wait for Key (index pnp isa)
10 = PNP Motherbd (wake in config state index 0x15C)
*11 = PNP Motherbd (wake in config state index 0x2E)
CONFIGURATION STRAPPING
(30K unternal pulldown default)
DO NOT STUFF
BLM41A800S: 80Ohm@100MHz/500mA
PS/2 Keyboard/Mouse
V5_0: 1, 24, 61, 100, 121, 140 | 65, 66
GND: 2, 11, 25, 40, 60, 101, 120, 130, 139 | 79, 80
NOTE 1: Place oscillator circuit close to X1C/X2C. Paracitic <=8pF
NOTE 2: Crystal is parallel, resonant, (N cut) or XY bar, Q>=35, Cl=9-13pF
NOTE 3: Test points are a hole/via such that a 25-mil square pin can be inserted.
SUPER I/O
{Doc
}1.
00
PO
S D
ES
IGN
GU
IDE
: Sup
er I/
O
A4
1018
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SA
[19:
0]
SD
[15:
0]
VB
AT
_GN
D
SA
4
SA
7
SA
10
KB
DA
T
SA
1
SA
13
MC
LK
VB
AT
SA
5
SA
8
SD
1
KB
CLK
SA
14
SD
0
SA
9
SD
6
SD
3
SA
3
MD
AT
SA
0
VB
AT
SA
2
SA
15
SD
5
SA
6
SA
12
SD
4
SD
7
SD
2
SA
11
MD
AT
M_C
LK
KB
DA
T
KB
DA
TA
M_V
CC
KB
CLK
KB
_VC
C
MC
LK
MD
AT
A
X2
C
GP
IO10
GP
IO11
GP
IO12
GP
IO13
GP
IO14
GP
IO15
GP
IO16
GP
IO17
GP
IO20
P12
P16
P17
P20
X1
KB
_CLK
-A20
M
GP
IO21
GP
IO22
-CLR
CM
OS
-SW
ITC
HD
TR
112
DT
R0
12
TX
D1
12
TX
D0
12
RT
S1
12
SA
[19:
0]5,
6,8,
9,10
SD
[15:
0]5,
8,9,
10
RT
S0
12
-RD
AT
A12
-DR
VS
A12
DR
Q1
5,8,
9
-IO
R5,
8,9
IRQ
125,
8,9
PP
DR
112
RX
D1
12
-MO
TE
A12
IRQ
95,
8,9
-WA
IT12
FD
DE
N12
-SID
E1
12
DR
Q3
5,8,
9
IRQ
45,
8,9
-IR
Q8
5,9
PP
DR
612
-DIR
12
-MO
TE
B12
PP
DR
012
-AC
K12
SLC
T12
RX
D0
12
-IN
DE
X12
-TR
K0
12
-DA
CK
25,
8
-DS
KC
HG
12
IRQ
35,
8,9
IRQ
155,
8,9
PP
DR
312
-WG
AT
E12
DS
R0
12
CT
S1
12
-DA
CK
05,
8
DC
D0
12
-ER
R12
TC
5,8
IRQ
65,
8,9
DR
AT
E0
12
-WD
AT
A12
DS
R1
12
PP
DR
412
-ST
EP
12
MS
EN
112
DR
Q0
5,8,
9
IRQ
15,
9
IRQ
55,
8,9
-DR
VS
B12
DR
Q2
5,8,
9
MS
EN
012
RI0
12
CT
S0
12
IRQ
145,
6,8,
9
PP
DR
212
PE
12
-DA
CK
35,
8
-IO
W5,
8,9,
11-0W
S5,
8,9
IRQ
115,
8,9
-IN
IT12
IOC
HR
DY
5,8,
9
-WR
ITE
12
RI1
12
AE
N5,
8,11
IRQ
105,
8,9
PP
DR
512
-DA
CK
15,
8
PP
DR
712
-WP
T12
RS
TD
RV
5,8
DC
D1
12
IRQ
75,
8,9
-AS
TR
B12
-KB
DR
ST
9-A
20M
3
32kH
Z13
-DS
TR
B12
AP
PF
LSH
_SA
19A
PP
FLS
H_S
A20
AP
PF
LSH
_SA
21A
PP
FLS
H_W
P#
V5_
0
V5_
0
V5_
0
V5_
0
V5_
0
V5_
0
V3_
3
BT
1H
U 2
032-
1 S
OC
KE
T
R46
10K
R51
10K
C16
022
uF
R45
4.7K
R41
4.7K
R44
4.7K
R42
4.7K
C15
647
0pF
FB
6
BLM
41A
800S
11
22
C15
547
0pF
C15
747
0pF
C15
347
0pF
FB
1B
LM41
A80
0S
11 2 2
FB
3
BLM
41A
800
S
11
22 FB
5
BLM
41A
800S
11
22
FB
4B
LM41
A80
0S
11 2 2
C15
447
0pF
C14
210
uFC
141
10uF
C14
30.
1uF
C14
40.
1uF
C14
50.
1uF
F1
SMD125-002
R52
22M
R54
120K
Y1
32.7
68K
HZ
C15
8
10pF
C15
910
pF
F2
SMD125-002
C15
247
0pF
FB
2
BLM
41A
800
S
11
22
C14
60.
1uF
C14
70.
1uF
C14
80.
1uF
C15
00.
01uF
C14
90.
01uF
C15
10.
01uF
TP
21
P12 TP
TP
22
P16 TP
TP
23
P1
7 TP
TP
24
P20 TP
TP
25
P21 TP
TP
27
G10 TP
TP
28
G11 TP
TP
29
G12 TP
TP
30
G13 TP
TP
31
G14 TP
TP
33
G16 TP
TP
35
G20 TP
TP
32
G15 TP
TP
34
G17 TP
TP
37
G22 TP J1
41x
2
1 2
TP
36
G21 TP
R55
10K
TP
26
X1 TP
J12
PS
2 S
TA
CK
TOP
BOTTOM
GN
D13
GN
D14
GN
D15
GN
D16
GN
D17
KB
DA
TA
T1
NC
T2
GN
DT
3
KB
_VC
CT
4
KB
_CLK
T5
NC
T6
MD
AT
AB
1
GN
DB
3
M_V
CC
B4
M_C
LKB
5
NC
B6
NC
B2
D2
FM
MD
914
21
3
J13
1x2
1 2
R43
4.7K
R47
10K
R50
10K
R49
10K
R48
10K
R53
22
R83
4.7k
PC
8730
7IB
U-V
UL
U10
Super I/O
WR
ITE
/ST
B11
2
TC
35
SLC
T11
4
PE
115
IOC
HR
DY
32
INIT
117
ER
R11
6
AF
D/D
ST
RB
119
BU
SY
/WA
IT11
1
AS
TR
B/S
LIN
118
AC
K11
3
PD
712
9P
D6
128
PD
512
7P
D4
126
PD
312
5P
D2
124
PD
112
3P
D0
122
D7
10D
69
D5
8D
47
D3
6D
25
D1
4D
03
IRQ
1549
IRQ
1448
IRQ
1247
IRQ
1146
IRQ
1045
IRQ
944
IRQ
843
IRQ
742
IRQ
641
IRQ
539
IRQ
438
IRQ
337
IRQ
136
A1
529
A1
428
A1
327
A1
226
A1
123
A1
022
A9
21A
820
A7
19A
618
A5
17A
416
A3
15A
214
A1
13A
012
GN
D13
9
GN
D13
0
GN
D12
0
GN
D10
1
GN
D60
GN
D40
GN
D25
GN
D11
GN
D2
CF
G0/
SO
UT
113
8
CF
G2/
RT
S2
146
CF
G3/
SO
UT
214
8
BA
DD
R1/
RT
S1
136
V5_
01
V5_
024
V5_
061
V5_
010
0
V5_
014
0
CS
068
XD
071
XD
172
CT
S1
131
CT
S2
141
DC
D1
132
DC
D2
142
DS
KC
HG
99
DS
R1
133
DS
R2
143
DT
R1/
BA
DD
R0
134
CF
G1/
DT
R2/
144
GP
IO21
158
GP
IO10
149
GP
IO11
150
GP
IO12
151
GP
IO13
152
GP
IO14
153
GP
IO15
154
GP
IO16
155
GP
IO17
156
XD
778
GP
IO25
74
XD
677
XD
CS
69
GP
IO24
73
GP
IO26
75
GP
IO27
76
ZW
S31
RD
33
WR
34
X1
50
MR
51
DR
Q0
52
DR
Q1
53
DR
Q2
54
DR
Q3
55
DA
CK
056
DA
CK
157
DA
CK
258
DA
CK
359
X1
C62
X2
C63
VB
AT
64
VC
CH
65
SW
ITC
H66
ON
CT
L67
XR
D70
IRR
X2/
IRS
L0/ID
079
IRR
X1
80
IRT
X81
KB
CLK
102
KB
DA
T10
3
MC
LK10
4
MD
AT
105
P12
106
P16
107
P17
108
P20
109
P21
110
RI1
135
AE
N30
WD
AT
A89
MT
R1
86M
TR
085
MS
EN
183
MS
EN
082
DR
AT
E0
84
DR
188
DR
087
DIR
90
ST
EP
91
HD
SE
L92
WG
AT
E93
DE
NS
EL
94
RD
AT
A95
TR
K0
96
IND
EX
97
WP
98
SIN
113
7
RI2
145
SIN
214
7
GP
IO20
157
GP
IO22
159
GP
IO23
160
V5_
012
1
BOOT BLOCK FLASH
Mode Pos
Recover 1-2
Normal 2-3
GND:
U12 10
U9 12
U10/U11 7,8
U13 16
U7 7
Mode Pos
Program IN
Normal OUT
Pull To VPP For Boot Block Unlocking
VCC:
U12 20
U9 24
U10/U11 1,14
U13 32
U7 14
{Doc
}1.
00
PO
S D
esig
n G
uide
: F
lash
Bio
s
A4
1118
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
XD
[7:0
]
SA
[19:
0]
AD
DR
16-B
IOS
_RP
XD
7X
D6
XD
5X
D4
XD
3X
D2
XD
1X
D0
SA
10
SA
14S
A13
SA
5
SA
8
SA
1
SA
12
SA
6
SA
3
SA
9
SA
4
SA
2
SA
7
SA
15
SA
11
SA
0
SA
16
BIO
S_V
PP
-BIO
SC
S5
SA
[19:
0]5,
6,8,
9,10
XD
[7:0
]5
-ME
MR
5,8,
9
-ME
MW
5,8,
9
V5_
0
+12
V
V5_
0
J16
1x1
1
J15
1x3
1
2
3
R56
8.2K
C16
30.
1uF
U8C
74A
LS0
0
9
108
R57
20K
J17
1x2
1 2C16
10.
1uF
C16
20.
1uF
U11
28F
001B
X-T
150
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
29
A15
3
A16
2
OE
24
WE
31
CE
22
RP
30
DQ
013
DQ
114
DQ
215
DQ
317
DQ
418
DQ
519
DQ
620
DQ
721
VP
P1
COM0
COM1
PARALLEL
I/O CONNECTORS
Pin 5 is the Key
FLOPPY
COM0/COM1
Clamped diodes acting as input port protection
{Doc
}1.
00
PO
S D
esig
n G
uide
: I/O
Con
nect
ors
A4
1218
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
-PP
DS
TR
B
-WR
ITE
PD
R0
PD
R5
-PP
WR
ITE
PD
R4
SP
_DC
D1
PP
SLC
T
PD
R3
PP
E
-DS
TR
B
PP
DR
6
-PP
INIT
-PP
ER
R
-AC
K
-PP
AS
TR
B
-IN
IT
PD
R1
SLC
T
-ER
R
SP
_DT
R1
SP
_CT
S0
-PP
WA
IT
PE
PD
R7
SP
_DT
R0
SP
_TX
D0
SP
_RI1
SP
_TX
D1
PP
DR
7
PP
DR
1
PP
DR
2
SP
_RX
D0
PP
DR
0
PP
DR
4
-WA
IT
PD
R6
SP
_RT
S0
SP
_RX
D1
SP
_DS
R1
PP
DR
3
PD
R2
-PP
AC
K
PP
DR
5
SP
_RI0
SP
_RT
S1
SP
_DC
D0
SP
_DS
R0
SP
_CT
S1
RX
D0
10
RI0
10
RX
D1
10
CT
S1
10
-AC
K10
-IN
IT10
PP
DR
410
PP
DR
010
SLC
T10
DT
R0
10
RT
S0
10
RT
S1
10
DC
D1
10-W
RIT
E10
PP
DR
710
PP
DR
310
-WA
IT10
DT
R1
10
CT
S0
10
DS
R0
10
-AS
TR
B10
TX
D1
10
-DS
TR
B10
PP
DR
610
DC
D0
10
PP
DR
210
PE
10
TX
D0
10
RI1
10
DS
R1
10
-ER
R10
PP
DR
510
PP
DR
110
-WG
AT
E10
MS
EN
110
-WD
AT
A10
-TR
K0
10
-DS
KC
HG
10
-DR
VS
B10
FD
DE
N10
-DR
VS
A10
DR
AT
E0
10
-MO
TE
B10
-IN
DE
X10
-MO
TE
A10
MS
EN
010
-WP
T10
-DIR
10
-SID
E1
10
-ST
EP
10
-RD
AT
A10
+12V
V5_
0
+12
V
V5_
0-1
2V
-12V
+12V
+12
V
-12V
-12V
V5_
0
V5_
0
+12V
+12V +1
2V
-12V
C19
522
0pF
C18
047
0pF
C19
722
0pF
C18
447
0pF
C18
122
0pF
C16
90.
1uF
C19
147
0pF
C19
422
0pF
RP
45
22
18
27
36
45
C16
80.
1uF
C19
622
0pF
C16
40.
1uF
C18
847
0pF
C19
822
0pF
C20
122
0pF
C17
622
0pF
R59
22
RP
434.
7K
18273645
C19
222
0pF
C17
547
0pF
C20
022
0pF
C18
547
0pF
C19
922
0pF
RP
49
22
18
27
36
45
C16
60.
1uF
C19
047
0pF
C18
947
0pF
C17
022
0pF
C17
947
0pF
C18
322
0pF
C17
847
0pF
C19
322
0pF
C16
50.
1uF
C17
122
0pF
C16
70.
1uF
RP
424.
7K
18273645
RP
47
33
18
27
36
45
C17
247
0pF
C18
222
0pF
C18
747
0pF
J19
DB
25
13251224112310229218207196185174163152141
2627
RP
46
33
18
27
36
45
C17
347
0pF
RP
444.
7K
18273645
R58
4.7K
C17
747
0pF
U12
GD
7523
2SO
P
+12V
1V
5_0
20
RA
12
RA
23
RA
34
DY
15
DY
26
RA
47
DY
38
RA
59
-12V
10R
Y5
12D
A3
13R
Y4
14D
A2
15D
A1
16R
Y3
17R
Y2
18R
Y1
19
GN
D11
C17
447
0pF
J18
SE
RIA
L S
TA
CK
1414
1818
1313
1717
1212
1616
1111
1515
1010
55
99
44
88
33
77
22
66
11
U13
GD
7523
2SO
P
+12V
1V
5_0
20
RA
12
RA
23
RA
34
DY
15
DY
26
RA
47
DY
38
RA
59
-12V
10R
Y5
12D
A3
13R
Y4
14D
A2
15D
A1
16R
Y3
17R
Y2
18R
Y1
19
GN
D11
C18
647
0pF
JP1
FLO
PP
Y H
EA
DE
R 1
7X2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
R60
1K
RP
48
1K
1 82 73 64 5
D5
D1N
916A
D7
D1N
916A
D6
D1N
916A
D4
D1N
916A
D3
D1N
916A
D8
D1N
916A
D9
D1N
916A
D10
D1N
916A
D12
D1N
916A
D11
D1N
916A
D15
D1N
916A
D17
D1N
916A
D16
D1N
916A
D14
D1N
916A
D13
D1N
916A
D18
D1N
916A
D19
D1N
916A
D20
D1N
916A
D22
D1N
916A
D21
D1N
916A
VIDEO CONTROLLER
Clamped diodes acting as input port
protection
Optional :
{Doc
}1.
00
PO
S D
esig
n G
uide
: V
ideo
Con
trol
ler
A4
1318
Frid
ay, M
ay 1
5, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
BLU
E
IRE
F
RE
D
HS
YN
C
VR
EF
VS
YN
C
GR
EE
N
VA_VDD
MA_VDD
DA
C_V
DD
AD
0A
D1
AD
2A
D3
AD
4A
D5
AD
6A
D7
AD
8
AD
10A
D11
AD
12A
D13
AD
14A
D15
AD
16A
D17
AD
18
AD
20A
D21
AD
22A
D23
AD
24A
D25
AD
26A
D27
AD
28A
D29
AD
30A
D31
AD
19
AD
9
MA0MA1MA2MA3MA4MA5MA6MA7MA8
VMD48VMD49VMD50VMD51VMD52VMD53VMD54VMD55VMD56VMD57VMD58VMD59VMD60VMD61VMD62VMD63
VMD32VMD33VMD34VMD35VMD36VMD37VMD38VMD39VMD40VMD41VMD42VMD43VMD44VMD45VMD46VMD47
VMD16VMD17VMD18VMD19VMD20VMD21VMD22VMD23VMD24VMD25VMD26VMD27VMD28VMD29VMD30VMD31
VMD0VMD1VMD2VMD3VMD4VMD5VMD6VMD7VMD8VMD9VMD10VMD11VMD12VMD13VMD14VMD15
IDS
EL
AD
13
-PIR
Q1
-PIR
Q[3
:0]
HR
EF
I
-CA
S4
-C/B
E0
-C/B
E3
AD
[31:
0]
-CA
S6
VM
D[6
3:48
]
MA
[8:0
]
-DE
VS
EL
-C/B
E1
-IR
DY
-CA
S1
VM
D[1
5:0]
-ST
OP
-RA
S0
-CA
S2
-CA
S5
VM
D[4
7:32
]
-PC
IRS
T
-CA
S7
-C/B
E2
PC
LK_V
IDE
O
-FR
AM
E
-CA
S0
-TR
DY
PA
R
-CA
S3
VM
D[3
1:16
]
32kH
Z
-PIR
Q[3
:0]
-ER
OM
-WE
-OE
14M
HZ
MA
VD
D
DA
CV
DD
MV
DD
V5_
0
+12V
V5_
0
V5_
0
V5_
0
V5_
0
J20
CO
NN
EC
TO
R D
B15
HD
1 7 2 8 3 9 4 10 5
11 12 13 14 156
R66
R
R63
150
R68
33
C21
7
1uF
R61
150
R64
180
C21
9
CA
P
R65
R
R67
220
R69
33
C20
310
uFC
202
10uF
C20
41u
FC
205
1uF
C20
61u
FC
207
0.1u
FC
208
0.1u
FC
211
0.1u
FC
210
0.1u
FC
212
0.1u
FC
213
0.01
uFC
214
0.01
uFC
215
0.01
uFC
216
0.01
uFC
209
0.1u
F
D23
D1N
916
D24
D1N
916
D25
D1N
916
D27
D1N
916
D26
D1N
916
D28
D1N
916
D30
D1N
916
D29
D1N
916
R62
150
D32
D1N
916
D31
D1N
916
C21
8
CA
P
C22
0
CA
P
CL-
GD
7555
U14
MD0/ROMD024
MD1/ROMD123
MD2/ROMD222
MD3/ROMD321
MD4/ROMD420
MD5/ROMD519
MD6/ROMD618
MD7/ROMD717
MD8/ROMA014
MD9/ROMA113
MD10/ROMA212
MD11/ROMA311
MD12/ROMA410
MD13/ROMA59
MD14/ROMA67
MD15/ROMA76
MD16/ROMA85
MD17/ROMA94
MD18/ROMA103
MD19/ROMA11249
MD20ROMA12248
MD21/ROMA13247
MD22/ROMA14246
MD23/ROMA15245
MD24/SW1PU242
MD25/SW2PU241
MD26240
MD27/SCANPU238
MD28/INTPU237
MD29/XCLKPU236
MD30/ROM32KPU235
MD31/BIOSPU234
MD32219
MD33/TMPU218
MD34/MMIOPU217
MD35216
MD36215
MD37214
MD38213
MD39212
MD40/RIOPU211
MD41210
MD42209
MD43206
MD44205
MD45204
MD46203
MD47202
MD48201
MD49199
MD50198
MD51197
MD52196
MD53195
MD54187
MD55186
MD56185
MD57184
MD58183
MD59182
MD60181
MD61180
MD62179
MD63178
VPC086 VPC187
VPC288VPC389VPC4
90 VPC591 VPC692
VPC793VPY094VPY1
95 VPY296 VPY397
VPY4100VPY5101VPY6
102 VPY7103
VA
CT
I10
8
HR
EF
I10
6
VS
111
0
VP
CLK
111
1
DD
CD
104
ER
OM
#25
3
PR
OG
012
7
PR
OG
1/T
WR
#11
9
PR
OG
212
9
AC
TI
63
CLK
32K
/SU
SP
ST
#57
FP
VC
C12
5
FP
VE
E12
3
SU
SP
I56
MA
VS
S25
2
VA
VS
S10
7
VS
S1
25
VS
S2
49
VS
S3
64
VS
S4
85
VS
S5
99
VS
S6
128
VS
S7
154
VS
S8
171
VS
S9
177
VS
S10
192
VS
S11
220
VS
S12
233
VS
S13
256
MA0 232MA1 231MA2 230MA3 229MA4 225MA5 224MA6 223MA7 222MA8 221MA9 193FP0 157FP1 158FP2 159FP3 160FP4 161FP5 162FP6 163FP7 164FP8 166FP9 167
FP10 168FP11 169FP12 170FP13 172FP14 173FP15 174FP16 175FP17 176FP18 131FP19 132FP20 133FP21 135FP22 136FP23 137FP24 138FP25 139FP26 140FP27 141FP28 143FP29 144FP30 145FP31 146FP32 147FP33 148FP34 149FP35 150
NC 1NC 2NC 62NC 65NC 66NC 118NC 126NC 130NC 190NC 191NC 254
MAVDD 250VAVDD 105CVDD1 44CVDD2 82CVDD3 239
FPVDD1 165FPVDD2 151MVDD1 8MVDD2 227MVDD3 200
AD
084
AD
183
AD
281
AD
380
AD
479
AD
578
AD
676
AD
775
AD
874
AD
973
AD
1072
AD
1171
AD
1270
AD
1369
AD
1468
AD
1567
AD
1642
AD
1741
AD
1840
AD
1939
AD
2038
AD
2137
AD
2235
AD
2334
AD
2433
AD
2532
AD
2631
AD
2730
AD
2829
AD
2928
AD
3027
AD
3126
C/B
E0#
61
C/B
E1#
60
C/B
E2#
59
C/B
E3#
58
CLK
50
DE
VS
EL#
47
FR
AM
E#
52
IDS
EL
53
INT
R#
43
IRD
Y#
51
PA
R46
RS
T#
55
ST
OP
#45
TR
DY
#48
OS
C/X
VC
LK54
MC
LK/S
W0/
XM
CLK
251
VC
LK0/
DD
CC
98
CA
S#/
WE
#22
6
OE
#25
5
RAS0 228RAS1 194
CAS0# 16CAS1# 15CAS#2 244CAS3# 243CAS4# 208CAS5# 207CAS6# 189CAS7# 188BVDD1 77BVDD2 36
DA
CV
DD
109
CR
TV
DD
117
RE
D12
2
GR
EE
N12
1
BLU
E12
0
VR
EF
115
IRE
F11
6
VS
YN
C11
4
HS
YN
C11
2
LFS
156
FP
VD
CLK
155
LLC
LK15
3
FP
DE
152
FP
DE
CT
L12
4
DA
CV
DD
134
DA
CV
SS
214
2
DA
CV
SS
111
3
VIDEO DRAM
VGA BIOS ROM
{Doc
}1.
00
PO
S D
esig
n G
uide
: V
ideo
DR
AM
and
VG
A B
IOS
RO
M
A4
1418
Frid
ay, M
ay 1
5, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
VM
D8
VM
D9
VM
D10
VM
D11
VM
D12
VM
D13
VM
D14
VM
D15
VM
D16
VM
D17
VM
D18
VM
D19
VM
D20
VM
D21
VM
D22
VM
D23
MA
0M
A1
MA
2M
A3
MA
4M
A5
MA
6M
A7
MA
8
VM
D0
VM
D1
VM
D2
VM
D3
VM
D4
VM
D5
VM
D6
VM
D7
VM
D8
VM
D9
VM
D10
VM
D11
VM
D12
VM
D13
VM
D14
VM
D15
MA
0M
A1
MA
2M
A3
MA
4M
A5
MA
6M
A7
MA
8
VM
D16
VM
D17
VM
D18
VM
D19
VM
D20
VM
D21
VM
D22
VM
D24
VM
D25
VM
D26
VM
D27
VM
D28
VM
D29
VM
D30
VM
D31
VM
D23
MA
0M
A1
MA
2M
A3
MA
4M
A5
MA
6M
A7
MA
8
VM
D32
VM
D33
VM
D34
VM
D35
VM
D36
VM
D37
VM
D38
VM
D39
VM
D40
VM
D41
VM
D42
VM
D43
VM
D44
VM
D45
VM
D46
VM
D47
MA
0M
A1
MA
2M
A3
MA
4M
A5
MA
6M
A7
MA
8
VM
D48
VM
D49
VM
D50
VM
D51
VM
D52
VM
D53
VM
D54
VM
D55
VM
D56
VM
D57
VM
D58
VM
D59
VM
D60
VM
D61
VM
D62
VM
D63
VM
D1
VM
D2
VM
D3
VM
D4
VM
D5
VM
D6
VM
D7
VM
D0
VM
D[3
1:16
]V
MD
[47:
32]
VM
D[6
3:48
]
-RA
S0
-CA
S7
-CA
S6
-WE
-OE
-RA
S0
-CA
S5
-CA
S4
-WE
-OE
-CA
S3
-CA
S2
-WE
-OE
-RA
S0
-RA
S0
-CA
S1
-WE
-CA
S0
-OE
MA
[8:0
]M
A[8
:0]
MA
[8:0
]M
A[8
:0]
VM
D[1
5:0]
VM
D[3
1:16
]
-ER
OM
VM
D[1
5:0]
VM
D[1
5:0]
V5_
0
V5_
0V
5_0
V5_
0V
5_0
V5_
0
U15
HY
B51
4171
BJ-
60
A0
16
A1
17
A2
18
A3
19
A4
22
A5
23
A6
24
A7
25
A8
26
I/O 0
2
I/O 1
3
I/O 2
4
I/O 3
5
I/O 4
7
I/O 5
8
I/O 6
9
I/O 7
10
I/O 8
31
I/O 9
32
I/O 1
033
I/O 1
134
I/O 1
236
I/O 1
337
I/O 1
438
I/O 1
539
NC
11
NC
12
NC
15
NC
30
VC
C1
VC
C6
VC
C20
VS
S21
VS
S35
VS
S40
RA
S#
14
UC
AS
#28
LCA
S#
29
WE
#13
OE
#27
U16
HY
B51
4171
BJ-
60
A0
16
A1
17
A2
18
A3
19
A4
22
A5
23
A6
24
A7
25
A8
26
I/O 0
2
I/O 1
3
I/O 2
4
I/O 3
5
I/O 4
7
I/O 5
8
I/O 6
9
I/O 7
10
I/O 8
31
I/O 9
32
I/O 1
033
I/O 1
134
I/O 1
236
I/O 1
337
I/O 1
438
I/O 1
539
NC
11
NC
12
NC
15
NC
30
VC
C1
VC
C6
VC
C20
VS
S21
VS
S35
VS
S40
RA
S#
14
UC
AS
#28
LCA
S#
29
WE
#13
OE
#27
U18
HY
B51
4171
BJ-
60
A0
16
A1
17
A2
18
A3
19
A4
22
A5
23
A6
24
A7
25
A8
26
I/O 0
2
I/O 1
3
I/O 2
4
I/O 3
5
I/O 4
7
I/O 5
8
I/O 6
9
I/O 7
10
I/O 8
31
I/O 9
32
I/O 1
033
I/O 1
134
I/O 1
236
I/O 1
337
I/O 1
438
I/O 1
539
NC
11
NC
12
NC
15
NC
30
VC
C1
VC
C6
VC
C20
VS
S21
VS
S35
VS
S40
RA
S#
14
UC
AS
#28
LCA
S#
29
WE
#13
OE
#27
U17
HY
B51
4171
BJ-
60
A0
16
A1
17
A2
18
A3
19
A4
22
A5
23
A6
24
A7
25
A8
26
I/O 0
2
I/O 1
3
I/O 2
4
I/O 3
5
I/O 4
7
I/O 5
8
I/O 6
9
I/O 7
10
I/O 8
31
I/O 9
32
I/O 1
033
I/O 1
134
I/O 1
236
I/O 1
337
I/O 1
438
I/O 1
539
NC
11
NC
12
NC
15
NC
30
VC
C1
VC
C6
VC
C20
VS
S21
VS
S35
VS
S40
RA
S#
14
UC
AS
#28
LCA
S#
29
WE
#13
OE
#27
U19
27C
512
A0
10
A1
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
3
A8
25
A9
24
A10
21
A11
23
A12
2
A13
26
A14
27
A15
1
D0
11
D1
12
D2
13
D3
15
D4
16
D5
17
D6
18
D7
19
Vcc
28
OE
#/V
PP
22
CE
#20
Vss
14
C22
210
uFC
221
10uF
C22
31u
FC
224
1uF
C22
50.
1uF
C22
70.
1uF
C22
80.
1uF
C23
00.
01uF
C22
90.
1uF
C23
10.
01uF
C23
30.
01uF
C23
20.
01uF
C22
60.
1uF
{Doc
}1.
00
PO
S D
esig
n G
uide
: P
CM
CIA
Con
nect
or
A4
1518
Frid
ay, M
ay 1
5, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
VP
P_O
UT
VP
P_O
UT
PC
M_D
7
PC
M_D
0
AA
9
-A IO
RD
PC
M_D
0
AA21
AA14
A W
P/-
IOIS
16
SD
7
LA22
AA
16
A R
DY
/-IR
EQ
-A IO
WR
PC
M_D
11
PC
M_D
9
AA25
SD
6S
D5
PC
M_D
2
PC
M_D
4P
CM
_D5
PC
M_D
12 A G
PS
TB
PC
M_D
12
AA12
AA6
A B
VD
2/-S
PK
R/-
LED
SD
4S
D3
AA
7
AA
22A
A23
AA
24
PC
M_D
14
PC
M_D
10
PC
M_D
1
AA22
AA9
A G
PS
TB
A B
VD
1/-S
CS
CH
G/-
RI
A V
PP
VC
C-A
CD
2B
GP
ST
B
PC
M_D
3
AA18
AA10
A V
PP
PG
M
SD
15
SD
10
PWRGOOD
AA
3
AA
0
PC
M_D
15
-A O
E
SD
14S
D13
SD
12S
D11
SD
9S
D8
AA
1 -AC
D1
A R
DY
/-IR
EQ
PC
M_D
[15:
0]
A B
VD
2/-S
PK
R/-
LED
PC
M_D
8
AA13
AA8
AA4
-A IN
PA
CK
-A C
E2
A B
VD
1/-S
TS
CH
G/-
RI
A S
OC
KE
T V
CC
-AC
D2
SA
3
AA
15
-A W
AIT
-A C
E1
AA19
-A IO
RD
A R
ES
ET
SD
2S
D1
SA
10
SA
2S
A1
AA
2
AA
6
AA
20A
A21 -A
WE
A R
ES
ET
AA15
AA5
LA17
SA
14S
A13
SA
12
SA
9S
A8
PC
M_D
8
AA
8
PC
M_D
10
PC
M_D
5
AA11
AA2
SD
0
SA
11
SA
7
AA
[25:
0]
AA
5A
A4
AA
11
PC
M_D
14
PC
M_D
11
AA16
AA7
PC
M_D
15
AA
10
AA20
AA
18A
A19
-A IN
PA
CK
A V
PP
PG
M
PC
M_D
2
AA23
-A V
CC
3
SA
4
PC
M_D
3
PC
M_D
13
PC
M_D
6
A S
OC
KE
T V
CC
-A V
CC
3
PC
M_D
13
PC
M_D
4
AA17
AA3
-A W
AIT
-A V
CC
5
LA21
LA20
LA19
SA
16S
A15
PC
M_D
9
AA
25
AA
17
A W
P/-
IOIS
16
-A C
E2
-A O
E
AA24
AA1AA0
-A IO
WR
A V
PP
VC
C
-AC
D1
LA18
SA
6
SA
0
AA
13
B G
TS
TB
PC
M_D
1
AA
12
AA
14
-A R
EG
-A V
CC
5V
5_0
PC
M_D
7P
CM
_D6
-A R
EG
-A W
E
LA23
SA
5
-A C
E1
SA
[19:
0]
SD
[15:
0]
LA[2
3:17
]
RS
TD
RV
-ME
MW
IRQ
12
IRQ
7
IRQ
4
-IO
CS
16
-0W
S
BA
LE
14M
HZ
-IO
R
-ME
MC
S16
IRQ
9
IRQ
14
-ME
MR
IOC
HR
DY
IRQ
5
-SB
HE
IRQ
3
-IO
W
-RE
FR
ES
HA
EN
+12V
V3_
3
V5_
0
V5_
0
C28
9
0.01
uF
C28
3
0.1u
F
C28
1
CA
P
U33
LTC
1472
VP
PE
N0
7
VP
PE
N1
8
VC
CE
N0
4
VC
CE
N1
3
SH
DN
6
VP
PIN
5
5VIN
2
3VIN
15
3VIN
14
VD
D9
VC
C_O
UT
1
VC
C_O
UT
16
VC
CIN
12
VP
P_O
UT
11
GN
D10
GN
D13
C29
0
0.01
uF
J26
PC
MC
IA C
onne
ctor
A0
29
A1
28
A2
27
A3
26
A4
25
A5
24
A6
23
A7
22
A8
12
A9
11
A10
8
A11
10
A12
21
A13
13
A14
14
A15
20
A16
19
A17
46
A18
47
A19
48
A20
49
A21
50
A22
53
A23
54
A24
55
A25
56
D0
30
D1
31
D2
32
D3
2
D4
3
D5
4
D6
5
D7
6
D8
64
D9
65
D10
66
D11
37
D12
38
D13
39
D14
40
D15
41
OE
*9
WE
*/P
GM
*15
IOR
D*
44
IOW
R*
45
WP
/IOC
S16
33
INP
AC
K*
60
RD
Y/B
SY
*16
WA
IT*
59
CD
1*36
CD
2*67
CE
1*7
CE
2*42
RE
SE
T58
BV
D1/
ST
SC
HD
*63
BV
D2/
SP
KR
62
RE
G*
61
VS
1*43
VS
2*57
VC
C17
VC
C51
VP
P2
52
VP
P1
18
GN
D68
GN
D1
GN
D34
GN
D35
U31
A
7404
12
C28
7
1uF
C29
1
0.01
uF
C28
8
0.01
uF
C28
0
0.1u
F
C28
2
0.1u
F
C28
4
1uF
U32
CL-
PD
6720
PW
RG
OO
D20
1
CLK
163
ME
MR
*14
5
ME
MW
*14
4
IOR
*18
5
IOW
*18
6
SA
016
1
SA
116
2
SA
216
4
SA
316
5
SA
416
7
SA
516
8
SA
616
9
SA
717
1
SA
817
3
SA
917
5
SA
1017
6
SA
1117
8
SA
1217
9
SA
1318
1
SA
1418
2
SA
1518
3
SA
1618
4
LA17
146
LA18
147
LA19
149
LA20
151
LA21
153
LA22
155
LA23
157
SD
018
9
SD
119
0
SD
219
3
SD
319
4
SD
419
6
SD
519
7
SD
619
9
SD
720
0
SD
814
3
SD
914
2
SD
1014
1
SD
1113
9
SD
1213
7
SD
1313
6
SD
1413
5
SD
1513
4
SP
KR
OU
T*/
C_S
EL
202
INT
R*
203
IRQ
317
0
IRQ
417
2
IRQ
517
4
IRQ
717
7
IRQ
919
8
IRQ
1015
6
IRQ
1115
4
IRQ
12/L
ED
_OU
T*
152
IRQ
1414
8
IRQ
15/R
I_O
UT
*15
0
A C
D1*
10
A C
D2*
69
A G
PS
TB
6
A V
CC
3*
4
A V
CC
5*
5
A R
ES
ET
51
A V
PP
PG
M1
A V
PP
VC
C2
A S
OC
KE
T V
CC
24
A S
OC
KE
T V
CC
52
A B
VD
1/S
TS
CH
G*/
RI*
61
A B
VD
2/S
PK
R*/
LED
*59
A O
E*
23
A W
E*
37
A IO
RD
*26
A IO
WR
*29
A C
E1*
19
A C
E2*
22
A W
P/IO
IS16
*68
A IN
PA
CK
*56
A W
AIT
*54
A R
EG
*8
A R
DY
/IRE
Q*
39
AA060 AA158 AA257 AA355 AA453 AA550 AA649 AA747 AA830 AA928 AA1021 AA1125 AA1245 AA1333 AA1435 AA1543 AA1641 AA1732 AA1834 AA1936 AA2038 AA2140 AA2242 AA2344 AA2446 AA2548
AD
062
AD
164
AD
266
AD
39
AD
411
AD
513
AD
615
AD
717
AD
863
AD
965
AD
1067
AD
1112
AD
1214
AD
1316
AD
1418
AD
1520
+5V
208
ISA
_VC
C19
5
ISA
_VC
C13
8
CO
RE
_VD
D13
3
CO
RE
_VD
D27
BD
1584
BD
1482
BD
1380
BD
1277
BD
1175
BD
1013
0
BD
912
8
BD
812
6
BD
781
BD
678
BD
576
BD
474
BD
372
BD
212
9
BD
112
7
BD
012
5
B IO
WR
*92
B IO
RD
*90
B W
E*
99B
OE
*87
B B
VD
2/ S
PK
R*/
LED
*12
2B
BV
D1/
ST
SC
HG
*/R
I*12
4B
SO
CK
ET
VC
C11
7B
SO
CK
ET
VC
C88
B V
PP
VC
C20
5B
VP
P P
GM
204
B R
ES
ET
114
B V
CC
5*
207
B V
CC
3*
206
B G
PS
TB
7B
CD
2*13
2B
CD
1*73
GN
D31
GN
D70
GN
D79
GN
D14
0
GN
D11
1
GN
D19
2
ALE
166
AE
N18
7
RE
FR
ES
H*
180
SB
HE
*15
9
IOC
S16
*15
8
ME
MC
S16
*16
0
IOC
HR
DY
188
ZW
S*
191
BA0 123BA1 121BA2 120BA3 118BA4 115BA5 113BA6 112BA7 109BA8 93BA9 91
BA10 85BA11 89BA12 107BA13 95BA14 97BA15 105BA16 103BA17 94BA18 96BA19 98BA20 100BA21 102BA22 104BA23 106BA24 108BA25 110
VP
P V
ALI
D*
3
B C
E1*
83
B C
E2*
86
B W
P/IO
IS16
*13
1
B IN
PA
CK
*11
9
B W
AIT
*11
6
B R
EG
*71
B R
DY
/IRE
Q*
101
APPLICATION FLASH
To Parallel Port
{Doc
}1.
00
PO
S D
ES
IGN
GU
IDE
: App
licat
ion
Flas
h
A4
1618
Thu
rsda
y, M
ay 1
4, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SD
O
-FLS
H_C
ELA
21LA
20
LA23
LA22 P
OR
TC
LK
PO
RT
MO
DE
SD
I
LA19
RP
#
SU
PE
RIO
_GP
IO27
SU
PE
RIO
_GP
IO26
SU
PE
RIO
_GP
IO25
SU
PE
RIO
_GP
IO24
IP_G
ND
-FLS
H_W
P
-ME
MC
S16
#S
A2
SA
17
SA
10
SA
16
SA
12
SA
9
SA
7
SA
3
SA
15
SA
5
SA
13
SA
4
SA
8
SA
6
SA
1
SA
18
SA
0
SA
11
SA
14
V5_
0
SD
7
SD
14
SD
12
SD
5
SD
10
SD
0
SD
3
SD
8
SD
1
SD
6
SD
15
SD
13
SD
2
SD
4
SD
9
SD
11
-ME
MW-S
BH
E
-ME
MR
SA
[19:
0]
SD
[15:
0]
LA[2
3:17
]
-ME
MC
S16
RS
TD
RV
IOC
HR
DYSA
0
SY
SC
LK
AP
PF
LSH
_SA
20A
PP
FLS
H_S
A21
AP
PF
LSH
_WP
#
AP
PF
LSH
_SA
19
BA
LE
V5_
0
V5_
0
V5_
0
C23
41u
FC
235
0.1u
FC
236
0.1u
FC
237
0.01
uF
U36
Soc
ket2
11 22 33 44 55 66 77 88
C23
8
CA
P
R80
4.7K
U22 is
pGA
L22V
10
IP3
IP4
IP5
IP6
IP7
IP9
IP10
IP11
IP12
IP13
IP16
OP
17
OP
18
OP
19
OP
20
OP
21
OP
23
OP
24
OP
25
OP
26
OP
27
MO
DE
8
SC
LK1
I/CLK
2
GN
D14
VC
C28
SD
O22
SD
I15
U9C
74A
CT
05
56R
84
4.7k
J27
JUM
P3
1
2
3
U23
28F
320S
5
A0
37
A1
51
A2
50
A3
49
A4
48
A5
47
A6
46
A7
45
A8
43
A9
52
A10
53
A11
54
A12
2
A13
3
A14
4
A15
5
A16
13
A17
12
A18
11
A19
10
A20
9
A21
8
CE
0#1
CE
1#7
RP
#55
OE
#22
WE
#21
ST
S20
D0
38
D1
40
D2
33
D3
31
D4
27
D5
25
D6
16
D7
18
D8
39
D9
41
D10
32
D11
30
D12
26
D13
24
D14
17
D15
19
NC
6
NC
35N
C34
VP
P56
VC
C14
VC
C28
VC
C42
GN
D15
GN
D29
GN
D44
WP
#23
BY
TE
#36
ADDITIONAL COMMUNICATION PORTS
C3CS
C4CS
{Doc
}1.
00
PO
S D
esig
n G
uide
: S
eria
l com
mun
icat
ion
s
A4
1718
Frid
ay, M
ay 1
5, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SD
0S
D1
SD
2S
D3
SD
4S
D5
SD
6S
D7
SA
0S
A1
SA
2
TX2
RX
2D
TR
2R
TS
2C
TS
2D
SR
2
RI3
CD
3D
SR
3C
TS
3R
TS
3D
TR
3R
X3
TX3
RI2
AR
X2
AR
TS
2A
TX
2A
CT
S2
AD
TR
2
AR
I3
AR
TS
3A
TX
3A
CT
S3
AD
TR
3
AC
D3
CD
2
AR
X3
AD
SR
2
AD
SR
3
AC
D2
AR
I2
LGC
1
LGC
2
LGC
3
LGC
5
LGC
4
LGC
6
PU
LL-U
P
LGC
7
SA
[19:
0]
IRQ
3
-IO
W-I
OR
SY
SC
LK
IRQ
4
SD
[15:
0]
SA
8
SA
9
SA
7S
A6
SA
5
SA
4SA
3
RS
TD
RV
+12V
-12V +1
2V
-12V
V5_
0
V5_
0
V5_
0
+12V
-12V
-12V
+12V
C24
3
.1uF
P2
DB
9
594837261
1011
U29
GD
7523
2SO
P
+12V
1V
5_0
20
RA
12
RA
23
RA
34
DY
15
DY
26
RA
47
DY
38
RA
59
-12V
10R
Y5
12D
A3
13R
Y4
14D
A2
15D
A1
16R
Y3
17R
Y2
18R
Y1
19
GN
D11
D52
1N91
4
D47
1N91
4
D46
1N91
4
D36
1N91
4
D51
1N91
4
D50
1N91
4
D35
1N91
4
D45
1N91
4
D34
1N91
4
D44
1N91
4
D49
1N91
4
D33
1N91
4
D43
1N91
4
D48
1N91
4
C23
91u
FC
240
0.1u
FC
241
0.1u
FC
242
0.01
uF
U28
ST
16C
452
D0
14
D1
15
D2
16
D3
17
D4
18
D5
19
D6
20
D7
21
A0
35
A1
34
A2
33
IOW
*36
IOR
*37
CS
A*
32
CS
B*
3
CS
P*
38
BID
EN
1
INT
A45
INT
B60
INT
P*
59
CLK
4
RE
SE
T*
39
INT
SE
L*43
RD
OU
T44
TX
A26
RX
A41
DT
RA
*25
RT
SA
*24
CT
SA
*28
DS
RA
*31
CD
A*
29
RIA
*30
TX
B10
RX
B62
DT
RB
*11
RT
SB
*12
CT
SB
*13
DS
RB
*5
CD
B*
8
RIB
*6
PD
053
PD
152
PD
251
PD
350
PD
449
PD
548
PD
647
PD
746
SLC
TIN
*58
AU
TO
FD
XT
*56
INIT
57
ST
RO
BE
*55
ER
RO
R*
63
SLC
T65
PE
67
AC
K*
68B
US
Y66
GND 2GND 7GND 27GND 54VCC23 VCC40 VCC64
NC
9
NC
61
U27
GD
7523
2SO
P
+12V
1V
5_0
20
RA
12
RA
23
RA
34
DY
15
DY
26
RA
47
DY
38
RA
59
-12V
10R
Y5
12D
A3
13R
Y4
14D
A2
15D
A1
16R
Y3
17R
Y2
18R
Y1
19
GN
D11
P1
DB
9
594837261
1011
D37
1N91
4
D42
1N91
4
R70
4.7k
U31
B
7404
34
U45
A
7400
1 23
U45
B
7400
4 56
U45
C
7400
9 108
U45
D
7400
12 1311
U46
A
7421
1 2 4 5
6
U46
B
7421
9 10 12 13
8
D41
1N91
4
D38
1N91
4
D39
1N91
4
D40
1N91
4
Power Indicators
SPEAKER HEADER
FAN HEADER
Note: Add screen marking for V5_0 LED, V3_3 LED, V2_9 LED
PLACE CLOSE TO PIN 109 OF CL-GD7555
Supply for
display memory
Supply for
memory and
video clock
PLACE CLOSE TO PIN 250 OF CL-GD7555
Place at ATX Connector
Place single point
connection at ATX
Connector
Note Cap Direction
PLACE CLOSE TO PIN 8/227/200 OF CL-GD7555
Place at ATX Connector
Place at ATX Connector
Note Cap Direction
Vr=2.7v
PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH
Vr=2.4v
PS_OK comes up before V2_9 off Mohave so AND
these to generate system power ok to PIIX3
(PWOK)
SCHMITT
1-2 Mohave 2.9V
PWOK = V2_9OK AND PS_OK
Place at ATX Connector
Place at ATX Connector
Open Collector
Optional
Note :
.
For EMDMOD133, use D10 which is 2.7V.
For EMBMOD166, use D11 which is 2.3V.
Supply for
RAMDAC
{Doc
}1.
00
PO
S D
esig
n G
uide
: P
ower
A4
1818
Wed
nesd
ay, M
ay 1
3, 1
998
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
VIN
_A
MV
DD
VIN
_BV
IN_C
V-
V2_
9OK
PW
_OK
PS
_OK
PS
_ON
SP
KR
5
MV
DD
13
V2_
93
MA
VD
D13
DB
RE
SE
T3
DA
CV
DD
PW
OK
5
-5V
V5_
0
V5_
0
V5_
0
V5_
0
+12V
V5_
0V
5_0
V5_
0V
3_3
V3_
3-1
2VV
5_0
V2_
9
C25
610
uF
C25
047
0pF
C25
30.
1uF
JP2
1x4
1 2 3 4
C25
5
100u
F
R77
10K
J25
1x3
1 2 3
C27
310
00pF
C26
51u
F
C27
110
uF
C26
20.
1uF
C25
922
uF
C27
00.
1uF
C26
70.
01uF
C26
310
uF
C26
90.
1uF
C26
00.
1uF
C27
20.
1uF
C26
60.
1uF
FB
8
CB
70
11
22
C26
10.
1uF
C26
80.
01uF
C25
147
0pF
R75
110
C25
247
0pF
C25
4
100u
F
D53
LGS
260-
DO
IN2
NC1OUT 3
D54
LGS
260-
DO
IN2
NC1OUT 3
D55
LGS
260-
DO
IN2
NC1OUT 3
C25
74.
7nF
C24
9
100u
F
C24
70.
1uF
C24
810
0uF
C24
5
100u
F
C24
40.
1uF
FB
7
CB
70
11
22
D56
BZ
X84
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7J24
1x3
1
2
3
D57
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X84
C2V
4
R79
1K
S1
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SE
T S
WIT
CH
C25
8
1uF
C26
410
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U30
A
TLC
393C
+ -
3 21
8 4
C27
810
0uF
C27
6
100u
F
C27
70.
1uF
R74
130
C27
510
0uF
C27
40.
1uF
C27
9
100u
F
R76
4.7K
J22
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X P
OW
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10
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12
PS
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14
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18
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V5_
020
GN
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D7
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D13
GN
D15
GN
D16
GN
D17
V5_
04
V5_
06
V3_
31
V3_
32
V3_
311
J23
1x2
1 2
C24
6
100u
F
R73
215
R78 10
K
U8D
74A
LS00
12 1311
U4B
74H
CT
14
34
U9B
74A
CT
05
34