North-Holland Microprocessing and M icroprogramming 27 (1989) 571-578 571

P M L S - A PARALLEL MULTI-LEVEL VLSI SIMULATOR *

E. Aposporidis, F. Lohnert, P. Mehring AEG Aktiengesellschaft Berlin Research Institute Holl&nderstr. 31-34, D-1000 Berlin 51

F. Hoppe, H . - U. Post Technische Universit&t Berlin Institut fi.ir Technische Informatik Franklinstr. 28-29, D-1000 Berlin 12

A B S T R A C T

Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of th~ simulation through exploitation of parallelism.

This paper reports of a new Parallel Multi-Level VLSI Simulator(PMLS) for a general purpose parallel machine which combines mufti-leveling and exploitation of parallelism at the circuit level.

The VLSI simulator is implemented in the object-oriented language POOL and runs on the parallel DOOM machine.

The paper surveys briefly the principles of digital-circuit simulation, the possibilities of exploiting parallelism, the DOOM machine, its programming language POOL, and describes the design and implementation of the simulator. Preliminary performance figures are also given.

1. INTRODUCTION

Powerful simulators are a key element in today's and future dig- ital circuit design environments. However, simulation becomes a bottleneck in circuit design with increasing design complexity.

There are mainly two ways to get out of this situation:

- Red uction of the sire ulation load through multi-level sim ula- tion, i.e. using different modelling levels within a circuit and not only one basic level throughout, e.g. gate level or electri- cal level (s. Fig. 1).

- Acceleration of the simulation through exploitation of paral- lelism on the different modelling and simulator levels.

In order to hold simulation times within acceptable limits, spe- cial purpose machines ("logic simulation machines") have been developed in the past. Almost all machines are hardware accel- erators; they operate at the gate level, run a fixed algorithm and exploit parallelism through pipelining.

Our paper reports of a new Para//e/Mu/ti-Leve/VLSl Simu/a- tor(PMLS) [1,2] for general purpose parallel machines which combines multi-leveling and exploitation of parallelism at the circuit level. The initial implementation of the simulator is in the object-oriented language POOL for the parallel DOOM ma- chine [3,4]. A short description of DOOM and POOL and prelim- inary performance figures are also given.

2. LEVELS OF ABSTRACTION IN THE DESIGN PRO- CESS

VLSI circuits are very complex systems and cannot be de- signed in one single step even with modern computer aided de- sign techniques. There are four major design steps [1,5]: Sys- tem design, logic design, electrical (or circuit) design and physi- cal (or layout) design.

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* Research partially funded by ESPRIT Project 415: Parallel Architectures and Languages for Advanced Information Processing - A VLSI-Directed Approach.

572 E. Aposporidis et a L / P M L S - a Parallel Multi-Level VLSl Simulator

The design process starts with a global specification at the high- est possible level of abstraction covering all system require- ments. Then the detailed structure of the system is derived by breaking down this abstraction level step by step. in this pro- cess the designer tries to break down the problem into a num- ber of interconnected subproblems. This process is repeated until solutions to all the subproblems are known or until wel l- known procedures are available which can be applied to solve these subproblems (top-down design).

PMLS focuses on the logic design levels. The underlying as- sumption is that the electrical and physical design cycle will be largely automated in the near future.

Within logic design, a VLSI circuit can be described at various abstraction levels (s. Fig. 1 ):

- at the register-transfer level (registers, ALUs, ROMs, RAMs),

- at the functional level (flipflops, counters, etc.),

- at the gate level (NAND gates, OR gates, etc.),

- at the switch level (MOS transistors modelled as switches).

An advanced VLSI simulator has to cover all these abstraction levels, i.e. it has to have the capability to simulate circuit parts of a given circuit on different abstraction levels [6]. As an even more advanced feature, a VLSI simulator should allow to select dynamically the abstraction level on which a circuit part is to be simulated (zooming [7]).

3. PRINCIPLES OF DIGITAL CIRCUIT SIMULATION

Simulation methods for digital circuits are characterised by the circuit model used and by the procedures for model handling. Models may represent different levels of abstraction corre- sponding to the levels in Section 2. There is a large variety of models. Each model is characterised by its modelling of sig- nals and its modelling of elements.

There are two different types of simulation in logic design corre- sponding to different phases of the design and production pro- cess:

- Iogicsimulationfor checking the design for logic and timing errors

- fault simulation as an aid in testing the circuit for possible hardware defects.

In the following we focus on the logic simulation, as that is the basic simulation type for digital circuits.

3.1 S imulat ion Mode ls

Modelling of Signals

At the logic design levels the analog signals are replaced by discrete approximations [8,9]. As a first approximation the sta- tionary (binary) values 0 and 1 are used. Modelling the high im- pedance state of an element output (i.e. tristate output) and the unknown state of a signal (because of initial or invalid condi- tions) requires the additional values Z and X, respectively. An improved approximation also considers the strength of a signal

specifying the type of connection between the voltage source und the signal (especially required to model MOS transistors as bidirectional switches at the "switch level").

Modelling of Elements

Modelling of circuit elements splits down into modelling of their logic behaviour and of their timing behaviour:

- The logic behaviour is modelled by an evaluation algorithm corresponding to the element's type or simply by a truth table. The evaluation algorithm computes a new output va- lue and a new state value (if the circuit element has a storage capability) from the current input values (and the current state value).

- The timing behaviour is modelled by a propagation delay, i.e. a delayed output reaction to a change at the input.

3.2 Bas ic Simulat ion Execut ion Control

There are several basic methods for execution control of a si- mulation, even in the sequential case [8]. The most important execution control method is event-driven or discrete event si- mulation with selective trace.

With this method "element evaluations" are triggered by "events", i.e. changes of signal values. Basically, an event is de- fined by a signal identification, a new signal value, and a time stamp describing when the signal value change occurs. An "event list" maintaining all future events is used to keep track of the events.

The simulator fetches an event with the smallest time stamp from the event list (event-driven), and determines those ele- ments which are activated bythis event (selective trace). These elements are then evaluated and resulting new events with a time stamp according to the propagation delay are entered into the event list.

The advantage of applying discrete event simulation for Iogicsi- mulation is that only those circuit elements are evaluated, for which signal changes actually do occur.

3.3 Paral lel S imulat ion

This section surveys the possibilities for the parallel execution of digital circuit simulation. The basic principle behind the orga- nisation of parallel processing in the sire ulation of digital circuits is partitioning with regard to structure and time. There are three basic "grain levels" for the organisation of parallel processing (s. Table 1 ).

At the casegrain level, i.e. atthe level of sire ulation jobs, there is a very important possibility for parallel processing for all types of variant simulation:

- the structure variants, such as with fault simulation and the simulation of design variants,

- the stimulus variants, i.e. different patterns of input signals.

The basis is that all the variants can be executed as single- case simulations independently from each other, i.e. in parallel.

E. Aposporidis et aL / PMLS - a Parallel Multi-Level VLSl Simulator 573

Grain level

Case

Circuit

Algor i thm

Grain size

Coarse

Medium

Fine

Mechanisms

Parti t ioning of: fault set, stimuli set, variant set

Circuit parti t ioning, asynchro- nous processing

Algor i thm partit ioning, task pipel ining

Table 1: Basic "grain levels" for paral lel processing m digital circuit s imulat ion

Parallel variant simulation leads to simulation processes with coarse grain size; thus no special requirements on the parallel machine are imposed. It is even simply possible to map parallel variant simulation on a set of general purpose computers con- nected in a local area network (e.go workstations).

At the circuit grain level i.e. the level of individual circuit simula- tion, the basis for parallel processing is partitioning of the circuit into subcircuits. Modern design techniques (top down design) lend themselves automatically to a hierarchical partitioning of circuits into functional units. Functional units are collected into subcircuits to be simulated by subsimulators (s. Fig. 2).

Circuit

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Sub- simulators

l 1

Event Messages

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Circuit partitioning ascribing subcircuits to subsimulators al- lows the exploitation of asynchronous parallel processing of all subcircuits. Corresponding to the interconnection of the subcir- cults the individual subsimulators have to communicate with each other by exchanging event messages, each one time- stamped with the scheduled simulation time of this event.

This leads to the concept of distributed discrete event simula- tion [10] requiring a way to synchronise the subsimulators. The

two basic methods for synchronisation are:

- the conservative strategy using synchronisation by wait, i.e. each subsimulator waits until it is guaranteed that no event message carrying a time stamp less than the local simula- tion time of a subsimulator arrives,

- the optimistic strategy using synchronisation by rollback (time warp approach) [11,12], i.e. a subsimulator always runs forward and rolls back on receiving an event message carrying a time stamp less than the local simulation time.

Circuit partitioning leads to simulation processes with medium grain size; as a consequence, this approach is efficient for today's general purpose parallel machines such as DOOM, Su- pernode, INTEL iPSC/2 or SEQUENT.

The algorithm grain level i.e. the level of individual simulators or subsimulators, offers very distinct options for parallel pro- cessing. It is the major level for exploitation of parallelism in today's specialised "simulation machines". In case of the event-driven algorithm, a common approach is to map the se- quence of operations (i.e. fetching an event, updating the sig- nals, evaluating an element, inserting new events into the event list) onto a circular pipeline with a central event list [13]. This ap- proach leads to tasks with very fine grain size; thus specialised hardware is required.

4. TARGET MACHINE AND IMPLEMENTATION LANGUAGE

PMLS is designed to run on avariety of general purpose parallel machines. The initial implementation of PMLS is on DOOM (Decentralised Object Oriented Machine) using POOL (Paral- lel Object-Oriented Language) [3,4]. DOOM and POOL are de- veloped by Philips within ESPRIT project 415.

The DOOM architecture can be characterised as a network of computing nodes. Each of these nodes consists of a data pro- cessor, a local memory, and a communication processor. There is no shared memory. Communication between nodes is per- formed by means of packet switching. The communication pro- cessor is designed to support various network topologies (e.g. hypercubes, meshes) using an adaptive routing scheme. Each node has a copy of the operating system kernel. This kernel performs local resource management (i.e. scheduling, memory management) and cooperates with other kernels for global tasks (i.e. distributed garbage collection, load balancing for ob- ject allocation).

The DOOM prototype built within the frame of ESPRIT project 415 consists of 100 nodes each with a 68020 CPU, 12 Mbyte memory, and a bread-board implementation of the communi- cation processor. It is planned to have VLSI implementations of the communication processor as well as of the data processor in 1990/91. Currently, a 12 node prototype is used for testing and evaluation.

The POOL programming language, especially designed for reliable programming of large scale applications for highly par- allel machines, uses the well-known advantages of the con- cepts of object-oriented programming. A POOL program con- sistsof a large number of dynamicobjects communicating sole- ly by message passing. Objects are instances of classes. In

574 E. Aposporidis et aL / P M L S - a Parallel Multi-Level VLSl Simulator

contrast to most object-oriented programming languages, ob- jects in POOL are active, i.e. they are processes. POOL pro- vides synchronous communication (similar to the ADA rendez- vous) and asynchronous communication (no-wait-send) be- tween objects. POOL runs on DOOM and also on standard UNIX machines (e.g. SUN, VAX) using the POOL interpreter and the DOOM simulator.

5. ENVIRONMENT OF THE SIMULATOR

We are aiming at the development of the next generation VLSI simulation tools, based on the utilisation of parallel processing on general-purpose parallel machines. Three parallel simula- tor kernels are under development:

- the Parallel Multi-Level Simulator (PMLS),

- the Parallel Fault Simulator (PFS), and

- the Parallel Pattern Generator (PARPAT).

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These new kernels will be integrated into the existing environ- ment of the DISlM simulation system [9] (Fig.3).

The DISIM system consists of a hardware description lan- guage, an Input Processor translating the high-level hardware description into the Internal Input Interface Format, sequential simulator kernels for logic simulation (DISIM), fault simulation (FESIM) and automatic pattern generation (PATSIM) and an Output Processor convening the Internal Output Interface into the desired representation (e.g. alphanumerics, graphics, in- teractive output).

In the following, we concentrate on PMLS as an example of a sophisticated application for a general purpose parallel ma- chine.

6. MAIN FEATURES OF PMLS

The parallel multi-level simulator (PMLS) is a genera/purpose VLSl simulator covering the register-transfer, functional, gate and switch level. Modelling of signals is performed by four values (0, 1, X, plus Z) and continuous strength (for the switch level).

PMLS is a broadbandsimulator, i.e. there is just one simulation concept for all abstraction levels. This concept is characterised by using distributed discrete event simulation with the circuit partitioning approach, i.e. partitioning of the circuit into subcir- cults which are sire ulated by subsim ulator processes (s. Fig. 2). Each subcircuit may contain elements at different abstraction levels. Subsimulators execute asynchronously using their own local time, communicate by exchanging event messages and synch ronise by the time warp approach [11]. Selective trace is used at the element level as well as at the subcircuit level.The implementation is object-oriented, allowing highly dynamic features like dynamic object creation and dynamic object #7- terconnection, for dynamic simulation (e. g. incremental simu- lation [17]).

The concept delivers sufficient grain size to gain significant speed up on a parallel general purpose machine like DOOM. It is also flexible enough to take advantage of future architectural enhancements of these machines.

PMLS provides a highly interactive user interface including zooming (i.e. dynamic change of the abstraction level) and a high flexibility, i.e. allowing easy modification of the simulator for functional enhancements due to the object--oriented ap- proach.

7. DESIGN OF PMLS

In the following, the software design of PMLS will be outlined, beginning with the design at the process (or active object) level. Thereafter the synchronisation of the subsimulators is dis- cussed and the design of a subsimulator is described in more detail.

7.1 Design at the Process Level

Fig. 4 exhibits the global PMLS design; herein, processes are represented as boxes and messages as arrows.

The Man-Machine Interface accepts commands from the hu- man user terminal and propagates these commands to the Global Controller or (and) the Output Manager.

E. Aposporidis et aL / PMLS - a Parallel Multi-Level VLSI Simulator 575

Terminal Output

Slmulatior Monltorin{ File

Simulatiod Results

Simulation Results

Figure 4: Global design at the Process Level

The Global Controllerreads the partitioned circuit description, creates subsimulators (one for each subcircuit), initialises sub- simulators with their circuit description, determines Global Vir- tual Time (GVT) and performs simulation monitoring.

The Subsimulators simulate their individual subcircuit, ex- change Interface Event Messages and send Output Event Messages to the Output Manager.

The Output Managercollects Output Event Messages and per- forms physical output of that Output Event Messages which are guaranteed not to be cancelled (according to GVT).

7.2 Synchronlsatlon Mechanism

Two basic methods for the synchronisation of subsimulators exist (see Section 3.3). Theoretical considerations as well as si- mulations have shown that the time warp approach exhibits better performance than the conservative strategy, particularly if lazy cancellation (see below) is applied [14,15,16].

In P MLS, the synchronisation of the subsimulators is perform ed by a modified time warp approach: Subsimulators execute asynchronouslyusing their own local simulation time. In case of an event message with a time stamp less than the local time is received, rollback has to be performed. Rollbacks require the maintenance of history information. In our approach, we do not perform checkpointing of the complete state of the subcircuit (as proposed by [11 ]), but save all changes of this state (i.e. his- tory events). Rolling back a subsimulator requires other subsi- mulators to roll back if they received event messages; this is performed by sending antimessages. For minimising rollback of other subsimulators, lazy cancellation is performed in our approach, i.e. sending antimessages only if the sent event

messages have actually proved to be wrong.

7.3 Detailed Design of a Subslmulator

Figure 5 shows the detailed design of a subsimulator:

Figure 5: Detailed design of a Subsimulator

The SubsimulatorController controls all operations of a subsi- mulator. The External Event List holds interface event mes- sagesgenerated by other subsimulators,ordered bytheir sche- duled time stamp. The Internal Event List holds internal (i.e. lo- cal) events generated by this subsimulator in time stamp order. Branches contains static information describing which events (signal id) are propagated to the corresponding elements. Ele- mentobjects model circuit elements such as register level ele- ments (registers, ALUs, RAMs), functional elements (flipflops, counters), gates (AND, OR, NOT), switches (MOS transis- tors). SignalStates maintains all current (i.e. at local time) va- lues of the signals of the subcircuit. SignalState History main- tains all signal changes, i.e. contains events time stamped with Local Virtual Time (LVT) and ordered by LV-F. The EventDistrib- utorlooks at each received event from the elements and deter- mines whether it has to be sent to. The Output Queue stores copies of sent messages for rollback purposes.

576 E. Aposporidis et aL / P M L S - a Parallel Multi-Level VLSI Simulator

8. CIRCUIT PARTITIONING

PMLS expects as input a circuit description (s. Section 5) ac- companied by an appropriate partitioning information. The par- titioning information is crucial for the degree of the effective par- allelism.

Initially, for the PMLS prototype user-defined partitioning is em- ployed. However, for advanced utilisation of PMLS an efficient partitioning algorithm is required. Therefore a heuristic parti- tioning method is currently under development. This partition- ing approach is using activity and communications data meas- ured in a simulation run (or simulation interval) to improve the partitioning for simulation runs (or intervals) that follow. Since during the design of a VLSI circuit, many simulation runs with only a few changes in the circuit have to be carried out, this "semi-adaptive quality improvement method" can be used ef- fectively here.

Our partitioning algorithm takes into account the fact that in the synchronisation through time warp the main loss in speed is caused by rollbacks. Our goal therefore is to minimise this loss factor by achieving load balance in such a mannerthatthe prob- ability of rollbacks and the rollback lengths are minimised. Dur- ing a simulation run following data are recorded: the contribu- tion of each element in a subcircuit to the subsimulator load (execution costs), the communication between subcircuits (communication costs) and the rollback data.

The partitioning procedure that follows calculates element move gains in order to achieve an improved load balance. Thereafter the subcircuits send element transfer messages, causing a reconfigu ration of the subcircuits. The procedure op- erates on the same data structures as the sire ulator and runs on the parallel machine. After the reconfig uration of the subcircuits a new simulation run can start immediately, because the subcir- cult descriptions remain in the local memories of the parallel machine.

A detailed description of this partitioning approach including re- sults will be issued in the near future.

9. PRESENTSTATUS AND RESULTS

Currently, PMLS is in the final implementation stage: The main parts of the sire ulator (tim e warp layerfor the synchronisation of the subsimulators) including switch level, gate level, functional level, and register transfer level have been implemented in POOL. We are currently working on the advanced features like zooming, dynamic change of the circuit structure, incremental simulation, and on tuning of the simulator.

The execution behavior of the simulator is currently measured using the POOL interpreter/DOOM simulator as well as using the 12-node DOOM prototype. Performance measurements on the DOOM simulator with the simulation of small circuits (the random generator benchmark circuit of [18]) and small DOOM node numbers produced the following results (s. Table 2).

The Speed Up is defined as "the execution time of the sequen- tial simulation on a single DOOM node"divided by "the execu- tion time of parallel simulation on n DOOM nodes".

Corresponding tests with medium and large circuits are under way. We expect similar efficiencies (i.e. speed up)when scaling

up circuit size and node numbers.

odes Circuit

4 stage Random Generator

16 stage Random Generator

64 stage Random Generator

4 I 8 Speed Up

2.2

2.8 4.9

3.4 6.9

Table 2: Preliminary performance results

A further result of the project is a Parallel Fault Simulator (PFS, s. Section 5). This simulator splits dynamically the fault set into subsets which are then processed as parallel jobs in the nodes of a local area network. PFS achieves a near linear speed up and is currently under field test.

Summarising our work, we can state that VLSI simulation -as a specialcase of discrete event simulation-is definitely a promis- ing application of parallel general purpose machines like DOOM.

ACKNOWLEDGMENTS

We would like to thankthe Philips team for the excellent cooper- ation and their support in using POOL and DOOM.

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