PMC-SierraUniTX-Altera JESD204BMegacoreIP … · 2020. 8. 10. · RevisionHistory Issue IssueDate DetailsofChange 1 February2014 PreliminarytestreportshowingfullRFchaindatatransfer

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PMC-SierraUniTX - AlteraJESD204B Megacore IPInteroperability ReportPMC-2140377PreliminaryIssue 1: February 2014

Copyright © 2014 PMC-Sierra, Inc. All rights reserved.

The information in this document is proprietary and confidential toPMC-Sierra, Inc. In any event, no part of this document may be reproducedor redistributed in any form without the express written consent ofPMC-Sierra, Inc.

PMC-2140377, Issue 1

None of the information contained in this document constitutes an expressor implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness orsuitability for a particular purpose of any such information or the fitness,or suitability for a particular purpose, merchantability, performance,compatibility with other parts or systems, of any of the products ofPMC-Sierra, Inc., or any portion thereof, referred to in this document.PMC-Sierra, Inc. expressly disclaims all representations and warranties ofany kind regarding the contents or use of the information, including, butnot limited to, express and implied warranties of accuracy, completeness,merchantability, fitness for a particular use, or non-infringement.

In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special,incidental or consequential damages, including, but not limited to, lostprofits, lost business or lost data resulting from any use of or reliance uponthe information, whether or not PMC-Sierra, Inc. has been advised of thepossibility of such damage.

For a complete list of PMC-Sierra’s trademarks and registered trademarks,visit: http://www.pmc-sierra.com/legal/.

Other product and company names mentioned herein may be thetrademarks of their respective owners.

The technology discussed in this document is protected by one or more ofthe following patent grants:

U.S. Patent No. 7,733,149 and 7,884,660. Other relevant patent grants mayalso exist.

2.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers' internal use.Document No. PMC-2140377, Issue 1

PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability Report

Revision History

Details of ChangeIssue DateIssue

Preliminary test report showing full RF chain data transferFebruary 20141

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Table of Contents

1 Definitions ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Introduction ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Device Compatibility .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2 HW Components Used ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Reference Diagrams ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 FPGA Architecture ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.2 JESD204B Link Connection Overview .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.3 Full System Setup ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.4 Full System Photograph ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Interoperability Test Overview .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1 DAC Datapath Testing ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.1 Test Methodology ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1.2 Test Results .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1.3 Test Result Interpretation ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 ADC Datapath Testing ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.1 Test Methodology ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.2 Test Results .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.2.3 Test Result Interpretation ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Interoperability Test Summary ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 References ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.1 Related PMC-Sierra Documents ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.2 Related Altera Documents ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.3 Protocol Standards References ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 End of Document ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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List of FiguresFigure 1 Customized Altera Megacore IP FPGA Design ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 2 JESD204B Link Connection Overview .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 3 Full System Diagram .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 4 System Photograph ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5 Test Signal 1 Spectrum Analyzer Capture ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 6 Test Signal 2 Spectrum Analyzer Capture ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 7 Test Signal 3 Spectrum Analyzer Capture ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 8 Test Signal 4 Spectrum Analyzer Capture ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 9 Test Signal 1 FFT Output ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 10 Test Signal 2 FFT Output ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 11 Test Signal 3 FFT Output ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 12 Test Signal 4 FFT Output ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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List of TablesTable 1 Definitions ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 2 Required SMA Cable Connections for JESD204B Interoperability .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 3 DAC Datapath Test Tone Signals .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 4 ADC Datapath Test Tone Signals .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 5 DAC Datapath Interoperability Test Summary ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 6 ADC Datapath Interoperability Test Summary ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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1 DefinitionsTable 1 Definitions

DefinitionTermAnalog to Digital ConverterADCControl bits per frame on JESD204B linkCFControl bits per sample on JESD204B linkCSDigital to Analog ConverterDACEvaluation BoardEVBDOctets per frame per lane on JESD204B linkFFast Fourier TransformFFTHigh Speed Mezzanine CardHSMCJESD204B Initial Lane Alignment SequenceILAFrames per multiframe on JESD204B linkKLanes in use on JESD204B linkLLine Code ViolationLCVConverters in use on JESD204B linkMBits per sample on JESD204B linkNBits per conversion word on JESD204B linkN'Radio FrequencyRFRadio Frequency Integrated CircuitRFICSamples per converter per frame cycle on JESD204B linkSSerializer / DeserializerSERDES

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportDefinitions

2 IntroductionThis document is a preliminary test report summarizing JESD204B interoperability between the AlteraJESD204BMegacoreTM IP and the PMC-Sierra PM8910UniTXTM integrated dual-transmit, dual-feedbackRFIC device. The testing outlined in this interim report provides a summary of full-systemdata transportbetween the RF interface of the PM8910 UniTX and the system side interface of the Altera JESD204BMegacore IP for one particular JESD204B link configuration. A full test report outlining a variety of linkconfigurations, transport layer test patterns, link startup / error conditions, and deterministic latencywill be published at a later date.

2.1 Device CompatibilityThe DAC datapath testing performedwith the PM8910 UniTX is equally applicable to the other deviceswithin the PMC-Sierra UniTX device family, as they share the same JESD204B RX subsystem.

The ADC datapath testing performedwith the PM8910 UniTX is equally applicable to the other deviceswithin the PMC-Sierra UniTX device family, as well as the PMC-Sierra UniRX device family, as theyshare the same JESD204B TX subsystem.

For questions related to any specific device variant within the UniTX or UniRX device families, pleasecontact your local PMC-Sierra sales representative.

2.2 HW Components UsedThe following components were used to perform the testing outlined in this document:

• Altera Arria V GT Development Kit• PM8910 UniTX Evaluation Card• UniXX Main board, containing PM7520 SyntheCLK Clock Generator Device, and host processor for

configuring UniTX• Terasic XTS HSMC SMA Breakout Board• PMC-Sierra Custom HSMC SMA Breakout Board• SMA cables• Spectrum Analyzer• Signal Generator• Reference Clock Source

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportIntroduction

3 Reference DiagramsThis section provides a variety of diagrams to illustrate the system architecture used in completingthe interoperability testing.

3.1 FPGA ArchitectureThe Altera JESD204BMegaCore IP incorporates data link layer (DLL) and physical layer (PHY) subsystemsfor JESD204B applications. For the purposes of interoperability testing, an FPGA design was createdconsisting of a customized Tx core, Rx core, and PHY layer subsystem. Customized transport layerfunctions were added to the Tx & Rx datapaths, as well as the use of encoder/decoder memories forinserting/extracting raw sample data. The FPGA design is controlled through aMatlab interface withinthe DSPBuilder component of the Altera Quartus II software. A diagram showing a high level view ofthe FPGA architecture is shown in Figure 1.

Figure 1 Customized Altera Megacore IP FPGA Design

JESD204BTX IP Core

JESD204BRX IP Core

GT TrasceiverSubsystem

Rx FrameDe-

Assembly

EncoderMemory

DecoderMemory

Tx FrameAssembly

Control

JESD204_TXDATA

JESD204_RXDATA

JESD204_TXSYNCBJESD204_RXSYNCBSYSREFSYSCLK

JTAG

JESD204B DataLink Layer JESD204B Phyiscal LayerJESD204B

Transport LayerSample Data

Insertion / Extraction

Control

Control

Ch 0

Ch 2

Ch 3

Ch 1

Ch 0

Ch 2

Ch 3

Ch 1

Ch 0

Ch 1

Ch 1

Ch 0

Arria V GT

The FPGA implementation used for this interoperability testing is customized for the following linkoperating conditions:

• 4 Lane, 4 converter operation for DAC direction (JESD204B TX IP Core)• 2 Lane, 2 converter operation for ADC direction (JESD204B RX IP Core)• S=1, F=2, K=32, N=16, N'=16, CF=0, CS=0, Scrambling=OFF JESD204B link parameters• 6.144 Gbps SERDES operation• 153.6 MHz SYSCLK input• 9.6 MHz SYSREF input

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportReference Diagrams

3.2 JESD204B Link Connection OverviewFigure 2 provides an overview of the various evaluation boards and SMA breakout boards used tocreate a JESD204B link connection between the PM8910 UniTX device and Altera Arria V GT FPGA,with the PMC-Sierra PM7520 SyntheCLK clock generator device being used to provide the necessarySYSCLK and SYSREF clocking signals to both sides of the JESD204B link.

Figure 2 JESD204B Link Connection Overview

Altera Arria V GTDevelopment Kit

AlteraArria V GTFPGA

UniXX Main Board

ControlFPGA

PowerSupply

Test Points

JESD204_RXDATA_P/N[1:0]

JESD204_TXDATA_P/N[3:0]

JESD204_RXSYNCB

JESD204_TXSYNCB

SyntheCLK

PM7520

PM8910 UniTX Evaluation Board

PM8910UniTXUniTX

PM8910

JESD204B_TX_P/N[1:0]

JESD204_TXSYNCB

JESD204_RXSYNCB

SPI

SYSREF_P/N

ClockBuffer(U56)

SYSCLK_P/N

HSMC Connector

HSMCConnector

SYSREF_UNITX_P/N

SYSCLK_FPGA_P/N

SYSREF_FPGA_P/N

REFCLK_P

SYSCLK_UNITX_P/N

TXRF_OUT_A

TXRF_OUT_B

FBRF_IN_A

FBRF_IN_B

JESD204B_RX_P/N[7:4]

TM

TM

PMCS CustomHSMC Breakout

board

Terasic XTS HSMCBreakout board

HSMCConnector

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The following table provides a list of necessary SMA cable connections required for JESD204B interop-erability testing.

Table 2 Required SMA Cable Connections for JESD204B Interoperability

DestinationConnector

Label

Destination ConnectorBoard

SourceConnector

Label

Source Connector BoardSignal Description

J3PMCS HSMC BoardJ21XTS HSMC BoardDAC Datapath JESD204B_P[0]J4PMCS HSMC BoardJ23XTS HSMC BoardDAC Datapath JESD204B_N[0]J5PMCS HSMC BoardJ17XTS HSMC BoardDAC Datapath JESD204B_P[1]J6PMCS HSMC BoardJ19XTS HSMC BoardDAC Datapath JESD204B_N[1]J7PMCS HSMC BoardJ13XTS HSMC BoardDAC Datapath JESD204B_P[2]J8PMCS HSMC BoardJ15XTS HSMC BoardDAC Datapath JESD204B_N[2]J9PMCS HSMC BoardJ9XTS HSMC BoardDAC Datapath JESD204B_P[3]J10PMCS HSMC BoardJ11XTS HSMC BoardDAC Datapath JESD204B_N[3]J22XTS HSMC BoardJ16PMCS HSMC BoardADC Datapath JESD204B_P[0]J24XTS HSMC BoardJ17PMCS HSMC BoardADC Datapath JESD204B_N[0]J18XTS HSMC BoardJ14PMCS HSMC BoardADC Datapath JESD204B_P[1]J20XTS HSMC BoardJ15PMCS HSMC BoardADC Datapath JESD204B_N[1]

CLKIN0(Testpoint)

XTS HSMC BoardJ13PMCS HSMC BoardDAC Datapath SYNCb

J20PMCS HSMC BoardCLKOUT1(Testpoint)

XTS HSMC BoardADC Datapath SYNCb

CLKIN_P1(Testpoint)

XTS HSMC BoardJ19UniXX Main BoardFPGA SYSREF_P

CLKIN_N1(Testpoint)

XTS HSMC BoardJ20UniXX Main BoardFPGA SYSREF_N

J17Arria V GT Dev KitJ6UniXX Main BoardFPGA SYSCLK_PJ18Arria V GT Dev KitJ7UniXX Main BoardFPGA SYSCLK_N

3.3 Full System SetupFigure 3 provides an overview of the test equipment used to complete the interoperability testingoutlined in this report. In addition to the required evaluation boards and HSMC connector boards, thefollowing equipment was used:

• Clock Generator to provide 30.72 MHz REFCLK reference signal to the PM7520 SyntheCLK clockgenerator device.

• Spectrum analyzer to capture PM8910 UniTX RF output signal (DAC datapath testing).• Tone generator to generate PM8910 UniTX RF input signal (ADC datapath testing).• Laptop for initialization / configuration of Altera Arria VGT and PM8910UnITX evaluation platforms.

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Figure 3 Full System Diagram

UniXX MainBoard

PM8910 UniTXEvaluation Board

PMCS CustomHSMC Breakout

Board

Altera Arria V GTDevelopment Kit

Spectrum Analyzer

Terasic XTSHSMC Breakout

Board

USB Control

SMA Cables

USB Control

RF_OUT

RF_IN

Single Tone Generator

Reference ClockGenerator

3.4 Full System PhotographA photograph of the boards outlined in Figure 2 with the cable connections from Table 2 is shownbelow.

Figure 4 System Photograph

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4 Interoperability Test OverviewAs each direction of the JESD204B interface operates independently, the interoperability testing isseparated into two distinct testbeds: DAC datapath testing and ADC datapath testing.

4.1 DAC Datapath TestingThe JESD204B portion of the DAC datapath is the path from DAC sample data insertion at the encodermemory in the Arria V GT FPGA (see Figure 1) to the demapped sample data at the egress of theJESD204BRX interfacewithin the PM8910UniTX device. For the purposes of this preliminary test report,a full chain data throughput test was performed to demonstrate operation of the full datapath fromArria V GT FPGA encoder memory to PM8910 UniTX RF output.

4.1.1 Test MethodologyWith the HW setup shown in Figure 3, the PM8910 UniTX DAC datapath was configured with the fol-lowing operating conditions:

• 4 Lane, 4 converter operation• S=1, F=2, K=32, N=16, N'=16, Scrambling=OFF JESD204B link parameters• 6.144 Gbps SERDES operation• 753.6 MHz RF center frequency output

A Matlab-based signal generator function was used to create I/Q sample streams representing thefollowing single-tone signal formats:

Table 3 DAC Datapath Test Tone Signals

I/Q Sample Rate(MSPS)

Power Backoff (dBFS)Offset From RF CenterFrequency (MHz)

Test Signal

307.2-111

307.2-522

307.2-943

307.2-1384

The sample data representing the tones was inserted via the encoder memory of the Arria V GT FPGAand the resulting RF output was observed on a spectrum analyzer connected to the RF output portsof the PM8910 UniTX device. The sample data was injected into the system in two separate formats:having the same tone applied to both pairs of I/Q converters as well as having unique tones appliedto each pair of I/Q converters. In all cases, the RF output from I/Q path A as well as I/Q path B of thePM8910 UniTX was observed on a spectrum analyzer.

In addition, during each test scenario, the link was restarted to ensure spectrum analyzer output re-turned to the previous state and that the link did not experience any error conditions.

4.1.2 Test ResultsThe dual RF outputs from the PM8910 UniTX Evaluation Board were separately observed on thespectrum analyzer to ensure the frequency and power of the resulting output tones appeared as ex-pected. In addition, diagnostic registers within the PM8910 UniTX device were examined and showedthat the JESD204B Rx interface remained error free and properly synchronized after the link restartoperation.

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportInteroperability Test Overview

The following diagrams provide screen captures of the test signals captured on the spectrum analyzer.

Figure 5 Test Signal 1 Spectrum Analyzer Capture


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4.1.3 Test Result InterpretationThe spectrum analyzer captures showing tones of the correct frequency offset and relative powerbackoff demonstrate that the sample data injected into the encoder memory of the Altera ArriaV GTFPGAwas successfully transported across the JESD240B interface and converted to an RF signal withinthe PM8910 UniTX device.

This testing demonstrates interoperability of the JESD204B interface between the Altera MegacoreJESD204B TX IP within an Arria V GT FPGA and the PM8910 UniTX for one particular JESD204B link

15.



configuration at 6.144 Gbps. Further test results showing a variety of different link configurations andtest patterns / error conditions as well as deterministic latency operation will be published in a futurerevision of this document.

4.2 ADC Datapath TestingThe JESD204B portion of the ADC datapath is the path from ADC output sample data at the ingress ofthe JESD204B TX interface within the PM8910 UniTX device to the decoder memory in the Arria V GTFPGA (see Figure 1). For the purposes of this interim test report, a full chain data throughput test wasperformed to demonstrate operation of the full datapath from PM8910 UniTX RF input to Arria V GTFPGA decoder memory.

4.2.1 Test MethodologyWith the HW setup shown in Figure 3, the PM8910 UniTX ADC datapath was configured with the fol-lowing operating conditions:

• 2 Lane, 2 converter operation• S=1, F=2, K=32, N=14, N'=16, Scrambling=OFF JESD204B link parameters• 6.144 Gbps SERDES operation• 1GHz LO operation

An external signal generator was used to inject a tone with the following parameters:

Table 4 ADC Datapath Test Tone Signals

Signal Amplitude(dBm)

Center Frequency(GHz)

Test Signal

51.011

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The signal generator outputwas connected to the RF input port of the PM8910UniTX and the resultingoutput sample data was extracted from the decoder memory within the Arria V GT FPGA. A Matlab-based FFT function was performed on the sample data to capture the resulting frequency domainsignal. The test tones from the signal generator were injected into both RF input ports (one RF inputport at a time) of the PM8910 UniTX and the FFT function was performed for each resulting convertersample stream at the FPGA decoder memory to ensure there was no tone detected from the unusedRF input.

In addition, during each test scenario, the link was restarted to ensure spectrum analyzer output re-turned to the previous state and that the link did not experience any error conditions.

4.2.2 Test ResultsThe frequency based FFT function output from the FPGA decoder memory was plotted in Matlab toensure the frequency and power of the resulting output data appeared as expected. In addition, dia-gnostic registers within the Arria V GT FPGAwere examined and showed that the JESD204B Rx interfaceremained error free and properly synchronized after the link restart operation.

The following diagrams provide screen captures of the test signals captured on the spectrum analyzer.

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Figure 9 Test Signal 1 FFT Output

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ADC Capture Spectrum


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4.2.3 Test Result InterpretationThe Matlab FFT outputs showing tones of the correct frequency offset and relative power backoffdemonstrate that the RF tones injected into the PM8910 UniTX device were successfully sampled andtransported across the JESD204B interface.

This testing demonstrates interoperability of the JESD204B interface between the PM8910 UniTX andthe Altera Megacore JESD204B RX IP within an Arria V GT FPGA for one particular JESD204B link con-figuration at 6.144 Gbps. Further test results showing a variety of different link configurations and testpatterns / error conditions as well as deterministic latency will be published in a future revision of thisdocument.

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5 Interoperability Test SummaryThe following table provides a quick-view summary of completed interoperability tests.

Table 5 DAC Datapath Interoperability Test Summary

ResultSCRN'NKSFMLLink Speed(Gbps)

Test Name

PASSOFF16163212446.144Full Chain Throughput

Table 6 ADC Datapath Interoperability Test Summary

ResultSCRN'NKSFMLLink Speed(Gbps)

Test Name

PASSOFF16143212226.144Full Chain Throughput

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportInteroperability Test Summary

6 References

6.1 Related PMC-Sierra Documents1. PMC-2102763, PM8910 UniTX Product Datasheet2. PMC-2123939, PM8921 UniRX Product Datasheet3. PMC-2124189, JESD204B Debug Guide for UniTX / UniRX

6.2 Related Altera Documents4. UG-01142, JESD204B MegaCore Function User Guide

6.3 Protocol Standards References5. JEDEC JESD204B, Serial Interface for Data Converters, Issue 1, 2011

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportReferences

7 End of Document

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PMC-Sierra UniTX - Altera JESD204B Megacore IP Interoperability ReportEnd of Document