Pluto 5 Specification - Heberdownload.heber.co.uk/pdfdownloads/calypso16_um.pdf · 2014-10-28 · In a separate document, the Pluto 5 Software User Manual, Heber Document number 80-16040

File Name: \\heber1\h1_usr2\pluto5\manuals\calypso16.docDocument No. 80-16484 Issue 3

Pluto 5 Calypso 16 Card ManualDocument No. 80-16484 Issue 3 HEBER LTD

Current Issue: - Issue 3 - 27th April 2004

Previous Issues: - Issue 1 - 4th October 2001Issue 2 - 20th June 2002Issue 2r1 - 22nd October 2002

©HEBER Ltd. 2004. This document and the information contained therein is the intellectual property ofHEBER Ltd. A single copy may be printed, but otherwise it may not be reproduced in any formWHATSOVEVER. Further copies may be obtained from Heber Ltd.

File Name: \\heber1\h1_usr2\pluto5\manuals\calypso16.docDocument No. 80-16484 Issue 3

HEBER LTDBelvedere Mill

ChalfordStroud

GloucestershireGL6 8NTEngland

Tel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013

Email: [email protected]://www.heber.co.uk

mailto:[email protected]

http://www.heber.co.uk/

Page i

Document No. 80-16484 Issue 3 HEBER LTD

CONTENTS

1 INTRODUCTION.................................................................................................................... 1

2 OVERVIEW............................................................................................................................ 1

3 CIRCUIT SCHEMATIC DESCRIPTION ................................................................................ 2

3.1 SHEET 1 .................................................................................................................................. 23.2 SHEET 2 .................................................................................................................................. 23.3 SHEET 3 .................................................................................................................................. 23.4 SHEET 4 .................................................................................................................................. 23.5 SHEET 5 .................................................................................................................................. 23.6 SHEET 6 .................................................................................................................................. 23.7 SHEET 7 .................................................................................................................................. 2

4 CIRCUIT OPERATION .......................................................................................................... 3

4.1 FPGA...................................................................................................................................... 34.2 IDE INTERFACE........................................................................................................................ 34.3 RS232 INTERFACE................................................................................................................... 34.4 EXPANSION CONNECTORS - BUS BUFFERING............................................................... 34.5 EPROM EXPANSION ............................................................................................................ 34.6 FUJITSU CREMSON GRAPHICS CONTROLLER ............................................................... 34.7 VIDEO DISPLAY MEMORY................................................................................................... 4

5 OPERATION.......................................................................................................................... 4

5.1 MEMORY MAP ...................................................................................................................... 45.2 CALYPSO 16 CARD MAPPING ............................................................................................ 4

6 VIDEO CAPABILITIES .......................................................................................................... 5

6.1 SCREEN RESOLUTION............................................................................................................... 56.2 KEY FEATURES ........................................................................................................................ 56.3 VIDEO LAYER ARCHITECTURE ................................................................................................... 5

6.3.1 Console Layer.................................................................................................................... 66.3.2 Window Layer .................................................................................................................... 66.3.3 Middle Layer ...................................................................................................................... 66.3.4 Base Layer......................................................................................................................... 6

6.4 PERFORMANCE LIMITATIONS ..................................................................................................... 66.4.1 Video Memory Bandwidth.................................................................................................. 66.4.2 Achievable Performance.................................................................................................... 7

7 CONNECTOR TYPES AND PIN-OUTS ................................................................................ 7

1.1 P7 - VIDEO OUTPUT CONNECTOR ............................................................................................. 77.2 P6 - VIDEO OUTPUT CONNECTOR ............................................................................................. 77.3 P3 - MEMORY EXPANSION CARD CONNECTOR .......................................................................... 87.4 P4 - IDE CONNECTOR.............................................................................................................. 9

Page ii


LIST OF FIGURES

Figure 1 - Calypso 16, Schematic Sheet 1............................................................................................ 11Figure 2 - Calypso 16, Schematic Sheet 2............................................................................................ 12Figure 3 - Calypso 16, Schematic Sheet 3............................................................................................ 13Figure 4 - Calypso 16, Schematic Sheet 4............................................................................................ 14Figure 5 - Calypso 16, Schematic Sheet 5............................................................................................ 15Figure 6 - Calypso 16, Schematic Sheet 6............................................................................................ 16Figure 7 - Calypso 16, Schematic Sheet 7............................................................................................ 17Figure 8 - Calypso 16, Photograph ....................................................................................................... 18

Page iii


This page deliberately left blank

Page 1


1 INTRODUCTION

The Pluto 5 Calypso 16 card provides a high performance video capability for the Pluto 5 family ofproducts. The card represents an evolutionary development of the CGA/VGA video system. It providesenhanced performance while maintaining compatibility with software written for the Pluto 5 videosystem.

The card additionally provides:• A standard IDE interface, to which a Hard Drive or ATAPI CD-ROM can be connected.• An RS232 serial port, which can be used to connect to a touch screen.• Expansion EPROM.

This manual covers the detail of the hardware operation of the Pluto 5 CGA/VGA Card.The Software Driver functions that provide the Application Interface to this board are describedIn a separate document, the Pluto 5 Software User Manual, Heber Document number 80-16040

2 OVERVIEW

The Pluto 5 CALYPSO 16 Card is an add-on board for the Pluto 5 Controller Board, which plugs intothe Memory and I/O Expansion Card Connectors. The Memory Expansion Card Connector isduplicated on the CALYPSO 16 Card, allowing a Pluto 5 Memory Expansion Card to also be fitted.

The card is based around a Fujitsu Cremson Graphics Controller IC, and will directly drive ananalogue colour monitor. This device supports a number of screen resolutions varying from CGA(640x225) to SVGA (1024 x 768).

Supported colour depths are 8 bits per pixel (256 colours) and 16 bits per pixel (32, 768 colours).

Calypso 16 is fitted with 16 Mbyte of Video Display Memory. In addition, two 42 pin EPROM socketsare provided, allowing up to 8 Mbytes of expansion EPROM to be fitted.

A standard 40 pin IDE connector is fitted, which provides an interface to a Hard Drive or CD-ROM.

Page 2


3 CIRCUIT SCHEMATIC DESCRIPTION

This section is a walk through of the Pluto 5 CALYPSO 16 Card circuit schematics, document number56-16318. A detailed description is given in Section 4 "CIRCUIT OPERATION".

3.1 Sheet 1

This sheet shows the interconnection between the remaining sheets of this drawing.

3.2 Sheet 2

This sheet shows the following items: -

• Address and Data bus buffers.• Pluto 5 I/O and Memory Expansion Connectors. (P1 and P2)• Duplicated Memory Expansion Connector. (P3)

3.3 Sheet 3


• IDE Connector. (P4)• Two 42 pin EPROM Expansion Sockets. (U1 and U2)• RS232 Interface and Connector. (P5)

3.4 Sheet 4


• Xilinx FPGA.• Serial EEPROM for initialising FPGA.

3.5 Sheet 5


• Cirrus Cremson VGA Controller.• Video Output Connectors (P5 and P6)

3.6 Sheet 6


• Video Display Memory (16 MBytes)

3.7 Sheet 7


• Voltage Regulators.

Page 3


4 CIRCUIT OPERATION

4.1 FPGA

U10 is a Xilinx XS10 FPGA (Field Programmable Gate Array). It performs the following functions: -

• Address decoding.• Motorola CPU 32 to SH4 bus conversion• 16 bit to 32 bit data bus translation.• IDE Interface.• Single channel UART• PROM autoselect.

The Xilinx FPGA is RAM based, and the internal logic is configured during RESET by a Serial bit-stream generated by U11, which is a XC17S10XL eight pin socketed serial EEPROM

4.2 IDE Interface

The ATA-2 standard IDE interface is implemented within the FPGA, and a standard 40pin connectorP4 is provided. Additional buffering is provided on the RESET line, to prevent retriggering whenconnected to external drives with significant capacitive loading on the RESET line.

4.3 RS232 Interface

A single UART is implemented within the FPGA. Receive RXD and transmit TXD signals are provided,together with RTS and CTS handshaking. Signal level conversion is provided by U9, a MAX232device. The transmit clock and sixteen times receive clock are generated by subdivision from the CPUclock (16.77 MHz) giving an acceptable percentage error of 0.5 per cent.

4.4 EXPANSION CONNECTORS - BUS BUFFERING

The Pluto 5 address bus is buffered by octal buffers U4, U5, and U7. The data bus is buffered bi-directionally by U3, U8. A standard 9W D-type connector, P5, is fitted.

4.5 EPROM EXPANSION

Sockets are provided for up to two 42 pin EPROMs U1, U2. This allows up to 8Mbytes of expansionEPROM to be fitted to the board, if two 27C322 devices (2Mbyte x16) are fitted.

4.6 FUJITSU CREMSON GRAPHICS CONTROLLER

U12 is a Fujitsu Cremson device. This is configured by option links to implement a Hitachi SH4 businterface. Bus conversion between SH4 and Motorola CPU32 type control and status signals isperformed by the FPGA, together with 16 bit to 32 bit data bus conversion.

The analogue R, G, and B video outputs are terminated by R15, R16 and R17 and filtered by pi filtersL7-L9, C80-85. Separate horizontal and vertical syncs are generated. Diode clamps D1, D2, D7-D9provide protection against display monitor transients.

Page 4


4.7 VIDEO DISPLAY MEMORY

A total of 16 megabytes of display memory is fitted. This uses 100MHz SDRAMs, organised as two 4Mx 16 DRAMs, U14 and U15. The data path width to the Cremson controller is 32 bits. The displaymemory is mapped into the Pluto 5 address space via the Cremson controller.

5 OPERATION

5.1 MEMORY MAP

The default Pluto 5 system memory map is advised:

Chip Select Function Address SizeCS0-CS1-CS2-CS3-

EPROMRAMIO/FPGAVGA

0000 0000 - 00FF FFFF0100 0000 - 01FF FFFF0200 0000 - 02FF FFFF0300 0000 - 03FF FFFF

16Mbyte16Mbyte16Mbyte16Mbyte

To achieve these settings, the CS registers in the SIM40 module of the 68340 should be set asfollows;

SIM40 REG VALUE COMMENTSI_CSAM0I_CSBA0I_CSAM1I_CSBA1I_CSAM2I_CSBA2I_CSAM3I_CSBA3

00FF FFFD0000 0009000F FFFD0100 000100FF FFFF0200 0001000F FFFF0300 0001

All spaces, 3 wait states, 16 bit port, r only0000 0000 – 00FF FFFF (EPROM, 16Mb)All spaces, 3 wait states, 16 bit port, r/w0100 0000 – 010F FFFF (RAM, 16Mb)All spaces, 3ext dtack, 16 bit port, r/w0200 0000 – 02FF FFFF (PLUTO 5 FPGA, 16Mbyte)All spaces, ext dtack, 16 bit port, r/w0300 0000 – 030F FFFF (VGA BOARD, 16Mb)

Note the programming of CS2 & CS3 for external DTACK operation.

5.2 CALYPSO 16 CARD MAPPING

The card is located in the memory area addressed by CS3-.

Access is mapped as 5 blocks, as follows:

FUNCTION PLUTO 5 ADDRESSCremson RegsGraphics MemoryIDE Command RegsIDE Control RegsUART Control RegUART Data Reg

3FC0000 – 3FFFFF30000000 -- 3EFFFF3FA0000 – 3FA000F3FB000A3FB00003FB0002

Page 5


6 VIDEO CAPABILITIES

The Calypso 16 card uses the Fujitsu Cremson MB86290A graphics display controller. The Cremsongraphics display controller enables an image or an animation to be displayed on the screen withdisplay frames of up to four layers. The Cremson graphics display controller can display 8 bit and 16bit colour

6.1 Screen Resolution

Calypso 16 works with three main screen resolutions. The screen resolutions are set in the software.The main possible screen resolutions are:

• 640 x 480• 800 x 600• 1024 x 768

6.2 Key Features

The key features of Calypso 16 are:

• Up to 4 layers of overlaid video display frames• 8 bit colour depth (256 colours)• 16 bit colour depth (32, 768 colours)• Alpha Blending (Console layer only)• Double Buffering• Drawing features

6.3 Video Layer Architecture

The Fujitsu Cremson video processor can display four layers of display frames on top of each other.Each layer has different display properties such as the number of bytes per pixel, the ability to be split,display priority, and possible transparency.

Page 6


6.3.1 Console Layer

The Console layer contains a single logical graphics display field (C-Layer) which has the highestdisplay priority and can display 8 or 16 bits per pixel images. The console layer is the only layer thatallows Alpha Blending.

6.3.2 Window Layer

The Window layer contains a single logical graphics display field (W-layer) which has the secondhighest display priority and can only display 16 bits per pixel images. No transparency can be set forthis layer. The window layer size (not the logical graphics field) is not necessarily full screen, unlike theother three layers. The position parameter as well as the size of the layer must be definedindependently for it to be visible.

6.3.3 Middle Layer

The Middle layer is split vertically into left (ML-Layer) and right (MR-Layer) logical graphics displayfields. It is possible to set one of the two to represent the dimensions of the physical display. In thiscase the layer behaves as though it has a single display field. The Middle left layer and Middle rightlayer logical graphics fields have the third highest display priority and can display 8 or 16 bits per pixelimages. The Middle layer frames also support Double Buffering.

6.3.4 Base Layer

The Base layer is split vertically into left (BL-Layer) and right (BR-Layer) logical graphics displayfields. It is possible to set one of them to represent the dimensions of the physical display. In this casethe layer behaves as though it has a single logical graphics field. The Base left layer and Base rightlayer logical graphics fields have the lowest display priority and can display 8 or 16 bits per pixelimages. The Base layer frames also support Double Buffering.

6.4 Performance Limitations

Calypso 16 supports 8 bit colour with up to 4 layers at all screen resolutions. Calypso 16 also supports16 bit colour. However, at certain screen resolutions and depending on the number of layers used,there is on screen video disturbance. This is because the higher the resolution and the more layersthat are used, the more data that is needed to be written to and read from memory.

6.4.1 Video Memory Bandwidth

The performance limits are fixed by the memory bandwidth between the Cremson video controller andthe SDRAM video memory. On-screen disturbances occur when the required memory bandwidth isgreater than the maximum memory bandwidth.

The required memory bandwidth increases with:

• screen resolution• colour depth• number of active display layers• CPU to video memory activity• Cremson drawing activity• use of Alpha Blending

When on-screen disturbances occur, possible solutions are:• reducing the colour resolution of the layers• reducing the resolution of the layers• reducing the number of layers

Page 7


Heber recommends that only a certain number of layers are used at particular screen resolutions, asdetailed in the table below.

6.4.2 Achievable Performance

8 Bit Colour 16 Bit ColourResolution(pixels) 1 Layer 2 Layers 3 Layers 4 Layers 1 Layer 2 Layers 3 Layers 4 Layers

640 x 480800 x 6001024 x 768

Key

: OK to use these number of layers at this particular resolution: Bandwidth limitation produces possible screen disturbances

7 CONNECTOR TYPES AND PIN-OUTS

7.1 P7 - Video Output Connector

Reference: P7Type: Header 6W AMP MTA-100Description: Video Output Connector

1 RED2 GREEN3 BLUE4 HSYNC5 VSYNC6 GND

7.2 P6 - Video Output Connector

Reference: P6Type: 15W Hi-Density DtypeDescription: Video Output Connector

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Page 8


PIN SIGNAL PIN SIGNAL PIN SIGNAL1 RED 6 GND 11 nc2 GREEN 7 GND 12 nc3 BLUE 8 GND 13 H_SYNC4 nc 9 nc 14 V_SYNC5 GND 10 GND 15 nc

7.3 P3 - Memory Expansion Card Connector

Reference: P3Type: DIN41612, C/" Socket VerticalDescription: Connector for Memory Expansion Boards

A B c1 A4 A5 A62 VCC A7 A83 VCC A9 A104 A3 A11 A125 A2 A13 A146 A1 A15 A167 GND A17 A188 GND A19 ROM_P19 MEM_BRD- A21 D1510 ROM_CE3- D14 D1311 ROM_CE4- D12 D1112 FPGA3 D10 D913 FPGA4 D8 D714 FPGA5 D6 D515 A22 D1 D316 D0 D2 D4

Page 9


7.4 P4 - IDE Connector

Reference: P4Type: 40W HeaderDescription: IDE Connector for CD-ROM

RESET- 1 2 GNDD7 3 4 D8D6 5 6 D9D5 7 8 D10D4 9 10 D11D3 11 12 D12D2 13 14 D13D1 15 16 D14D0 17 18 D15

GND 19 20 KEYPINnc 21 22 GND

IOW- 23 24 GNDIOR- 25 26 GND

IORDY- 27 28 SYN/SELnc 29 30 GND

INTR 31 32 IO16-A1 33 34 PDIAG-A2 35 36 A3

CS1FX- 37 38 CS3FX-DASP- 39 40 GND

Page 11

Document No. 80-16484 Issue HEBER LTD

Figure 1 - Calypso 16, Schematic Sheet 1

BD[0..15]

PCLK

XWE2

Sheet 03 - EPROM/IDE/RS232

Sheet 03 - EPROM/IDE/RS232

A[0..23]

D[0..15]

ROM1_OE-ROM2_OE-

BYTE/A21

RXD-

CTS-RTS-

TXD-

RESET-

DIOW-DIOR-IORDY

INTRQIOCS16-

DA1

DA2DA0

CS0-CS1-

BD[0..15]

MD[0..31]

BD[0..15]

MCLK

ROM1_OE-

FPGA5

MCKE

MEM_BRD-

XWE1

SIZ0

Sheet 02 - Pluto 5 Interface

Sheet 02 - Pluto 5 Interface

D[0..15]

A[0..23]

BD[0..15]

BA[0..23]

ABUFEN-DBUFEN-

AS-DS-RW-

DSACK0DSACK1

SIZ0

INT_VIDEOINT_IDEROM_P1

SIZ1

MEM_BRD-ROM_CE3-ROM_CE4-ROM_CE1-ROM_CE2-

FPGA5

RESET-

CLKOUT

CS3-

BRW-

AS-

CS0-

IORDY

Sheet 06 - SDRAM

Sheet 06 - SDRAM

MA[0..13]

MCAS-MWE-MCKEMCLK

MDQM[0..3]

MD[0..31]

MRAS-

A[0..23]

MWE-

Sheet 04 - FPGA

Sheet 04 - XCS10XL FPGA

GD[0..31]

BD[0..15]

INTRQ

IORDY

CS1-CS0-DA2DA0

DA1

DIOR-DIOW-

IOCS16-

DBUFEN-

CTS-

RXD-

RTS-

TXD-

RW-

ROM1_OE-

AS-

INT_VIDEO

DS-

DSACK1

ROM_CE1-

INT_IDE

SIZ0

ROM2_OE-

MEM_BRD-

ROM_CE2-FPGA5

ROM_CE4-

DSACK0

SIZ1

ROM_P1

BYTE/A21

ROM_CE3-

CS3-

XWE2

XINT

XWE3

XRDY

XRDXCS

XWE0

PCLK

XRESET

XWE1

XBS

ABUFEN-

RESET-

CLKOUTGA[23..24]

BRW-

BA[0..23]

RST/OE

ROM_CE2-

RST/OEXBS

RESET-

MA[0..13]

IOCS16-

DSACK1

CLKOUT

DA2

XRESET

DA0

ROM1_OE-

XWE0ROM_P1

XRDMRAS-

D[0..15]

Sheet 07 - Power

Sheet 07 - Power

GA[23..24]

DBUFEN-

ROM_CE1-

INTRQ

GD[0..31]

BYTE/A21

RTS-

56-16318 5

Pluto 5 - Calypso 16 Video Board

Heber Ltd

Belvedere Mi llChalford, StroudGlos GL6 8NTTel 44 (0) 1453 886000

A3

1 7Thursday, May 02, 2002

Title

Size Document Number Rev

Date: Sheet of

MDQM[0..3]

DSACK0XCSBYTE/A21

INT_IDE

BA[0..23]

DA1

RESET-

CS1-

CS3-

ROM2_OE-

BRW-

ABUFEN-

ROM_CE4-

CTS-

MCAS-

RW-

INT_VIDEO

XRDY

Sheet 05 - CREMSON Video

Sheet 05 - CREMSON Video

MA[0..13]

MDQM[0..7]

MCAS-MWE-MCKE

MD[0..63]

MCLK

GA[23..24]

GD[0..31]

XBSXCSXRD

XWE0XWE1XWE2XWE3

XINT

XRDY

BA[0..23]

MRAS-

PCLK

XRESET

RST/OE

XINT

© Heber Ltd 2001, 2002

RXD-

BA[0..23]

ROM_CE3-

TXD-

DS-

ROM2_OE-

DIOW-DIOR-

XWE3

SIZ1

Page 12



BD3

D7

P3C

DIN 48_ABC-R

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16

A3

D[0..15]

PP251Probe Point

GND

BA[0..23]

A22

FPGA5 4

A4

D4

D2

FPGA5

FPGA4

A0

A2

U474LCX245

23456789

1817161514131211

191

20

10

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

G-DIR

VC

CG

ND

BA11

N1

10K*8

123456789

INT_VIDEO 4

BA1A9

D14

+5V

BD11

A15

D7

GND

BA18

A14

A9

BD5

GND A7

PP254Probe Point

BD1 C1

100n

+5V

A17

BD12

ROM_CE2-

BA[0..23] 4,5

BA6A19

D15

CLKOUT

DS- 4AS- 4

BA5

CS3-

GND

A17

D12

D5

DSACK1

BA16

P1C

DIN 48_ABC-R


D1

BD15

PP247Probe Point

A5

D2

BA21

D11

BD15

+3.3V

BA4A15

A11

A6

A21

D3

D0

RW-

MEM_BRD- 4

BD3A6

FPGA5

CLKOUT 4BA23

D9

A12

ABUFEN- 4

+5V

BD9

D4

ROM_CE3- BRW- 4

A13

FPGA3

A23

BD10

GND

GND

INT_VIDEO

ROM_CE1-

ROM_CE2- 4

BD6

BD2

RESET-

PP246Probe Point

D7

A23

+3.3V

A7

D11

RW-

DSACK14

GND

BA3

DSACK0

D1

A6

ROM_CE4-

SIZ1

+3.3V

BA20

A1

D13

D9

A19

BD7

D6

BA9

A13

D8ROM_CE4- 4

BA13

A8

BD4

D0

SIZ1 4

SIZ0

A2

DBUFEN-

DSACK04

D5

PP250Probe Point

GND

A10

BD0

D3

U774LCX245

23456789

1817161514131211

191

20

10

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

G-DIR

VC

CG

ND

56-16318 5


Heber Ltd


A3


Title


Date: Sheet of

+3.3V

BD8

GND

GND

A5

BD1

A0

P2B

DIN 48_ABC-R

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16

DS-

D9

D13

DSACK1

BD7

BD[0..15]

GND

BA8

+3.3V

A12

RESET- 3,4

BA10

BD13

PP249Probe Point

BD6

BD13

A9

A21

MEM_BRD-

A15

D6

D12

ROM_CE3- 4

© Heber Ltd 2001, 2002

+3.3V

BA14

BD12

CLKOUT

A20

+5V

GND

A8

+3.3V

BA12

A4BA0

A1

BD2D3

U874LCX245

23456789

1817161514131211

191

20

10

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

G-DIR

VC

CG

ND

PP256Probe Point

D[0..15]3

A22

GND

D13

PP245Probe Point

A1

A16

D5

A14

BD14

ROM_CE1-

ABUFEN-

PP253Probe Point

GND

A7

A11

D15

D11

FPGA4

BRW-

CS3-

A10

A16

A8

D14

SIZ1

A10

BD0D0

SIZ0 4

A17

D4

DSACK0

PP255Probe Point

+5V

GND

BA17

P3A

DIN 48_ABC-R

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

+3.3V

GND

A20

BD4

R2

OMIT

BD8

A3

D8

R4

OMIT

PP244Probe Point

DBUFEN- 4

BA2

BD11

A23

PP252Probe Point

AS-

A3

A22

BD5

RW- 4

BA22

A[0..23]3

BA19

A18

A18

A2

D6

BD[0..15]3,4

DS-

A18

D2

ROM_P1FPGA3

A16

N2

10K*8

123456789

A14

A11

D12

D14

P2A

DIN 48_ABC-R


P1B

DIN 48_ABC-R


BD9

P3B

DIN 48_ABC-R


D10

U374LCX245

23456789

1817161514131211

191

20

10

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

G-DIR

VC

CG

ND

+12V

BA15

SIZ0

P2C

DIN 48_ABC-R


+3.3V

GND

A19

BD10

A5

CS3- 4

BA7

BD14

D15

D10

D8

P1A

DIN 48_ABC-R


C3

100n

A13

D1

AS-

C2

100n

ROM_P1 4

+3.3V

INT_IDE

A0

U574LCX245

23456789

1817161514131211

191

20

10

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

G-DIR

VC

CG

ND

INT_IDE 4

A[0..23]

ROM_CE1- 4

A4

ROM_CE2-

D10

PP248Probe Point

GND

A21

A12

Page 13



GND

D15

U6

74HCT04P

1359

1113

24681012

7 14

1A2A3A4A5A6A

1Y2Y3Y4Y5Y6Y

GND VCC

GND

D3

CS0-

ROM2_OE-

+5V

D1

DIOW- 4

BD[0..15] 2,4

+5V

DIOW-

CTS

A7

PP226

Probe Point

PP230

Probe Point

IDE Keypin

A15

BD15

A[0..23] 2

DA2

D14

A11

CS1-

GND

D4

IDE_RESET-

PP231

Probe Point

P5

PLUG 9W D

594837261

PP2

Probe Point

RESET-2

BYTE/A21

U1

M27C800/160/322

109876543

414039383736353433

21

4232

14161820232527291517192124262830

1113

22

3112

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18

(A19)BYTE-/A20

D0D1D2D3D4D5D6D7D8D9

D10D11D12D13D14

A-1/D15

CE-OE-

VCC

VSSVSS

PDIAG

C11

100n

ROM2_OE-4ROM1_OE-

A10

L1

FERRITE BEAD

IDE_RESET-

PP232

Probe Point

RTS-4

RXD

D5

DA0

C9

100n

D2

A9

L2

FERRITE BEAD

A17

DASP-

+5V

BD3

INTRQ 4

A12

PP229

Probe Point

TXD-

C8

100n

BD2

TXD-4

A9

PP227

Probe PointGND

D12

IDE CONNECTOR

A13

TXD

R12K7

A17

A6

D2

D10

D[0..15] 2

DA0 4

A19

A5

BD[0..15]

A2

A13

© Heber Ltd 2001, 2002

D9

BD10

GND

GND

BD0

RXD-4

D6

D0

A14

A18

+5V

A2

A15

GND

CS1- 4

C7

100n

A4

D14

DIOR-

RTS

D0

A8

BD1

DA1 4

D1

BD5

INTRQ

L4

FERRITE BEAD

D4

IORDY

CTS-4

A3

C10

100n

GND

RESET

PP233

Probe Point

PP224

Probe Point

BYTE/A214

D8

GND

A1

BYTE/A21

D12

A[0..23]

BD12

PP228

Probe Point

D11D10

A7

CS0- 4

BD9

+5V

D7

RTS-

GND

D15

BD13

RESET-

GND

C4

100n

A10

A6

IOCS16- 4

16318 5


Heber Ltd


A3


Title


Date: Sheet of

D8

A3

A12

GND

PP223

Probe Point

A19

A4

BD8

PP222

Probe Point

IORDY 4

+5V

D6

A11

L3

FERRITE BEAD

DIOR- 4

GND

D3

D7

RXD-

D11

ROM1_OE-4

A1

A8

GNDDMARQ

A18

D[0..15]

A20

U9

MAX232A - NARROW SOIC

13

14

8

7

12

11

9

10

1

3

4

5

26

16

15

RX1

TX1

RX2

TX2

DO1

DI1

DO2

DI2

C1+

C1-

C2+

C2-

V+V-

VC

CG

ND

D5

A16

BD14

C12

100n

BD4

D13D13

BD6

DA2 4

GND

IOCS16-

P4

HEADER 40W

12345678910111213141516171819202122232425262728293031323334353637383940

U2

M27C800/160/322

109876543

41403938373635343321

4232

14161820232527291517192124262830

1113

22

3112

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18

(A19)BYTE-/A20

D0D1D2D3D4D5D6D7D8D9

D10D11D12D13D14

A-1/D15

CE-OE-

VCC

VSSVSS

PSYNC:CSEL

BD11

+5V

D9

A5

DA1

GND

A14

CTS-

RESET

A20

BD7

PP225

Probe Point

A16

DMACK-

Page 14



GND

GND

XWE2

SIZ02

CS1-

GD23

+3.3V

BD0

GD25

GD27

+3.3V

DBUFEN-2

ROM1_OE-3

XWE3 5

GD15

ROM_CE3-

BD7

DSACK0

GD11

XBS

DA1

TXD-

+3.3V

XWE1

DA1

DIOW-

PP16Probe Point

RST/OE

INT_IDEGD20

GD16

BA16

ROM_CE2-2

XBS 5

CS3-

BA20

LDC-

PP17Probe Point

IORDY3

BD12

GD[0..31] 5

XRESETPP18Probe Point

XWE0 5

+3.3V

LDC-

AS-DS-2

GD0

+3.3V

ROM2_OE-

INT_VIDEO

XINT 5

GND

BD1

PP48 Probe Point

GND

GD26

CS0-3

BD[0..15]

C17

100n

One per VCC

ROM_CE4-

DA2

RXD-

RST/OE

GD10

RXD-3

DSACK02

GND

BYTE/A21

XWE1 5

IOCS16-

C19

100n

GA24

PP50Probe Point

PCLK

+3.3V

DIOR-

GND

GD13GD14

INT_IDE2

16.77MHz CPU Clock

GD4

BA0

C16

100n

RST/OE5

BA[0..23]

IORDY

ROM_CE2-

PP56

Probe Point

XWE2 5

TXD-

DONE

N3

10K*8

123456789

U10

XCS10XL/TQ144

1

144

234567

910111213141516

1920212223242526

282930313233

1718

27

3534

8

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

737475767778798081828384858687888990919293949596979899100101102103104105106107108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

GND

VC

C

IO/GCK1IOIOIOIO/TDIIO/TCK

IOIOIO/TMSIOIOIOIOIO

IOIOIOIOIOIOIOIO

IOIOIOIOIOIO/GCK2

GNDVCC

GND

GNDM1

GND

M0

VC

CP

WR

DW

N-

IO/G

CK

3IO

/HD

CIO IO IO IO

/LD

C-

GN

DIO IO IO IO IO IO IO IO

/INIT

-V

CC

GN

DIO IO IO IO IO IO IO IO G

ND

IO IO IO IO IO IO/G

CK

4G

ND

DO

NE

VCCPROG-IO/D7

IO/GCK5IOIO

IO/D6IO

GNDIOIO

IO/D5IOIOIO

IO/D4IO

VCCGND

IO/D3IOIOIO

IO/D2IOIOIO

GNDIO/D1

IOIOIO

IO/D0/DINIO/GCK6/DOUT

CCLKVCC

O/T

DO

GN

DIOIO

/GC

K7

IOIOIO

/CS

1IONC

GN

DIOIOIOIOIOIOIOIOG

ND

VC

CIOIOIOIOIOIOIOIOG

NDIOIOIOIOIO

IO/G

CK

8

DA13

BD10

C20

100n

IOCS16-3

C13

100n

RW-2

© Heber Ltd 2001, 2002

PWRDWN-

PP13Probe Point

GD17

GD2

XRESET 5

GND

GD18

MEM_BRD-

BA3

MEM_BRD-2

GD22

+3.3V

ABUFEN-

RW-

ROM_CE4-

C18

100n

INTRQ3

BRW-2

CS0-

N6

10K*8

123456789

+3.3V

XWE0 GD6

PP257Probe Point

CCLK

DS-

DSACK1

RESET-

PP1Probe Point

INT_VIDEO2

CS3-2

+3.3V

BD2

GD9

SIZ1

GND

GND

FPGA5

PP52Probe Point

GND

BD13

GA23

+3.3V

CS1-3

PCLK 5

IORDY

DA2

ROM_CE4-2

GND

GND

C14

100n

DBUFEN-

C15

100n

GD24

C21

100n56-16318 5


HEBER LTD.

Belvedere Mi llChalford, Stroud, GL6 8NTTel: +44 (0) 1453 886000Fax: +44 (0) 1453 885013

A3

4 7Thursday, April 04, 2002

Title


Date: Sheet of

BD9

N5

10K*8

123456789

GA[23..24] 5

ABUFEN-

GD12GND

GD21

GD3

ROM_CE1-2

CTS-

ROM_CE3-2

GND

XRDY

GD7

CCLK

BD3

ROM1_OE-

U11

XC17S10XL

1

23

46

587

DATA

CLKRST/OE

CENC

GN

DV

CC

VP

P

DA03

BYTE/A213

BD11

+3.3V

GD1

DIOW-3

TXD-3

+3.3V

BA22

XCS 5

GND

XINT

GA[23..24]

GD19

N4

10K*8

123456789

IOCS16-

RTS-

GD29

GND

+3.3V

BD15

GA24

XCS

MEM_BRD-

BD[0..15] 2,3

ROM2_OE-3

CLKOUT2

BRW-

GD5

BA23

RTS-

BA18

+3.3V

BD8

SIZ0

CS0-

BD14

+3.3V

CTS-3

ROM_P12

+3.3V

BYTE/A21

XWE3

DATA

AS-2

+3.3V

BD4

INT_VIDEO

XRD 5

GND

GND

ROM_CE1-

CLKOUT

DIOW-

GD28

FPGA52

DA0

+3.3V

DBUFEN-

GA23

BA2

RESET-2

INTRQ

XRD

GD30

ROM1_OE-

+3.3V

ROM_CE3-

DSACK12

BA[0..23]2

CS1-

GD31

BA21

GD8

+3.3V

INT_IDE

BA1

+3.3V

BD5BD6

DA23

XRDY 5

DATA

PP240 Probe Point

DIOR-3

SIZ12

GND

RTS-3

GND

ROM2_OE-

DA0

GD[0..31]

DIOR-

ROM_P1

ABUFEN-2

GND

Page 15



XRESET

MDQM0

PP113Probe Point

PP155Probe Point

PP198Probe Point

+2.5V_A

GND

MD37

MD60

PP149Probe Point

PP123Probe Point

C56

100n

PP195Probe Point

+3.3V

GND

GD23

MD5

BA5

PP105Probe Point

PP75Probe Point

PP79Probe Point

PP124Probe Point

PP112Probe Point

PP129Probe Point

MD24

MD54

PP148Probe Point

C8222p

MCLKI

+3.3V

GND

GND

GND

MA4

MA11

MA8

C64220p

PP144Probe Point

+2.5V

GND

+3.3V

MD9MD8

PP205 Probe Point

R35390R

PP61Probe Point PCLK4

BA11

MDQM6

MD[0..63]

MD60

GD28

PP78Probe Point

C8122p

R23 33R

C46

100n

GD4

MD30

GD0

BA21

PP65Probe Point

GND

MD10

MD63

MD47

GD1

C53

100n

C51

100n

PP73Probe Point

BA8

BA17

PP77Probe Point

C47

100n

GND

TEST2

C52

100n

C50

100n

XRDY4

CREMSON

MA5

MA11

MD4

BA0

GND

XWE3

BA2

MD23

MD35C45

100n BA[0..23]2

GND

BA3

MCLKI

PP152Probe Point

R18390R

R20470R

C39

100n

+3.3V

BA12

MD15

MD46

C61100n

GND

BA6

MDQM4

MD7

MD4

MD55

GD14PP94Probe Point

C62100n

+2.5V

+3.3V

GD11

MD27

GD30

BA20

PP181Probe Point

PP165Probe Point

PP203 Probe Point

SDRAM

+2.5V_A

MA5

MD20

GD11

PP64Probe Point

PP187Probe Point

PP70Probe Point

L5

INDUCTOR

PP192Probe Point

BA5

MDQM4

MD39

PP207Probe Point

PP132Probe Point

PP140Probe Point

R7220K

+2.5V

GND

GND

BA21

S

MD18

BA7

PP166Probe Point

PP199 Probe Point

C35

100n

PP170Probe Point

D1BAV99

12

3

+2.5V

MD40PP139Probe Point

PP186Probe Point

BA10

GD12

L70.1uH

PP243Probe Point

PP178Probe Point

XWE14 MA3

MD31

PP197 Probe Point MDQM[0..7] 6

GA24

MD39

PP90Probe Point

D2BAV99

12

3

MWE- 6

Note:TracksignalMCLK asfollows:

GND

GND

MD3

MD29

MD57

XRDY

PP97Probe Point

PP141Probe Point

GD13

GD26

GD22C40

100n

PP116Probe Point

PP188Probe Point

XCS

MDQM5

MD15

MD17

BA2

GD5

PP128Probe Point

C57

100n

C30

100n

+3.3V

GD6

BA9

TEST3

MD24

MD43

PP183Probe Point

+3.3V

MD13

MA0

BA1

RED

GND

MD0

PP179Probe Point

C42

100n

R9OMIT

PP67Probe Point

"Daisy chain"

56-16318 5


Heber Ltd


A2


Title


Date: Sheet of

GND

MD1

MD14

MD56

MD19

MD37

PP122Probe Point

GD5

XRD

R192K7

PP143Probe Point

MD61

C41

100n

C8322p

MA[0..13]

MD59

MD56

PP84Probe Point

D7BAV99

12

3

PP150Probe Point

+2.5V

GND

MD12

GD2

BA13

C63220p

PP72Probe Point

PP156Probe PointPP154Probe Point

+2.5V

MD32

BA8

GD15

PP135Probe Point

PP194Probe Point

PP206Probe Point

PP89Probe Point

R22 33R

R13220R

C44

100n

MRAS- 6

GD26

MA8

MDQM7

MD52

MD22

PP93Probe Point

C54

100n

C49

100n

C8522p

U13

14.31818MHz SM4

4

3

2

1 VC

C

OUT

GN

D

E/D

XINT

TEST5

MDQM7

MD11

PP134Probe Point

PP177Probe Point

PP120Probe Point

GA[23..24]

MA13

MD2

MD13

BA3

PP59Probe Point

GND

BA14

C48

100n

C60100n

MCAS- 6

GND

MD51

PP202Probe Point

MCKE

C8422p

PP180Probe Point

PP92Probe Point

PP137Probe Point

XINT4

GND

MD34

MD26

PP189Probe Point

C36

100n

PP101Probe PointGD14

MCLKO

MD54

GD24

PP146Probe Point

MD55

GD25

BA12

PP119Probe Point

MA[0..13] 6

+3.3V

GND

GND

GND

GND

MD35

MD30

GD3

PP100Probe Point

+2.5V

GND

MD41

+3.3V

GD21

PP71Probe PointR10OMIT

PP118Probe PointGD22

BA19

MD38

BA23

U12

Cremson

170163209164161

456789

1011121317181920212223252627282930343536373839404142

181182183184185186189190191192193194195196197198201202203204205206208

169173174177178179180

32

175176

1

166167168210240115

238239

223218214227216212

226225

228229

232231230

233237

4445464751525354555657585960616263646869707172737476777879808182121122123124125126127128129130134135136137138139140141143144145146147148149152153154155156157158

9394959697100101102103104105106107108

86878889117118119120

909192109110114

14

31

48

65

83

98

111

131

150

234

16

33

50

67

85

113

133

160

172

188

200

236

162

213

217

220

224

15

24

32

43

49

66

75

84

99

112

116

132

142

151

159

171

187

199

207

235

165

215

219

221

222

BCLKICLKCKMSXRESET

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31

A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24

XBSXCSXRDXWE0XWE1XWE2XWE3XRDYDREQDRACKDTACKXINT

TEST0TEST1TEST2TEST3TEST4TEST5

MODE0MODE1

AOUTRAOUTGAOUTBACOMPRACOMPGACOMPB

VREFVR0

EOGV

HSYNCVSYNCCSYNC

DCLKODCLKI

MD0MD1MD2MD3MD4MD5MD6MD7MD8MD9

MD10MD11MD12MD13MD14MD15MD16MD17MD18MD19MD20MD21MD22MD23MD24MD25MD26MD27MD28MD29MD30MD31MD32MD33MD34MD35MD36MD37MD38MD39MD40MD41MD42MD43MD44MD45MD46MD47MD48MD49MD50MD51MD52MD53MD54MD55MD56MD57MD58MD59MD60MD61MD62MD63

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9

MA10MA11MA12MA13

MDQM0MDQM1MDQM2MDQM3MDQM4MDQM5MDQM6MDQM7

MRASMCASMWE

MCKEMCLKOMCLKI

VD

DH

1V

DD

H2

VD

DH

3V

DD

H4

VD

DH

5V

DD

H6

VD

DH

7V

DD

H8

VD

DH

9V

DDH

10

VD

DL1

VD

DL2

VD

DL3

VD

DL4

VD

DL5

VD

DL6

VD

DL7

VD

DL8

VD

DL9

VD

DL

10

VD

DL

11

VD

DL

12

AV

DVC

O

AV

D1A

VD2

AV

D3A

VD4

VS

S1

VS

S2

VS

S3

VS

S4

VS

S5

VS

S6

VS

S7

VS

S8

VS

S9

VS

S10

VS

S11

VS

S12

VS

S13

VS

S14

VS

S15

VS

S16

VS

S17

VS

S18

VS

S19

VS

S20

AV

S1

AV

S2

AV

S3

AV

S4

AV

S5

XWE1

MDQM0

MA2

MD43

MD6

MD16

MD20

MD45

MD62

PP66Probe Point

PP136Probe Point

+3.3V

+3.3V

GND

MWE-

MA2

MDQM5

MD27

+2.5V

GD31

MD7

BLUE

PP211 Probe Point

PP176Probe Point

C34

100n

GD20

MDQM1

MA13

MD10

MD52

PP172Probe Point


XCS4

MD62

GD10

R610K

PP212 Probe Point

C55

100n

PP117Probe Point

GND

TEST1

MD11

BA9

BA4

PP167Probe Point

XWE04

GA23

BA18

MD9

MD6

GD17

PP109Probe Point

PP147Probe Point

PP96Probe Point

C43

100n

MD41

PP74Probe Point

RST/OE4

XWE0

BA11

+3.3V

GND

BA7

MDQM6

MD42

MD58

PP76Probe Point

+3.3V

GD17

MD33

PP163Probe Point

PP173Probe Point

C58

100n

BA4

PP99Probe Point

PP174Probe Point

GND

+3.3V

MD3

MD45

MD59

PP103Probe Point

+2.5V

GND

GND

GD25

MA12

MD51

MD58

PP142Probe Point

GD28

MD53

GD4

GD23

L80.1uH

PP204Probe Point

L90.1uH

R4

+2.5V_A

MD22

BA18

GD7

PP85Probe Point

PP138Probe Point

MCLK 6

R15, R16 & R17 NORMALLY OMITTED.IF FITTED, REDUCE VALUE OF R19 TO INCREASEDRIVE CURRENT TO COMPENSATE.

GND

GD27MD34

R1575R

PP126Probe Point

GD[0..31]4

+3.3V

GND

GD7

MD28

XWE34

+2.5V

MA9

GD19

PP242Probe Point

MCAS-

MA3

MDQM3

MD29

MODE0

PP196Probe Point

R12390R

PP169Probe Point

GD24

MA9

MD17

MD5

MD44

MD16

VSYNC

PP164Probe Point

PP153Probe Point

GND

TEST0

MD46

C32220P

PP168Probe Point

MD[0..63] 6

+3.3V

BA16

MA1

MD26

PP162Probe Point

PP86Probe Point

© Heber Ltd 2001, 2002

MA0

MD18

MD48

GD8

PP121Probe Point

PP68Probe Point

GD9

GD31

BA6

C33

100n

PP114Probe Point

+2.5V_A

GND

GND

MD28

BA22

PP241Probe Point

PP130Probe Point

+3.3V

+3.3VN7

10K*8

123456789

PP182Probe Point

GD2

MA1

MD63

PP171Probe Point

GND

GND

GND

MD8

BA17

PP190Probe Point

PP125Probe Point

GND

MA4

MD31

PP115Probe Point

R1775R

PP62Probe Point

PP110Probe Point

+3.3V

GD0

MDQM3

MA10

MD21

MD0

PP127Probe Point

XRESET4

R5

MA7

MD21

PP157Probe Point

GND

GD3

GD8

MD57

MD49

N8

10K*8

12 3 4 5 6 7 8 9

PP60Probe Point

PP82Probe Point

+3.3V

BA13

MD1

MD50

GD16

PP158Probe Point

PP184Probe Point

D8BAV99

12

3

PP210 Probe Point

+2.5V

MA7

MDQM2

MD50

GD6

BA15

P6

CONNECTOR DB15 VGA

1728394

105

611

12

13

14

15

XWE24

MRAS-

MA6

MD33

GD9

XRDY

TEST4

MD40

C31100n

GA[23..24]4

GD16MD23

MD25

GD29

PP63Probe Point

PP80Probe Point

+3.3V

MD36

PP185Probe Point

PP107Probe Point

GND

MDQM1

MD25

MD36

R34

470R

PP191Probe Point

PP209Probe Point

GND


+2.5V

GND

GD15

GD10

MD49 PP159Probe Point

PP108Probe Point

MD48

MD61

PP95Probe Point

R14220R

D9BAV99

12

3

C37

100n

BA[0..23]

GD27

GD18

PP200Probe Point

PP87Probe Point

+3.3V

GND

+3.3V

GD[0..31]

MD38

BA10

BA16

PP106Probe Point

+2.5V

GND

GND

GD19

MD12

R11

BA22

MDQM[0..7]

PP88Probe Point

R1675R

PP160Probe Point

PP131Probe Point

XBS

MA10

BA19

C38

100n

PP145Probe Point

PP151Probe Point

XBS4

GND

GD29

MD44

MD32

GREEN

PP98Probe Point

PP193Probe Point

XRD4

+3.3V

GD18

HSYNC

MA12

MD42

MCKE 6

GND

XWE2

PP208Probe Point

PP111Probe Point

GD21

MDQM2

MA6

P7

PLUG 6W SIL

123456

PP133Probe Point

PP201 Probe Point

GND

GD30

BA15

XRESET

MD2

MD53

MD47

PP161Probe Point

MCLKO

GD1

MD14

GD20

GD12

PP175Probe Point

+3.3V

BA20

MD19

BA14

GD13

C8022p

PP91Probe Point

Page 16



MD7

MD31

MA0

+3.3V

+3.3V

MA10

MCKE

MD27

MCKE5

MA1

MA1

MCLK

MA4

C72

100n

MD30

GND

GND

MD3

MD11

MD13

MA2

MWE-

C65

100n

+3.3V

MWE-

MD[0..31]

PP217Probe Point

+3.3V

MDQM[0..3]

MD25

MA10

MWE-5

MA6

MCKE

MD21

MA5

MA5

C66

100n

GND

MCLK

C70

100n

+3.3V

MA2

© Heber Ltd 2001, 2002

MD20

C67

100n

MD14

MD6

MA8

MCAS-

MCAS-5

MCLK

MD28

MA6

GND

MA[0..13]5

MD5

MCAS-

MDQM0

C71

100n

MD8

MD24

C68

100n

GND

+3.3V

MD22

MA3

PP213Probe Point

MCKE

MA8

MD[0..31]5

MD1

U15

MB811641642A/SO

2021

2235

6122841465254

245781011134244454748505153

23242526293031323334

1539

37

38

16

1718

19

139

14274349

A13/BA1A12/BA0

A10/APA11

GNDGNDGNDGNDGNDGNDGND

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15

A0A1A2A3A4A5A6A7A8A9

DQMLDQMU

CKE

CLK

WE

CASRAS

CS

VCCVCCVCCVCCVCCVCCVCC

GND

MA3

MRAS-

MCKE

+3.3V

MA9

MRAS-

MD26

PP215Probe Point

MD4

MA11

MDQM1

MD12

MD18

MRAS-5

PP216Probe Point

MA13

MD19

GND

MCAS-

GND

MD9

MA11

+3.3VMWE-

U14

MB811641642A/SO

2021

2235

6122841465254

245781011134244454748505153

23242526293031323334

1539

37

38

16

1718

19

139

14274349

A13/BA1A12/BA0

A10/APA11

GNDGNDGNDGNDGNDGNDGND

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15

A0A1A2A3A4A5A6A7A8A9

DQMLDQMU

CKE

CLK

WE

CASRAS

CS

VCCVCCVCCVCCVCCVCCVCC

MA9

C69

100n

MD23

MCLK

MDQM[0..3]5

MA12

MD10

MCAS-

MDQM3

MD2

MD17

MA13

GND

56-16318 5


Heber Ltd


A3


Title


Date: Sheet of

+3.3V

MA0

MD29

+3.3V

GND

MD0

MA7

MA7

MCLK5

MWE-

MA[0..13]

MA12

MD16

MA4

MRAS-

MD15

PP214Probe PointMRAS-

GND

GND

MDQM2

Page 17



56-16318 5


Heber Ltd


A3


Title


Date: Sheet of

U17LM1117DT-ADJ (TO-252)

3

1

4VI

AD

J

VO

+5V

R27390R 1%

D5SM LED GREEN

PP220Probe Point

PP219Probe Point

+2.5V

C77100n

D330BQ015

PP239

Probe Point

D4SM LED GREEN

L668uH

© Heber Ltd 2001, 2002

+ C73220/16

+3.3V

+ C74220/16

+2.5V_A

R29

390R 1%

GND

+ C7810/16 TANT

R28390R

PP238

Probe Point

PP237Probe Point

+12V

D6SM LED GREEN

R24390R

+ C7610/16 TANT

+C75220/16

+5V

GND

+2.5V

U18LM1117DT-ADJ (TO-252)

31

4VI

AD

JVO

PP3

Probe Point

GND

R30390R 1%

R25390R

U16LM2595S-5.0 (TO263)

4

1

2

5

3

FB

VO

VI

ON

GN

D

C79100n

PP218Probe Point

+3.3V

R26

240R 1%

Page 18


Figure 8 - Calypso 16, Photograph

Documents

Pluto 5 Specification - Heberdownload.heber.co.uk/pdfdownloads/calypso16_um.pdf · 2014-10-28 · In a separate document, the Pluto 5 Software User Manual, Heber Document number 80-16040