Plesiochronous Plesiochronous Digital HierarchyDigital Hierarchy

PDH PDH MULTIPLEXINGMULTIPLEXING

PLESIOCHRONOUS HIGHER PLESIOCHRONOUS HIGHER ORDER DIGITAL ORDER DIGITAL MULTIPLEXINGMULTIPLEXING

PDH MUX NORTH AMERICAPDH MUX NORTH AMERICA

The 24 channel PCM system is the The 24 channel PCM system is the primary order of Digital MUX.primary order of Digital MUX.

If it is necessary to transmit more than 24 If it is necessary to transmit more than 24 channels, the system is build-up as in the channels, the system is build-up as in the “Plesiochronous Digital Hierarchy” as “Plesiochronous Digital Hierarchy” as shown in the diagramshown in the diagram

DIGITAL TRANSMISSION DIGITAL TRANSMISSION HIERARCHYHIERARCHY

TI MUX

T2 MUX

T3 MUX

T4 MUX

64kb/s

1

24 1.544 Mb/s

Four 1.544Mbits/s Inputs

1

4 6.312 Mbits/s

Seven 6.312inputs

1

7

274.176

Mbits/s

Six 44.736 Mbits/s inputs

1

6

DIGITAL MUX LEVELS IN North America, Europe, JapanDIGITAL MUX LEVELS IN North America, Europe, Japan

Digital MUX Digital MUX LevelLevel

No.of 64Kb/s No.of 64Kb/s ChannelsChannels

North America North America

Mbits/sMbits/s

Europe Europe Mbits/sMbits/s

Japan Mbits/sJapan Mbits/s

00 11 0.0640.064 0.0640.064 0.0640.064

11 2424 1.5441.544 1.5441.544

3030 2.0482.048

4848 3.1523.152 3.1523.152

22 9696 6.3126.312 6.3126.312

120120 8.4488.448

33 480480 34.36834.368 32.06432.064

672672 44.37644.376

13441344 91.05391.053

14401440 97.72897.728

44 19201920 139.264139.264

40324032 274.176274.176

57605760 397.200397.200

PDH MUXPDH MUX

Four primary systems (24-channle each) Four primary systems (24-channle each) are combined, multiplexed, to form an are combined, multiplexed, to form an output having 96 channels. This is called output having 96 channels. This is called the second order of multiplexing. Seven 96 the second order of multiplexing. Seven 96 channel systems can be multiplexed to channel systems can be multiplexed to give an output of 672- channels (Third give an output of 672- channels (Third order of Multiplexing). Six 672 – channels order of Multiplexing). Six 672 – channels systems are multiplexed to give an output systems are multiplexed to give an output of 4032 channels (fourth order) of 4032 channels (fourth order)

Second Order (DS2)PDH Second Order (DS2)PDH MUX(1.544 to 6.312 Mb/s)MUX(1.544 to 6.312 Mb/s)

The 6.312-Mb/s output of a second order (The 6.312-Mb/s output of a second order (DS2DS2) ) Multiplexer is created by multiplexing four first Multiplexer is created by multiplexing four first order (order (DS1DS1) multiplexing outputs. This is done by ) multiplexing outputs. This is done by interleaving the bit stream of the four primary interleaving the bit stream of the four primary systems. systems.

Each individual bit stream is called the Each individual bit stream is called the ““tributary”tributary”..

The main problem to overcome in this process is The main problem to overcome in this process is the organization of the four incoming tributaries. the organization of the four incoming tributaries.

Cont---Cont--- Synchronous Digital have tributaries with the same Synchronous Digital have tributaries with the same

clock frequency, and they are all synchronized to a clock frequency, and they are all synchronized to a master clock. master clock.

Plesiochronous Digital Mutiplexers are have tributaries Plesiochronous Digital Mutiplexers are have tributaries that have the same nominal frequency (that means that have the same nominal frequency (that means there can be small difference from one to another), but there can be small difference from one to another), but they are not synchnronized to each other. they are not synchnronized to each other.

For synchronous case, the pulses in each tributary all For synchronous case, the pulses in each tributary all rise and fall during the same time interval.rise and fall during the same time interval.

For the PDH, the rise and fall time of the pulses in For the PDH, the rise and fall time of the pulses in each tributaries do not coincide with each other.each tributaries do not coincide with each other.

PDH EuropePDH Europe

30 ch2.048 Mb/s

120 ch8.44Mb/s

480 ch34.368

Mb/s

1920 ch139.264

Mb/s

7680 ch564.992Mbit/s

64 kbits/s

x30x4

x4x4

x4

Europe

InterleavingInterleaving

The multiplexing of several tributaries can The multiplexing of several tributaries can be achieved by eitherbe achieved by either

Bit by bit multiplexing (bit interleaving)Bit by bit multiplexing (bit interleaving) Word by word multiplexing (byte Word by word multiplexing (byte

interleaving)interleaving)

BIT INTERLEAVINGBIT INTERLEAVING

There are four bit streams to be There are four bit streams to be multiplexed. One bit is sequentially taken multiplexed. One bit is sequentially taken from each tributary so that the resulting from each tributary so that the resulting multiplexed bit stream has every fifth bit multiplexed bit stream has every fifth bit coming from the same tributary. A specific coming from the same tributary. A specific no. of bits (usually 8), forming a word, are no. of bits (usually 8), forming a word, are taken from each tributary in turn. taken from each tributary in turn.

Byte InterleavingByte Interleaving

Byte interleaving sets some restraints on Byte interleaving sets some restraints on the frame structure of the tributaries and the frame structure of the tributaries and require great amount of memory capacity.require great amount of memory capacity.

Bit interleaving is much simpler because it Bit interleaving is much simpler because it is independent of frame structure and also is independent of frame structure and also requires less memory capacity. requires less memory capacity.

PDH featuresPDH features

Bit interleaving is used for North American Bit interleaving is used for North American and European PDH system. A typical 6.312 and European PDH system. A typical 6.312 Mb/s plesichronous multiplexer has four Mb/s plesichronous multiplexer has four primary (DS1) MUX, each having an out put primary (DS1) MUX, each having an out put of 1.544 Mb/s, bit interleaved to form the next of 1.544 Mb/s, bit interleaved to form the next level in hierarchy.level in hierarchy.

Note that this output rate of 6.312 Mb/s is not Note that this output rate of 6.312 Mb/s is not exactly four times the tributary bit rate of exactly four times the tributary bit rate of 1.544 Mb/s. This is a result of the non-1.544 Mb/s. This is a result of the non-sychronous nature of the system.sychronous nature of the system.

PDH FeaturesPDH Features

Every tributary has its own clock. Every tributary Every tributary has its own clock. Every tributary is timed with plesiochronous frequency, that is a is timed with plesiochronous frequency, that is a nominal frequency about which the shifts around nominal frequency about which the shifts around it within prefixed limits. For example, the primary it within prefixed limits. For example, the primary multiplexer output is 1.544 Mb/s +- 50ppm.multiplexer output is 1.544 Mb/s +- 50ppm.

To account for the small variations of the To account for the small variations of the tributaries frequencies about the nominal value tributaries frequencies about the nominal value when multiplexing four tributaries to the next when multiplexing four tributaries to the next hierarchy level, a process known as positive hierarchy level, a process known as positive stuffing (also known as positive justification) is stuffing (also known as positive justification) is used.used.

Positive Pulse stuffing or Positive Pulse stuffing or justificationjustification

Pulse stuffing involves intentionally making the Pulse stuffing involves intentionally making the output bit rate of a channel higher than the input output bit rate of a channel higher than the input rate. The output channel therefore contains all rate. The output channel therefore contains all the input data plus a variable number of “stuffed the input data plus a variable number of “stuffed bits’ that are not part of the incoming subscriber bits’ that are not part of the incoming subscriber information.information.

The stuffed bits are inserted at the specific The stuffed bits are inserted at the specific locations, to pad the input bit stream to the locations, to pad the input bit stream to the higher output bit rate. This stuffed bits must be higher output bit rate. This stuffed bits must be identified at the receiving end so that “de-identified at the receiving end so that “de-stuffing” can be done to recover the original bit stuffing” can be done to recover the original bit stream. stream.

Cont---Cont---

Pulse stuffing is used for higher order Pulse stuffing is used for higher order multiplexing when each of the incoming multiplexing when each of the incoming lower order tributary signal is lower order tributary signal is unsynchronized, and therefore bears no unsynchronized, and therefore bears no prefix phase relationship to any of the prefix phase relationship to any of the other.other.

The situation is vividly depicted in fig.The situation is vividly depicted in fig.

BIT INTERLEAVINGBIT INTERLEAVING

BYTE INTERLEAVINGBYTE INTERLEAVING

Word by Word MULTIPLEXING

BIT INTERLEAVINGBIT INTERLEAVING SIMPLIFIED SDH MULTIPLEXINGSIMPLIFIED SDH MULTIPLEXING

SYNCHRONOUS BYE INTERLEAVING SYNCHRONOUS BYE INTERLEAVING

(No Stuffing needed)(No Stuffing needed)

HIGR ORDER MULTIPLEXER

Simplified PDH bit interleavingSimplified PDH bit interleaving(Stuffing Needed)(Stuffing Needed)

-- --Higher Order

Multiplexer

11

Frame no.1 Frame no: 2

Lower Bit Rate

Higher Bit Rate

Stuffing Control bit Stuffing

bit is a data bit

Stuffing bit is a stuff bit

De-stuffing at Receive sideDe-stuffing at Receive side At the receiving end the writing clock has the same At the receiving end the writing clock has the same

characteristics as those of the transmit reading clock. characteristics as those of the transmit reading clock. That is, it has a frequency that is on average the same That is, it has a frequency that is on average the same as that of the tributary, but it presents periodic spaces as that of the tributary, but it presents periodic spaces for the frame structure and random spaces for the for the frame structure and random spaces for the stuffing process. A phase lock loop (PLL) circuit is stuffing process. A phase lock loop (PLL) circuit is used to reduce,used to reduce,

Jitter caused by the frame structure Jitter caused by the frame structure Higher frequency jitter components (waiting time) Higher frequency jitter components (waiting time)

caused by stuffing caused by stuffing Tributary signal jitterTributary signal jitter Jitter introduced by the 6.312 Mb/s link.Jitter introduced by the 6.312 Mb/s link.

PDH MUX Europe PDH MUX Europe

In summary, the positive stuffing method involves In summary, the positive stuffing method involves the canceling of a clock pulse assigned to a the canceling of a clock pulse assigned to a particular tributary in some of the frames in order to particular tributary in some of the frames in order to coordinate the timing of the plesiochronous coordinate the timing of the plesiochronous tributaries into a multiplexed output. Random tributaries into a multiplexed output. Random spaces are therefore created in the frame, as well spaces are therefore created in the frame, as well as periodic spaces. In the periodic spaces frame as periodic spaces. In the periodic spaces frame alignment word bits service bits, and stuffing control alignment word bits service bits, and stuffing control bits are inserted. The tributary information bits are bits are inserted. The tributary information bits are inserted in the random spaces in the absence of inserted in the random spaces in the absence of stuffing, or logic 1 is used when stuffing taken stuffing, or logic 1 is used when stuffing taken place. Remember, the stuffing pluses carry no place. Remember, the stuffing pluses carry no subscriber information. subscriber information.

PDH ENDPDH END

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