Pipeline Processor Design Project Pipeline Processor Design Project Jarred Beck

Design AssumptionsDesign Assumptions

• Three bit opcode• This is to be able to address all of the 8k

memory directly. 213 = 8192

• 16 registers with some limitations• In certain formats, only the first 8 are able to

reached

• Two reserved registers for the lw and sw.

Design Assumptions Cont. Design Assumptions Cont.

• Pipeline Data Path Structure• Ease of testability. (theoretically)

• Fast.

• Compiler responsibility’s• Hazard Prevention.

• Lw and Sw data moving.

• Jump return.

Register List Register List Register Register # Description

$zero 0 Holds constant zero value$a0 1 Holds an argument value$a1 2 Holds an argument value$a2 3 Holds an argument value$t0 4 Holds an argument value$t1 5 Holds a temporary value$s0 6 Holds a saved value $lr 7 Last value loaded from memory$sr 8 Last value stored into memory$s0 9 Holds a saved value$s1 10 Holds a saved value$t2 11 Holds a saved value$t3 12 Holds a saved value$ra 13 Holds the return

Instruction SetInstruction SetInstruction Set Formats

Inst. Type Format

  Opcode Result Reg. Argument 1Argument

2 ALU Op

Arithmatic (A) XXX XXXX XXXX XXX XX

           

  OpcodeCompare

Reg. 1Compare Reg.

2 DirectionBranch Offset

Branch (Br) XXX XXX XXX X XXXXXX

           

  Opcode Address

Jump (J) XXX XXXXXXXXXXXXX

           

  Opcode Address

Memory (M) XXX XXXXXXXXXXXXX

Instruction Set Cont.Instruction Set Cont.

Opcode Instructions 

Arithmatic**Jump (J)

Load Word (Lw)Store Word (Sw)

NopHltBeq

Bneq 

** has sub opcodes

InstructionsAddSubAndOr

BeqBneq

jlwswhltnop

Control UnitControl Unit

• 11 bits wide.

• Controls include• Branch Flags

• Jump Flag

• Data Memory Read and Write Flags

• Register Write Flag

• Mux controls for Memory Input, Register Input, and

Register Address

Control Unit Cont.Control Unit Cont.Opcode

InstructionsControl Pattern

   

Arithmatic** 00000001100

Jump (J) 10000000101

Load Word (Lw) 00100101100

Store Word (Sw) 00011000100

Nop 00000000100

Hlt 00000000000

Beq 01000000110

Bneq 00000010110

Control Bit Function10 Jump Flag9 BEQ Flag8 Data Read7 Data Write6 Data Select

5Reg Write

Sel.4 BNEQ Flag3 Reg Write2 PC Write

1Branch Signal

0 LW Addr Sel

DatapathDatapath

Simulation ResultsSimulation Results

• Individual Components• All Components passed tests

• Datapath and CPU • Datapath Passed tests

• Control Unit Passed test

• Memory passed

• Top level CPU problems

Moving ForwardMoving Forward

• Debug Top level VHDL• Altera passes compilation

• ModelSim gives error

• Synthesize corrected version into board

Questions?Questions?

The End