PIC16F1509

PIC16(L)F1508/9

High-Performance RISC CPU: C Compiler Optimized Architecture Only 49 Instructions Up to 8 Kwords Linear Program Memory

Addressing Up to 512 bytes Linear Data Memory Addressing Operating Speed:

- DC 20 MHz clock input- DC 200 ns instruction cycle

Interrupt Capability with Automatic Context Saving

16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset

Direct, Indirect and Relative Addressing modes:- Two full 16-bit File Select Registers (FSRs)- FSRs can read program and data memory

Flexible Oscillator Structure: 16 MHz Internal Oscillator Block:

- Factory calibrated to 1%, typical- Software selectable frequency range from

16 MHz to 31 kHz 31 kHz Low-Power Internal Oscillator Three External Clock modes up to 20 MHz

Special Microcontroller Features: Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF1508)- 2.3V to 5.5V (PIC16F1508)

Self-Programmable under Software Control Power-On Reset (POR) Power-up Timer (PWRT) Programmable Low-Power Brown-Out Reset

(LPBOR) Extended Watchdog Timer (WDT):

- Programmable period from 1 ms to 256s Programmable Code Protection In-Circuit Serial Programming (ICSP) via Two

Pins Enhanced Low-Voltage Programming (LVP) In-Circuit Debug (ICD) via Two Pins Power-Saving Sleep mode:

- Low-Power Sleep mode

Extreme Low-Power Managementwith XLP (PIC16LF1508/9): Standby Current:

- 20 nA @ 1.8V, typical Watchdog Timer Current:

- 260 nA @ 1.8V, typical Operating Current:

- 30 A/MHz @ 1.8V, typical Secondary Oscillator Current:

- 700 nA @ 32 kHz, 1.8V, typical

Peripheral Features: Analog-to-Digital Converter (ADC):

- 10-bit resolution- 12 external channels- Three internal channels:

- Fixed Voltage Reference- Digital-to-Analog Converter (DAC)- Temperature Indicator channel

- Auto acquisition capability- Conversion available during Sleep

5-Bit Digital-to-Analog Converter (DAC):- Output available externally- Positive reference selection- Internal connections to comparators and ADC

Two Comparators:- Rail-to-rail inputs- Power mode control- Software controllable hysteresis

Voltage Reference:- 1.024V Fixed Voltage Reference (FVR) with

1x, 2x and 4x Gain output levels 18 I/O Pins (1 Input-only Pin):

- High current sink/source 25 mA/25 mA- Individually programmable weak pull-ups- Individually programmable

Interrupt-On-Change (IOC) pins Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler Enhanced Timer1:

- 16-bit timer/counter with prescaler

20-Pin Flash, 8-Bit Microcontrollers with XLP Technology 2011-2014 Microchip Technology Inc. DS40001609D-page 1

- Low-Power BOR (LPBOR) Integrated Temperature Indicator 128 Bytes High-Endurance Flash

- 100,000 write Flash endurance (minimum)

- External Gate Input mode Timer2: 8-Bit Timer/Counter with 8-Bit Period

Register, Prescaler and Postscaler Four 10-bit PWM modules

PIC16(L)F1508/9Peripheral Features (Continued): Master Synchronous Serial Port (MSSP) with SPI

and I2C with:- 7-bit address masking- SMBus/PMBus compatibility

Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)- RS-232, RS-485 and LIN compatible- Auto-Baud Detect- Auto-wake-up on Start

Four Configurable Logic Cell (CLC) modules:- 16 selectable input source signals- Four inputs per module- Software control of combinational/sequential

logic/state/clock functions- AND/OR/XOR/D Flop/D Latch/SR/JK- Inputs from external and internal sources

- Output available to pins and peripherals- Operation while in Sleep

Numerically Controlled Oscillator (NCO):- 20-bit accumulator- 16-bit increment- True linear frequency control- High-speed clock input- Selectable Output modes

- Fixed Duty Cycle (FDC) mode- Pulse Frequency (PF) mode

Complementary Waveform Generator (CWG):- Eight selectable signal sources- Selectable falling and rising edge dead-band

control- Polarity control- Four auto-shutdown sources- Multiple input sources: PWM, CLC, NCO

PIC12(L)F1501/PIC16(L)F150X FAMILY TYPES

Device

Dat

a Sh

eet I

ndex

Prog

ram

Mem

ory

Flas

h (w

ords

)

Dat

a SR

AM

(byt

es)

I/Os

(2)

10-b

it A

DC

(ch)

Com

para

tors

DA

C

Tim

ers

(8/1

6-bi

t)

PWM

EUSA

RT

MSS

P (I2

C

/SPI

)

CW

G

CLC

NC

O

Deb

ug(1

)

XLP

PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 1 2 1 H PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 1 1 2 1 H PIC16(L)F1507 (3) 2048 128 18 12 2/1 4 1 2 1 H PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H YPIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H YNote 1: Debugging Methods: (I) - Integrated on Chip; (H) - using Debug Header; (E) - using Emulation Header.

2: One pin is input-only.Data Sheet Index: (Unshaded devices are described in this document.)

1: DS0004001615 PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.2: DS0004001607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.3: DS0004001586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.4: DS0004001609 PIC16(L)F1508/9 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.

Note: For other small form-factor package availability and marking information, please visithttp://www.microchip.com/packaging or contact your local sales office.DS40001609D-page 2 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

PIN DIAGRAMS

Pin Diagram 20-Pin PDIP, SOIC, SSOP

Pin Diagram 20-Pin QFN, UQFN

PIC

16(L

)F15

08PI

C16

(L)F

1509

1

234

14

131211

56

7

109

8

VDDRA5RA4

MCLR/VPP/RA3RC5RC4

VSSRA0/ICSPDAT

RA1/ICSPCLKRA2RC0

RC1RC2RC3

Note: See Table 1 for location of all peripheral functions.

18171615

2019

RC6

RC7RB7

RB4

RB5RB6

PIC16(L)F1508PIC16(L)F1509

Note 1: See Table 1 for location of all peripheral functions.2: It is recommended that the exposed bottom pad be connected to VSS.

15 RA1/ICSPCLK

RA2

RC0

RC1RC211

12

13

14

6 7

RC

7

RB

7

RB

4

RB

5

RB

6

8 9 10

2

3

1

181920 1617

5

4

VD

D

RA

5

RA

4

MCLR/VPP/RA3

RC5

RC4

RC3

RC6

VS

S

RA

0/IC

SP

DAT 2011-2014 Microchip Technology Inc. DS40001609D-page 3

PIC16(L)F1508/9

Bas

ic

DATAT

CLKLK

LRP

UTC2

INC1

D

SPIN ALLOCATION TABLE

TABLE 1: 20-PIN ALLOCATION TABLE (PIC16(L)F1508/9)

I/O

20-P

in P

DIP

/SO

IC/S

SOP

20-P

in Q

FN/U

QFN

AD

C

Ref

eren

ce

Com

para

tor

Tim

ers

EUSA

RT

MSS

P

CW

G

NC

O

CLC

PWM

Inte

rrup

t

Pull-

up

RA0 19 16 AN0 DAC1OUT1 C1IN+ IOC Y ICSPICDD

RA1 18 15 AN1 VREF+ C1IN0-C2IN0-

CLC4IN1 IOC Y ICSPICDC

RA2 17 14 AN2 DAC1OUT2 C1OUT T0CKI CWG1FLT CLC1 PWM3 INT/IOC

Y

RA3 4 1 T1G(1) SS(1) CLC1IN0 IOC Y MCVP

RA4 3 20 AN3 SOSCOT1G

IOC Y CLKOOS

RA5 2 19 SOSCIT1CKI

NCO1CLK IOC Y CLKOS

RB4 13 10 AN10 SDA/SDI CLC3IN0 IOC Y

RB5 12 9 AN11 RX/DT CLC4IN0 IOC Y

RB6 11 8 SCL/SCK IOC Y

RB7 10 7 TX/CK CLC3 IOC Y

RC0 16 13 AN4 C2IN+ CLC2

RC1 15 12 AN5 C1IN1-C2IN1-

NCO1 PWM4

RC2 14 11 AN6 C1IN2-C2IN2-

RC3 7 4 AN7 C1IN3-C2IN3-

CLC2IN0 PWM2

RC4 6 3 C2OUT CWG1B CLC4CLC2IN1

RC5 5 2 CWG1A CLC1(1) PWM1

RC6 8 5 AN8 SS NCO1(1) CLC3IN1

RC7 9 6 AN9 SDO CLC1IN1

VDD 1 18 VD

VSS 20 17 VS

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.DS40001609D-page 4 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

TABLE OF CONTENTSDevice Overview ................................................................................................................................................................................... 7Enhanced Mid-Range CPU................................................................................................................................................................. 12Memory Organization .......................................................................................................................................................................... 14Device Configuration........................................................................................................................................................................... 39Oscillator Module (With Fail-Safe Clock Monitor) ............................................................................................................................... 45Resets................................................................................................................................................................................................. 61Interrupts ............................................................................................................................................................................................. 69Power-Down Mode (Sleep) ................................................................................................................................................................. 82Watchdog Timer (WDT) ...................................................................................................................................................................... 85Flash Program Memory Control .......................................................................................................................................................... 89I/O Ports ............................................................................................................................................................................................ 105Interrupt-On-Change ......................................................................................................................................................................... 118Fixed Voltage Reference (FVR) ........................................................................................................................................................ 123Temperature Indicator Module .......................................................................................................................................................... 126Analog-to-Digital Converter (ADC) Module ....................................................................................................................................... 1285-Bit Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 142Comparator Module .......................................................................................................................................................................... 145Timer0 Module .................................................................................................................................................................................. 152Timer1 Module with Gate Control ..................................................................................................................................................... 155Timer2 Module .................................................................................................................................................................................. 167Master Synchronous Serial Port (MSSP) Module ............................................................................................................................. 170Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........................................................................ 225Pulse Width Modulation (PWM) Module ........................................................................................................................................... 253Configurable Logic Cell (CLC) .......................................................................................................................................................... 259Numerically Controlled Oscillator (NCO) Module .............................................................................................................................. 275Complementary Waveform Generator (CWG) Module ..................................................................................................................... 282In-Circuit Serial Programming (ICSP) ........................................................................................................................................ 294Instruction Set Summary ................................................................................................................................................................... 296Electrical Specifications .................................................................................................................................................................... 311DC and AC Characteristics Graphs and Charts ................................................................................................................................ 341Development Support ....................................................................................................................................................................... 382Packaging Information ...................................................................................................................................................................... 386Appendix A: Data Sheet Revision History......................................................................................................................................... 399The Microchip Web Site .................................................................................................................................................................... 400Customer Change Notification Service ............................................................................................................................................. 400Customer Support ............................................................................................................................................................................. 400Product Identification System ........................................................................................................................................................... 401 2011-2014 Microchip Technology Inc. DS40001609D-page 5

PIC16(L)F1508/9TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.DS40001609D-page 6 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

1.0 DEVICE OVERVIEWThe PIC16(L)F1508 are described within this data sheet.The block diagram of these devices are shown inFigure 1-1, the available peripherals are shown inTable 1-1, and the pinout descriptions are shown inTable 1-2.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC

12(L

)F15

01

PIC

16(L

)F15

03

PIC

16(L

)F15

07

PIC

16(L

)F15

08

PIC

16(L

)F15

09

Analog-to-Digital Converter (ADC) Complementary Wave Generator (CWG) Digital-to-Analog Converter (DAC) Enhanced UniversalSynchronous/Asynchronous Receiver/Transmitter (EUSART)

Fixed Voltage Reference (FVR) Numerically Controlled Oscillator (NCO) Temperature Indicator Comparators

C1 C2

Configurable Logic Cell (CLC)CLC1 CLC2 CLC3 CLC4

Master Synchronous Serial PortsMSSP1

PWM ModulesPWM1 PWM2 PWM3 PWM4

TimersTimer0 Timer1 Timer2 2011-2014 Microchip Technology Inc. DS40001609D-page 7

PIC16(L)F1508/9

FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM

OSC2/CLKOUT

OSC1/CLKIN

RAM

CPU

(Note 3)

Timing Generation

INTRC Oscillator

MCLR

Program Flash Memory

FVRDACADC10-bitTemp

IndicatorC1C2TMR0TMR1TMR2MSSP1

PWM1 EUSARTPWM2PWM3PWM4CLC1CLC2CLC3CLC4NCO1CWG1

PORTA

PORTB

PORTC

Rev. 10-000039A8/1/2013

Note 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals on specific devices.3: See Figure 2-1.DS40001609D-page 8 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/AN0/C1IN+/DAC1OUT1/ICSPDAT/ICDDAT

RA0 TTL CMOS General purpose I/O.AN0 AN ADC Channel input.

C1IN+ AN Comparator positive input.DAC1OUT1 AN Digital-to-Analog Converter output.ICSPDAT ST CMOS ICSP Data I/O.ICDDAT ST CMOS In-Circuit Debug data.

RA1/AN1/CLC4IN1/VREF+/C1IN0-/C2IN0-/ICSPCLK/ICDCLK


CLC4IN1 ST Configurable Logic Cell source input.VREF+ AN ADC Positive Voltage Reference input.C1IN0- AN Comparator negative input.C2IN0- AN Comparator negative input.

ICSPCLK ST ICSP Programming Clock.ICDCLK ST In-Circuit Debug Clock.

RA2/AN2/C1OUT/DAC1OUT2/T0CKI/INT/PWM3/CLC1/CWG1FLT

RA2 ST CMOS General purpose I/O.AN2 AN ADC Channel input.

C1OUT CMOS Comparator output.DAC1OUT2 AN Digital-to-Analog Converter output.

T0CKI ST Timer0 clock input.INT ST External interrupt.

PWM3 CMOS PWM output.CLC1 CMOS Configurable Logic Cell source output.

CWG1FLT ST Complementary Waveform Generator Fault input.RA3/CLC1IN0/VPP/T1G(1)/SS(1)/MCLR

RA3 TTL General purpose input with IOC and WPU.CLC1IN0 ST Configurable Logic Cell source input.

VPP HV Programming voltage.T1G ST Timer1 Gate input.SS ST Slave Select input.

MCLR ST Master Clear with internal pull-up.RA4/AN3/SOSCO/CLKOUT/T1G


SOSCO XTAL XTAL Secondary Oscillator Connection.CLKOUT CMOS FOSC/4 output.

T1G ST Timer1 Gate input.RA5/CLKIN/T1CKI/NCO1CLK/SOSCI

RA5 TTL CMOS General purpose I/O.CLKIN CMOS External clock input (EC mode).T1CKI ST Timer1 clock input.

NCO1CLK ST Numerically Controlled Oscillator Clock source input.SOSCI XTAL XTAL Secondary Oscillator Connection.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Alternate pin function selected with the APFCON (Register 11-1) register. 2011-2014 Microchip Technology Inc. DS40001609D-page 9

PIC16(L)F1508/9RB4/AN10/CLC3IN0/SDA/SDI RB4 TTL CMOS General purpose I/O.AN10 AN ADC Channel input.

CLC3IN0 ST Configurable Logic Cell source input.SDA I2C OD I2C data input/output.SDI CMOS SPI data input.

RB5/AN11/CLC4IN0/RX/DT RB5 TTL CMOS General purpose I/O.AN11 AN ADC Channel input.

CLC4IN0 ST Configurable Logic Cell source input.RX ST USART asynchronous input.DT ST CMOS USART synchronous data.

RB6/SCL/SCK RB6 TTL CMOS General purpose I/O.SCL I2C OD I2C clock.SCK ST CMOS SPI clock.

RB7/CLC3/TX/CK RB7 TTL CMOS General purpose I/O.CLC3 CMOS Configurable Logic Cell source output.

TX CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.

RC0/AN4/CLC2/C2IN+ RC0 TTL CMOS General purpose I/O.AN4 AN ADC Channel input.CLC2 CMOS Configurable Logic Cell source output.C2IN+ AN Comparator positive input.

RC1/AN5/C1IN1-/C2IN1-/PWM4/NCO1

RC1 TTL CMOS General purpose I/O.AN5 AN ADC Channel input.

C1IN1- AN Comparator negative input.C2IN1- AN Comparator negative input.PWM4 CMOS PWM output.NCO1 CMOS Numerically Controlled Oscillator is source output.

RC2/AN6/C1IN2-/C2IN2- RC2 TTL CMOS General purpose I/O.AN6 AN ADC Channel input.

C1IN2- AN Comparator negative input.C2IN2- AN Comparator negative input.

RC3/AN7/C1IN3-/C2IN3-/PWM2/CLC2IN0


C1IN3- AN Comparator negative input.C2IN3- AN Comparator negative input.PWM2 CMOS PWM output.

CLC2IN0 ST Configurable Logic Cell source input.RC4/C2OUT/CLC2IN1/CLC4/CWG1B

RC4 TTL CMOS General purpose I/O.C2OUT CMOS Comparator output.

CLC2IN1 ST Configurable Logic Cell source input.CLC4 CMOS Configurable Logic Cell source output.

CWG1B CMOS CWG complementary output.

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)



Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.DS40001609D-page 10 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9RC5/PWM1/CLC1(1)/CWG1A

RC5 TTL CMOS General purpose I/O.PWM1 CMOS PWM output.CLC1 CMOS Configurable Logic Cell source output.

CWG1A CMOS CWG primary output.RC6/AN8/NCO1(1)/CLC3IN1/SS


NCO1 CMOS Numerically Controlled Oscillator source output.CLC3IN1 ST Configurable Logic Cell source input.

SS ST Slave Select input.RC7/AN9/CLC1IN1/SDO RC7 TTL CMOS General purpose I/O.

AN9 AN ADC Channel input.CLC1IN1 ST Configurable Logic Cell source input.

SDO CMOS SPI data output.VDD VDD Power Positive supply.VSS VSS Power Ground reference.

TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED)



Note 1: Alternate pin function selected with the APFCON (Register 11-1) register. 2011-2014 Microchip Technology Inc. DS40001609D-page 11

PIC16(L)F1508/92.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, andRelative addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.

Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set

FIGURE 2-1: CORE BLOCK DIAGRAM

1515

15

15

8

8

8

1214

75

3

Program Counter

MUX

Addr MUX

16-Level Stack(15-bit)

Program MemoryRead (PMR)

Instruction Reg

Configuration

FSR0 Reg

FSR1 Reg

BSR Reg

STATUS Reg

RAM

W Reg

Power-upTimer

Power-onReset

WatchdogTimer

Brown-outReset

InstructionDecode and

Control

TimingGeneration

InternalOscillator

Block

ALU

FlashProgramMemoryM

UX

Data Bus

ProgramBus

Direct AddrIndirect

Addr

RAM Addr

CLKIN

CLKOUT

VDD VSS

Rev. 10-000055A7/30/2013

1212DS40001609D-page 12 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

2.1 Automatic Interrupt Context

SavingDuring interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 7.5 Automatic Context Saving,for more information.

2.2 16-Level Stack with Overflow and Underflow

These devices have a hardware stack memory 15 bitswide and 16 words deep. A Stack Overflow or Under-flow will set the appropriate bit (STKOVF or STKUNF)in the PCON register, and if enabled, will cause a soft-ware Reset. See section Section 3.4 Stack for moredetails.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.5 Indirect Addressing for more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 28.0 Instruction Set Summary for moredetails. 2011-2014 Microchip Technology Inc. DS40001609D-page 13

PIC16(L)F1508/93.0 MEMORY ORGANIZATIONThese devices contain the following types of memory:

Program Memory- Configuration Words- Device ID- User ID- Flash Program Memory

Data Memory- Core Registers- Special Function Registers- General Purpose RAM- Common RAM

The following features are associated with access andcontrol of program memory and data memory:

PCL and PCLATH Stack Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing a 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the interrupt vector is at 0004h (SeeFigure 3-1 and Figure 3-2).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words)Last Program Memory

AddressHigh-Endurance Flash

Memory Address Range (1)

PIC16LF1508PIC16F1508 4,096 0FFFh 0F80h-0FFFh

PIC16LF1509PIC16F1509 8,192 1FFFh 1F80h-1FFFh

Note 1: High-endurance Flash applies to low byte of each address in the range.DS40001609D-page 14 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR PIC16(L)F1508

FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1509

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC

Interrupt Vector

Page 1

Page 0

Rollover to Page 0

Rollover to Page 1

0000h

0004h0005h

07FFh0800h

0FFFh1000h

7FFFh

CALL, CALLW RETURN, RETLWInterrupt, RETFIE

On-chipProgramMemory

15

Rev. 10-000040A7/30/2013

CALL, CALLW RETURN, RETLWInterrupt, RETFIE

On-chipProgramMemory

Stack Level 0

Stack Level 15

Stack Level 1

Reset Vector

PC

Interrupt Vector

Page 1

Page 0

0000h

0004h0005h

07FFh0800h

0FFFh1000h

7FFFh

Rollover to Page 0

Rollover to Page 3

Page 2

Page 3

17FFh1800h

1FFFh2000h

15

Rev. 10-000040B7/30/2013 2011-2014 Microchip Technology Inc. DS40001609D-page 15

PIC16(L)F1508/9

3.1.1 READING PROGRAM MEMORY AS

DATAThere are two methods of accessing constants inprogram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table verysimple to implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available so the older table readmethod must be used.

3.1.1.2 Indirect Read with FSRThe program memory can be accessed as data by set-ting bit 7 of the FSRxH register and reading the match-ing INDFx register. The MOVIW instruction will place thelower eight bits of the addressed word in the W register.Writes to the program memory cannot be performed viathe INDF registers. Instructions that access the pro-gram memory via the FSR require one extra instructioncycle to complete. Example 3-2 demonstrates access-ing the program memory via an FSR.

The HIGH operator will set bit if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW DATA_INDEXcall constants; THE CONSTANT IS IN W

constantsRETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW LOW constantsMOVWF FSR1LMOVLW HIGH constantsMOVWF FSR1HMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN WDS40001609D-page 16 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

3.2 Data Memory OrganizationThe data memory is partitioned in 32 memory bankswith 128 bytes in a bank. Each bank consists of(Figure 3-3):

12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM

The active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as 0. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.5 IndirectAddressing for more information.Data memory uses a 12-bit address. The upper five bitsof the address define the Bank address and the lowerseven bits select the registers/RAM in that bank.

3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x08h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-2. For detailedinformation, see Table 3-8.

TABLE 3-2: CORE REGISTERS

Addresses BANKxx00h or x80h INDF0x01h or x81h INDF1x02h or x82h PCLx03h or x83h STATUSx04h or x84h FSR0Lx05h or x85h FSR0Hx06h or x86h FSR1Lx07h or x87h FSR1Hx08h or x88h BSRx09h or x89h WREGx0Ah or x8Ah PCLATHx0Bh or x8Bh INTCON 2011-2014 Microchip Technology Inc. DS40001609D-page 17

PIC16(L)F1508/9

3.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:

the arithmetic status of the ALU the Reset status

The STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section28.0 Instruction Set Summary).

Note 1: The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.

REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets1 = Bit is set 0 = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as 0bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.DS40001609D-page 18 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

3.2.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in the appro-priate peripheral chapter of this data sheet.

3.2.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section3.5.2 Linear Data Memory for more information.

3.2.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

FIGURE 3-3: BANKED MEMORY PARTITIONING

Memory Region7-bit Bank Offset

00h

0Bh0Ch

1Fh20h

6Fh

7Fh

70h

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

General Purpose RAM(80 bytes maximum)

Common RAM(16 bytes)

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PIC16(L)F1508/9

3.2Th

TABANK 6 BANK 7

00 0hCore Registers

(Table 3-2)

380hCore Registers

(Table 3-2)

00 Bh 38Bh00 Ch 38Ch 00 Dh 38Dh 00 Eh 38Eh 00 Fh 38Fh 01 0h 390h 01 1h 391h IOCAP01 2h 392h IOCAN01 3h 393h IOCAF01 4h 394h IOCBP01 5h 395h IOCBN01 6h 396h IOCBF01 7h 397h 01 8h 398h 01 9h 399h 01 Ah 39Ah 01 Bh 39Bh 01 Ch 39Ch 01 Dh 39Dh 01 Eh 39Eh 01 Fh 39Fh 02 0h

UnimplementedRead as 0

3A0h


06 Fh 3EFh07 0h

Common RAM(Accesses70h 7Fh)

3F0hCommon RAM

(Accesses70h 7Fh)

07 Fh 3FFh

Le.5 DEVICE MEMORY MAPSe memory maps for Bank 0 through Bank 31 are shown in the tables in this section.

BLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

0hCore Registers

(Table 3-2)

080hCore Registers

(Table 3-2)

100hCore Registers

(Table 3-2)

180hCore Registers

(Table 3-2)

200hCore Registers

(Table 3-2)

280hCore Registers

(Table 3-2)

30

Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 30Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 30Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 28Eh 30Fh 08Fh 10Fh 18Fh 20Fh 28Fh 300h 090h 110h 190h 210h 290h 311h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h 312h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h 313h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h 314h 094h 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h 315h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 316h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 317h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h 318h T1CON 098h 118h DAC1CON0 198h 218h 298h 319h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h 299h 31Ah TMR2 09Ah OSCSTAT 11Ah 19Ah TXREG 21Ah 29Ah 31Bh PR2 09Bh ADRESL 11Bh 19Bh SPBRG 21Bh 29Bh 31Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch 29Ch 31Dh 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh 29Dh 31Eh 09Eh ADCON1 11Eh 19Eh TXSTA 21Eh 29Eh 31Fh 09Fh ADCON2 11Fh 19Fh BAUDCON 21Fh 29Fh 310h

GeneralPurposeRegister80 Bytes

0A0h


120h


1A0h


220h


2A0h


32

0EFhFh 16Fh 1EFh 26Fh 2EFh 360h

Common RAM

0F0hCommon RAM

(Accesses70h 7Fh)

170hCommon RAM

(Accesses70h 7Fh)

1F0hCommon RAM

(Accesses70h 7Fh)

270hCommon RAM

(Accesses70h 7Fh)

2F0hCommon RAM

(Accesses70h 7Fh)

37

Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37

gend: = Unimplemented data memory locations, read as 0.

PIC16(L)F1508/9

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BANK 6 BANK 7

300h

Core Registers (Table 3-2)

380hCore Registers

(Table 3-2)

30Bh 38Bh30Ch 38Ch 30Dh 38Dh 30Eh 38Eh 30Fh 38Fh 310h 390h 311h 391h IOCAP312h 392h IOCAN313h 393h IOCAF314h 394h IOCBP315h 395h IOCBN316h 396h IOCBF317h 397h 318h 398h 319h 399h 31Ah 39Ah 31Bh 39Bh 31Ch 39Ch 31Dh 39Dh 31Eh 39Eh 31Fh 39Fh 320h General Purpose

Register 16Bytes 3A0h



36Fh 3EFh370h

Accesses70h 7Fh

3F0hAccesses70h 7Fh

37Fh 3FFhTABLE 3-4: PIC16(L)F1509 MEMORY MAP, BANK 0-7BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

000hCore Registers

(Table 3-2)

080hCore Registers

(Table 3-2)

100hCore Registers

(Table 3-2)

180hCore Registers

(Table 3-2)

200hCore Registers

(Table 3-2)

280hCore Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 28Eh 00Fh 08Fh 10Fh 18Fh 20Fh 28Fh 010h 090h 110h 190h 210h 290h 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h 013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h 014h 094h 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h 018h T1CON 098h 118h DAC1CON0 198h 218h 298h 019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h 299h 01Ah TMR2 09Ah OSCSTAT 11Ah 19Ah TXREG 21Ah 29Ah 01Bh PR2 09Bh ADRESL 11Bh 19Bh SPBRG 21Bh 29Bh 01Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch 29Ch 01Dh 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh 29Dh 01Eh 09Eh ADCON1 11Eh 19Eh TXSTA 21Eh 29Eh 01Fh 09Fh ADCON2 11Fh 19Fh BAUDCON 21Fh 29Fh

020h GeneralPurposeRegister80 Bytes

0A0h


120hGeneralPurposeRegister80 Bytes

1A0hGeneralPurposeRegister80 Bytes

220hGeneralPurposeRegister80 Bytes

2A0hGeneralPurposeRegister80 Bytes

0EFh06Fh 16Fh 1EFh 26Fh 2EFh070h

Common RAM

0F0hAccesses70h 7Fh

170hAccesses70h 7Fh

1F0hAccesses70h 7Fh

270hAccesses70h 7Fh

2F0hAccesses70h 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh

Legend: = Unimplemented data memory locations, read as 0.

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PIC16(L)F1508/9

TABANK 14 BANK 15

40

40

0h

Bh


780h

78Bh


40 Ch 78Ch 40 Dh 78Dh 40 Eh 78Eh 40 Fh 78Fh 41 0h 790h 41 1h 791h 41 2h 792h 41 3h 793h 41 4h 794h 41 5h 795h 41 6h 796h 41 7h 797h 41 8h 798h 41 9h 799h 41 Ah 79Ah 41 Bh 79Bh 41 Ch 79Ch 41 Dh 79Dh 41 Eh 79Eh 41 Fh 79Fh 42 0h


7A0h


46 Fh 7EFh47 0h

Accesses70h 7Fh

7F0hAccesses70h 7Fh

47 Fh 7FFh

BANK 22 BANK 2380

80

0h

Bh


B80h

B8Bh


80 ChUnimplemented

Read as 0

B8ChUnimplemented

Read as 086 Fh BEFh87 0h

Accesses70h 7Fh

BF0hAccesses70h 7Fh

87 Fh BFFhLeBLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13

0h

Bh


480h

48Bh


500h

50Bh


580h

58Bh


600h

60Bh


680h

68Bh


70

70Ch 48Ch 50Ch 58Ch 60Ch 68Ch 70Dh 48Dh 50Dh 58Dh 60Dh 68Dh 70Eh 48Eh 50Eh 58Eh 60Eh 68Eh 70Fh 48Fh 50Fh 58Fh 60Fh 68Fh 700h 490h 510h 590h 610h 690h 711h 491h 511h 591h 611h PWM1DCL 691h CWG1DBR 712h 492h 512h 592h 612h PWM1DCH 692h CWG1DBF 713h 493h 513h 593h 613h PWM1CON 693h CWG1CON0 714h 494h 514h 594h 614h PWM2DCL 694h CWG1CON1 715h 495h 515h 595h 615h PWM2DCH 695h CWG1CON2 716h 496h 516h 596h 616h PWM2CON 696h 717h 497h 517h 597h 617h PWM3DCL 697h 718h 498h NCO1ACCL 518h 598h 618h PWM3DCH 698h 719h 499h NCO1ACCH 519h 599h 619h PWM3CON 699h 71Ah 49Ah NCO1ACCU 51Ah 59Ah 61Ah PWM4DCL 69Ah 71Bh 49Bh NCO1INCL 51Bh 59Bh 61Bh PWM4DCH 69Bh 71Ch 49Ch NCO1INCH 51Ch 59Ch 61Ch PWM4CON 69Ch 71Dh 49Dh 51Dh 59Dh 61Dh 69Dh 71Eh 49Eh NCO1CON 51Eh 59Eh 61Eh 69Eh 71Fh 49Fh NCO1CLK 51Fh 59Fh 61Fh 69Fh 710h


4A0h


520h


5A0h


620h


6A0h


72

Fh 4EFh 56Fh 5EFh 66Fh 6EFh 760h

Accesses70h 7Fh

4F0hAccesses70h 7Fh

570hAccesses70h 7Fh

5F0hAccesses70h 7Fh

670hAccesses70h 7Fh

6F0hAccesses70h 7Fh

77

Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 210h

Bh

Core Registers (Table 3-2 )

880h

88Bh


900h

90Bh


980h

98Bh


A00h

A0Bh


A80h

A8Bh


B0

B0Ch


88ChUnimplemented

Read as 0

90ChUnimplemented

Read as 0

98ChUnimplemented

Read as 0

A0ChUnimplemented

Read as 0

A8ChUnimplemented

Read as 0

B0

Fh 8EFh 96Fh 9EFh A6Fh AEFh B60h

Accesses70h 7Fh

8F0hAccesses70h 7Fh

970hAccesses70h 7Fh

9F0hAccesses70h 7Fh

A70hAccesses70h 7Fh

AF0hAccesses70h 7Fh

B7

Fh 8FFh 97Fh 9FFh A7Fh AFFh B7gend: = Unimplemented data memory locations, read as 0.

2011-2014 M


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PIC16(L)F1508/9

TA

Le

BANK 30 BANK 31C

C

00h

Bh


F80h

F8Bh


C Ch

See Table 3-7 for register mapping

details

F8Ch

See Table 3-7 for register mapping

details

C Dh F8DhC Eh F8EhC Fh F8FhC 10h F90hC 11h F91hC 12h F92hC 13h F93hC 14h F94hC 15h F95hC 16h F96hC 17h F97hC 18h F98hC 19h F99hC Ah F9AhC Bh F9BhC Ch F9ChC Dh F9DhC Eh F9EhC Fh F9FhC 20h FA0h

C Fh FEFhC 70h

Accesses70h 7Fh

FF0hAccesses70h 7Fh

C Fh FFFhBLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31

gend: = Unimplemented data memory locations, read as 0.

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 2900h

0Bh


C80h

C8Bh


D00h

D0Bh


D80h

D8Bh


E00h

E0Bh


E80h

E8Bh


F

F00Ch C8Ch D0Ch D8Ch E0Ch E8Ch F00Dh C8Dh D0Dh D8Dh E0Dh E8Dh F00Eh C8Eh D0Eh D8Eh E0Eh E8Eh F00Fh C8Fh D0Fh D8Fh E0Fh E8Fh F010h C90h D10h D90h E10h E90h F11h C91h D11h D91h E11h E91h F12h C92h D12h D92h E12h E92h F13h C93h D13h D93h E13h E93h F14h C94h D14h D94h E14h E94h F15h C95h D15h D95h E15h E95h F16h C96h D16h D96h E16h E96h F17h C97h D17h D97h E17h E97h F18h C98h D18h D98h E18h E98h F19h C99h D19h D99h E19h E99h F1Ah C9Ah D1Ah D9Ah E1Ah E9Ah F11Bh C9Bh D1Bh D9Bh E1Bh E9Bh F11Ch C9Ch D1Ch D9Ch E1Ch E9Ch F11Dh C9Dh D1Dh D9Dh E1Dh E9Dh F11Eh C9Eh D1Eh D9Eh E1Eh E9Eh F11Fh C9Fh D1Fh D9Fh E1Fh E9Fh F120h


CA0h


D20h


DA0h


E20h


EA0h


F

6Fh CEFh D6Fh DEFh E6Fh EEFh F670h

Accesses70h 7Fh

CF0hAccesses70h 7Fh

D70hAccesses70h 7Fh

DF0hAccesses70h 7Fh

E70hAccesses70h 7Fh

EF0hAccesses70h 7Fh

F

FFh CFFh D7Fh DFFh E7Fh EFFh F7

PIC16(L)F1508/9

TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31

Bank 30F0Ch F0Dh F0Eh F0Fh CLCDATAF10h CLC1CONF11h CLC1POLF12h CLC1SEL0F13h CLC1SEL1F14h CLC1GLS0F15h CLC1GLS1F16h CLC1GLS2F17h CLC1GLS3F18h CLC2CONF19h CLC2POLF1Ah CLC2SEL0F1Bh CLC2SEL1F1Ch CLC2GLS0F1Dh CLC2GLS1F1Eh CLC2GLS2F1Fh CLC2GLS3F20h CLC3CONF21h CLC3POLF22h CLC3SEL0F23h CLC3SEL1F24h CLC3GLS0F25h CLC3GLS1F26h CLC3GLS2F27h CLC3GLS3F28h CLC4CONF29h CLC4POLF2Ah CLC4SEL0F2Bh CLC4SEL1F2Ch CLC4GLS0F2Dh CLC4GLS1F2Eh CLC4GLS2F2Fh CLC4GLS3F30h


F6Fh

Bank 31F8Ch

FE3h


FE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh FEDh STKPTRFEEh TOSLFEFh TOSH

Legend: = Unimplemented data memory locations, read as 0.DS40001609D-page 24 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

3.2.6 CORE FUNCTION REGISTERS

SUMMARYThe Core Function registers listed in Table 3-8 can beaddressed from any Bank.

TABLE 3-8: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue on all other Resets

Bank 0-31x00h or x80h INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x01h or x81h INDF1

Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register) xxxx xxxx uuuu uuuu

x02h or x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h or x83h STATUS TO PD Z DC C ---1 1000 ---q quuu

x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h or x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h or x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h or x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h or x88h BSR BSR ---0 0000 ---0 0000

x09h or x89h WREG Working Register 0000 0000 uuuu uuuu

x0Ah or x8Ah PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh or x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. Shaded locations are unimplemented, read as 0. 2011-2014 Microchip Technology Inc. DS40001609D-page 25

PIC16(L)F1508/9

on all er ets

xxxx----xxxx

0-00-00-0000

uuuuuuuuuuuuuu-uuxuu

000011110000

1111----1111

0-0000--0000

1111qquu0110

1-00--qquuuuuuuu0000--00----s 0.TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue

othRes

Bank 000Ch PORTA RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx 00Dh PORTB RB7 RB6 RB5 RB4 xxxx ---- xxxx 00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx 010h Unimplemented

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 0000 0-00 0000 012h PIR2 OSFIF C2IF C1IF BCL1IF NCO1IF 000- -00- 000- 013h PIR3 CLC4IF CLC3IF CLC2IF CLC1IF ---- 0000 ---- 014h Unimplemented

015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu 018h T1CON TMR1CS T1CKPS T1OSCEN T1SYNC TMR1ON 0000 00-0 uuuu 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONET1GVAL T1GSS 0000 0x00 uuuu

01Ah TMR2 Timer2 Module Register 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 01Ch T2CON T2OUTPS TMR2ON T2CKPS -000 0000 -000

01Dhto

01Fh Unimplemented

Bank 108Ch TRISA TRISA5 TRISA4 (2) TRISA2 TRISA1 TRISA0 --11 1111 --11 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 08Eh TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 08Fh Unimplemented

090h Unimplemented

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 0000 0-00 0000 092h PIE2 OSFIE C2IE C1IE BCL1IE NCO1IE 000- 00-- 000- 093h PIE3 CLC4IE CLC3IE CLC2IE CLC1IE ---- 0000 ---- 094h Unimplemented

095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 1111 1111 1111 096h PCON STKOVF STKUNF RWDT RMCLR RI POR BOR 00-1 11qq qq-q 097h WDTCON WDTPS SWDTEN --01 0110 --01 098h Unimplemented

099h OSCCON IRCF SCS -011 1-00 -011 09Ah OSCSTAT SOSCR OSTS HFIOFR LFIOFR HFIOFS 0-q0 --00 q-qq 09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu 09Dh ADCON0 CHS GO/DONE ADON -000 0000 -000 09Eh ADCON1 ADFM ADCS ADPREF 0000 --00 0000 09Fh ADCON2 TRIGSEL 0000 ---- 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC16F1508/9 only.

2: Unimplemented, read as 1.DS40001609D-page 26 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

-uuu----uuuu

-100

--00---u0000-0--0000

0-00

-111----1111

00000000uuuuuuuuq0000000--01

0000000000000000000x00100-00

on all er ets

s 0. Bank 210Ch LATA LATA5 LATA4 LATA2 LATA1 LATA0 --xx -xxx --uu 10Dh LATB LATB7 LATB6 LATB5 LATB4 xxxx ---- uuuu 10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu 10Fh Unimplemented

110h Unimplemented

111h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1HYS C1SYNC 0000 -100 0000 112h

to114h

Unimplemented

115h CMOUT MC2OUT MC1OUT ---- --00 ---- 116h BORCON SBOREN BORFS BORRDY 10-- ---q uu-- 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 0q00 0000 0q00 118h DAC1CON0 DACEN DACOE1 DACOE2 DACPSS 0-00 -0-- 0-00 119h DAC1CON1 DACR ---0 0000 ---0

11Ahto

11Ch Unimplemented

11Dh APFCON SSSEL T1GSEL CLC1SEL NCO1SEL ---0 0-00 ---0 11Eh Unimplemented

11Fh Unimplemented

Bank 318Ch ANSELA ANSA4 ANSA2 ANSA1 ANSA0 ---1 -111 ---1 18Dh ANSELB ANSB5 ANSB4 --11 ---- --11 18Eh ANSELC ANSC7 ANSC6 ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 18Fh Unimplemented

190h Unimplemented

191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 192h PMADRH (2) Flash Program Memory Address Register High Byte 1000 0000 1000 193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu 194h PMDATH Flash Program Memory Read Data Register High Byte --xx xxxx --uu 195h PMCON1 (2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 197h VREGCON(1) VREGPM Reserved ---- --01 ---- 198h Unimplemented

199h RCREG USART Receive Data Register 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 19Fh BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 01-0

TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)


othRes

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read aNote 1: PIC16F1508/9 only.

2: Unimplemented, read as 1. 2011-2014 Microchip Technology Inc. DS40001609D-page 27

PIC16(L)F1508/9

1111----

11110000000000000000

000000000000------------

00000000000000000000

---0--00

on all er ets

s 0. Bank 420Ch WPUA WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 1111 ---- 1111 E20Eh

to212h

Unimplemented

213h SSP1MSK MSK 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000

218hto

21Fh Unimplemented

Bank 528Ch

to29Fh

Unimplemented

Bank 630Ch

to31Fh

Unimplemented

Bank 738Ch

to390h

Unimplemented

391h IOCAP IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 392h IOCAN IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 393h IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 0000 ---- 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 0000 ---- 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 0000 ---- 0000

397hto

39Fh Unimplemented

Bank 840Ch

to41Fh

Unimplemented

Bank 948Ch

to497h

Unimplemented

498h NCO1ACCL NCO1ACC 0000 0000 0000 499h NCO1ACCH NCO1ACC 0000 0000 0000 49Ah NCO1ACCU NCO1ACC 0000 0000 0000 49Bh NCO1INCL NCO1INC 0000 0000 0000 49Ch NCO1INCH NCO1INC 0000 0000 0000 49Dh Unimplemented

49Eh NCO1CON N1EN N1OE N1OUT N1POL N1PFM 0000 ---0 0000 49Fh NCO1CLK N1PWS N1CKS 0000 --00 0000



othRes



PIC16(L)F1508/9

----uuuu--------uuuu--------uuuu--------uuuu----

0000xxxx0--0-0000000

on all er ets

s 0. Bank 1050Ch

to51Fh

Unimplemented

Bank 1158Ch

to59Fh

Unimplemented

Bank 1260Ch

to610h

Unimplemented

611h PWM1DCL PWM1DCL 00-- ---- 00-- 612h PWM1DCH PWM1DCH xxxx xxxx uuuu 613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL 0000 ---- 0000 614h PWM2DCL PWM2DCL 00-- ---- 00-- 615h PWM2DCH PWM2DCH xxxx xxxx uuuu 616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL 0000 ---- 0000 617h PWM3DCL PWM3DCL 00-- ---- 00-- 618h PWM3DCH PWM3DCH xxxx xxxx uuuu 619h PWM3CON0 PWM3EN PWM3OE PWM3OUT PWM3POL 0000 ---- 0000 61Ah PWM4DCL PWM4DCL 00-- ---- 00-- 61Bh PWM4DCH PWM4DCH xxxx xxxx uuuu 61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL 0000 ---- 0000

61Dhto

61Fh Unimplemented

Bank 1368Ch

to690h

Unimplemented

691h CWG1DBR CWG1DBR --00 0000 --00 692h CWG1DBF CWG1DBF --xx xxxx --xx 693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA G1CS0 0000 0--0 0000 694h CWG1CON1 G1ASDLB G1ASDLA G1IS 0000 -000 0000 695h CWG1CON2 G1ASE G1ARSEN G1ASDC2 G1ASDC1 G1ASDSFLT G1ASDSCLC2 00-- 0000 00--

696hto

69Fh Unimplemented



othRes



PIC16(L)F1508/9

00000000uuuu-uuu-uuuuuuuuuuuuuuuuuuu0000uuuu-uuu-uuuuuuuuuuuuuuuuuuu0000uuuu-uuu-uuuuuuuuuuuuuuuuuuu0000uuuu-uuu-uuuuuuuuuuuuuuuuuuu0000uuuuuuuu

on all er ets

s 0. Banks 14-29x0Ch/x8Ch x1Fh/x9Fh

Unimplemented

Bank 30F0Ch

toF0Eh

Unimplemented

F0Fh CLCDATA MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE 0000 0000 0000 F11h CLC1POL LC1POL LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- F12h CLC1SEL0 LC1D2S LC1D1S -xxx -xxx -uuu F13h CLC1SEL1 LC1D4S LC1D3S -xxx -xxx -uuu F14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu F15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu F16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu F17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu F18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE 0000 0000 0000 F19h CLC2POL LC2POL LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- F1Ah CLC2SEL0 LC2D2S LC2D1S -xxx -xxx -uuu F1Bh CLC2SEL1 LC2D4S LC2D3S -xxx -xxx -uuu F1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu F1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu F1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu F1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu F20h CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE 0000 0000 0000 F21h CLC3POL LC3POL LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- F22h CLC3SEL0 LC3D2S LC3D1S -xxx -xxx -uuu F23h CLC3SEL1 LC3D4S LC3D3S -xxx -xxx -uuu F24h CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu F25h CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu F26h CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu F27h CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu F28h CLC4CON LC4EN LC4OE LC4OUT LC4INTP LC4INTN LC4MODE 0000 0000 0000 F29h CLC4POL LC4POL LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- F2Ah CLC4SEL0 LC4D2S LC4D1S -xxx -xxx -uuu F2Bh CLC4SEL1 LC4D4S LC4D3S -xxx -xxx -uuu F2Ch CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu F2Dh CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu F2Eh CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu F2Fh CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu F20h CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE 0000 0000 0000 F21h CLC3POL LC3POL LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- F2Fh CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu

F30hto

F6Fh Unimplemented



othRes



PIC16(L)F1508/9

-uuu

uuuu

uuuu

uuuu

uuuu

uuuu

uuuu

uuuu

1111uuuuuuuu

on all er ets

s 0. Bank 31F8Ch FE3h

Unimplemented

FE4h STATUS_SHAD

Z_SHAD DC_SHAD C_SHAD ---- -xxx ----

FE5h WREG_SHAD

Working Register Shadow xxxx xxxx uuuu

FE6h BSR_SHAD

Bank Select Register Shadow ---x xxxx ---u

FE7h PCLATH_SHAD

Program Counter Latch High Register Shadow -xxx xxxx uuuu

FE8h FSR0L_SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu

FE9h FSR0H_SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu

FEAh FSR1L_SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu

FEBh FSR1H_SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu

FECh Unimplemented

FEDh STKPTR Current Stack Pointer ---1 1111 ---1 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu FEFh TOSH Top-of-Stack High byte -xxx xxxx -uuu



othRes



PIC16(L)F1508/9

3.3 PCL and PCLATHThe Program Counter (PC) is 15 bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The high byte (PC) is not directlyreadable or writable and comes from PCLATH. On anyReset, the PC is cleared. Figure 3-4 shows the fivesituations for the loading of the PC.

FIGURE 3-4: LOADING OF PC IN DIFFERENT SITUATIONS

3.3.1 MODIFYING PCLExecuting any instruction with the PCL register as thedestination simultaneously causes the ProgramCounter PC bits (PCH) to be replaced by thecontents of the PCLATH register. This allows the entirecontents of the program counter to be changed bywriting the desired upper seven bits to the PCLATHregister. When the lower eight bits are written to thePCL register, all 15 bits of the program counter willchange to the values contained in the PCLATH registerand those being written to the PCL register.

3.3.2 COMPUTED GOTOA computed GOTO is accomplished by adding an offset tothe program counter (ADDWF PCL). When performing atable read using a computed GOTO method, care shouldbe exercised if the table location crosses a PCL memoryboundary (each 256-byte block). Refer to ApplicationNote AN556, Implementing a Table Read (DS00556).

3.3.3 COMPUTED FUNCTION CALLSA computed function CALL allows programs to maintaintables of functions and provide another way to executestate machines or look-up tables. When performing atable read using a computed function CALL, careshould be exercised if the table location crosses a PCLmemory boundary (each 256-byte block).

If using the CALL instruction, the PCH and PCLregisters are loaded with the operand of the CALLinstruction. PCH is loaded with PCLATH.

The CALLW instruction enables computed calls by com-bining PCLATH and W to form the destination address.A computed CALLW is accomplished by loading the Wregister with the desired address and executing CALLW.The PCL register is loaded with the value of W andPCH is loaded with PCLATH.

3.3.4 BRANCHINGThe branching instructions add an offset to the PC.This allows relocatable code and code that crossespage boundaries. There are two forms of branching,BRW and BRA. The PC will have incremented to fetchthe next instruction in both cases. When using eitherbranching instruction, a PCL memory boundary may becrossed.

If using BRW, load the W register with the desiredunsigned address and execute BRW. The entire PC willbe loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,the signed value of the operand of the BRA instruction.

7 86

14

0

0

4 11

0

6 0

14

7 86 0

014

15

014

15

014

PCL

PCL

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

PC

PC

PC

PC

PC

PCLATH

PCLATH

PCLATH

Instructionwith PCL asDestination

GOTO, CALL

CALLW

BRW

BRA

ALU result

OPCODE

W

PC + W

PC + OPCODE

Rev. 10-000042A7/30/2013DS40001609D-page 32 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

3.4 StackAll devices have a 16-level x 15-bit wide hardwarestack (refer to Figures 3-5 through 3-8). The stackspace is not part of either program or data space. ThePC is PUSHed onto the stack when CALL or CALLWinstructions are executed or an interrupt causes abranch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH isnot affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVRENbit is programmed to 0 (Configuration Words). Thismeans that after the stack has been PUSHed sixteentimes, the seventeenth PUSH overwrites the value thatwas stored from the first PUSH. The eighteenth PUSHoverwrites the second PUSH (and so on). TheSTKOVF and STKUNF flag bits will be set on an Over-flow/Underflow, regardless of whether the Reset isenabled.

3.4.1 ACCESSING THE STACKThe stack is available through the TOSH, TOSL andSTKPTR registers. STKPTR is the current value of theStack Pointer. TOSH:TOSL register pair points to theTOP of the stack. Both registers are read/writable. TOSis split into TOSH and TOSL due to the 15-bit size of thePC. To access the stack, adjust the value of STKPTR,which will position TOSH:TOSL, then read/write toTOSH:TOSL. STKPTR is 5 bits to allow detection ofoverflow and underflow.

During normal program operation, CALL, CALLW andInterrupts will increment STKPTR while RETLW,RETURN, and RETFIE will decrement STKPTR. At anytime STKPTR can be inspected to see how much stackis left. The STKPTR always points at the currently usedplace on the stack. Therefore, a CALL or CALLW willincrement the STKPTR and then write the PC, and areturn will unload the PC and then decrement theSTKPTR.

Reference Figure 3-5 through Figure 3-8 for examplesof accessing the stack.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

Note 1: There are no instructions/mnemonicscalled PUSH or POP. These are actionsthat occur from the execution of theCALL, CALLW, RETURN, RETLW andRETFIE instructions or the vectoring toan interrupt address.

Note: Care should be taken when modifying theSTKPTR while interrupts are enabled.

STKPTR = 0x1FStack Reset Disabled(STVREN = 0)

Stack Reset Enabled(STVREN = 1)

Initial Stack Configuration:

After Reset, the stack is empty. Theempty stack is initialized so the StackPointer is pointing at 0x1F. If the StackOverflow/Underflow Reset is enabled, theTOSH/TOSL register will return 0. If theStack Overflow/Underflow Reset isdisabled, the TOSH/TOSL register willreturn the contents of stack address0x0F.

0x0000 STKPTR = 0x1F

TOSH:TOSL 0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

0x1FTOSH:TOSL


PIC16(L)F1508/9



STKPTR = 0x00Return Address

This figure shows the stack configurationafter the first CALL or a single interrupt.If a RETURN instruction is executed, thereturn address will be placed in theProgram Counter and the Stack Pointerdecremented to the empty state (0x1F).

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00TOSH:TOSL

Rev. 10-000043B7/30/2013

STKPTR = 0x06

After seven CALLs or six CALLs and aninterrupt, the stack looks like the figure onthe left. A series of RETURN instructions willrepeatedly place the return addresses intothe Program Counter and pop the stack.

Return Address

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

TOSH:TOSL

Rev. 10-000043C7/30/2013DS40001609D-page 34 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9


3.4.2 OVERFLOW/UNDERFLOW RESETIf the STVREN bit in Configuration Words isprogrammed to 1, the device will be reset if the stackis PUSHed beyond the sixteenth level or POPedbeyond the first level, setting the appropriate bits(STKOVF or STKUNF, respectively) in the PCONregister.

3.5 Indirect AddressingThe INDFn registers are not physical registers. Anyinstruction that accesses an INDFn register actuallyaccesses the register at the address specified by theFile Select Registers (FSR). If the FSRn addressspecifies one of the two INDFn registers, the read willreturn 0 and the write will not occur (though Status bitsmay be affected). The FSRn register value is createdby the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows anaddressing space with 65536 locations. These locationsare divided into three memory regions:

Traditional Data Memory Linear Data Memory Program Flash Memory

STKPTR = 0x10

When the stack is full, the next CALL oran interrupt will set the Stack Pointer to0x10. This is identical to address 0x00 sothe stack will wrap and overwrite thereturn address at 0x00. If the StackOverflow/Underflow Reset is enabled, aReset will occur and location 0x00 willnot be overwritten.

Return Address0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x04

0x05

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return AddressTOSH:TOSL

Rev. 10-000043D7/30/2013 2011-2014 Microchip Technology Inc. DS40001609D-page 35

PIC16(L)F1508/9

FIGURE 3-9: INDIRECT ADDRESSING

0x0000

0x0FFF

0x0000

0x7FFF0xFFFF

0x0000

0x0FFF0x1000

0x1FFF0x2000

0x29AF0x29B0

0x7FFF0x8000

Reserved

Reserved

TraditionalData Memory

LinearData Memory

ProgramFlash Memory

FSRAddressRange

Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.


PIC16(L)F1508/9

3.5.1 TRADITIONAL DATA MEMORYThe traditional data memory is a region from FSRaddress 0x000 to FSR address 0xFFF. The addressescorrespond to the absolute addresses of all SFR, GPRand common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

Direct Addressing

4 0BSR 6 0From Opcode

007 FSRxH

0 0 007 FSRxL

Indirect Addressing

00000 00001 00010 11111Bank Select Location Select

0x00

0x7F

Bank Select Location Select

Bank 0 Bank 1 Bank 2 Bank 31


PIC16(L)F1508/9

3.5.2 LINEAR DATA MEMORYThe linear data memory is the region from FSRaddress 0x2000 to FSR address 0x29AF. This region isa virtual region that points back to the 80-byte blocks ofGPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of thelinear data memory region allows buffers to be largerthan 80 bytes because incrementing the FSR beyondone bank will go directly to the GPR memory of the nextbank.

The 16 bytes of common memory are not included inthe linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY MAP

3.5.3 PROGRAM FLASH MEMORYTo make constant data access easier, the entireprogram Flash memory is mapped to the upper half ofthe FSR address space. When the MSb of FSRnH isset, the lower 15 bits are the address in programmemory which will be accessed through INDF. Only thelower eight bits of each memory location is accessiblevia INDF. Writing to the program Flash memory cannotbe accomplished via the FSR/INDF interface. Allinstructions that access program Flash memory via theFSR/INDF interface will require one additionalinstruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH MEMORY MAP

0x020Bank 00x06F

0x0A0Bank 10x0EF

0x120Bank 20x16F

0xF20Bank 300xF6F

0 0 10 07 7FSRnH FSRnL

Location Select 0x2000

0x29AF

Rev. 10-000057A7/31/2013

0x0000

Program Flash

Memory (low 8 bits)

0x7FFF

10 07 7FSRnH FSRnL

Location Select 0x8000

0xFFFF


PIC16(L)F1508/94.0 DEVICE CONFIGURATIONDevice configuration consists of Configuration Words,Code Protection and Device ID.

4.1 Configuration WordsThere are several Configuration Word bits that allowdifferent oscillator and memory protection options.These are implemented as Configuration Word 1 at8007h and Configuration Word 2 at 8008h.

Note: The DEBUG bit in Configuration Words ismanaged automatically by devicedevelopment tools including debuggersand programmers. For normal deviceoperation, this bit should be maintained asa 1. 2011-2014 Microchip Technology Inc. DS40001609D-page 39

PIC16(L)F1508/9

4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1FCMEN(1) IESO(1) CLKOUTEN BOREN(2)

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1CP(3) MCLRE PWRTE WDTE FOSC

bit 7 bit 0

Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as 10 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit1 = Fail-Safe Clock Monitor is enabled(1)0 = Fail-Safe Clock Monitor is disabled

bit 12 IESO: Internal External Switchover bit(1)1 = Internal/External Switchover (Two-Speed Start-up) mode is enabled0 = Internal/External Switchover mode is disabled

bit 11 CLKOUTEN: Clock Out Enable bit1 = CLKOUT function is disabled. I/O function on the CLKOUT pin0 = CLKOUT function is enabled on the CLKOUT pin

bit 10-9 BOREN: Brown-Out Reset Enable bits(2)11 = BOR enabled10 = BOR enabled during operation and disabled in Sleep01 = BOR controlled by SBOREN bit of the BORCON register00 = BOR disabled

bit 8 Unimplemented: Read as 1bit 7 CP: Code Protection bit(3)

1 = Program memory code protection is disabled0 = Program memory code protection is enabled

bit 6 MCLRE: MCLR/VPP Pin Function Select bitIf LVP bit = 1:

This bit is ignored.If LVP bit = 0:

1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA3 bit.bit 5 PWRTE: Power-Up Timer Enable bit

1 = PWRT disabled0 = PWRT enabled

bit 4-3 WDTE: Watchdog Timer Enable bits11 = WDT enabled10 = WDT enabled while running and disabled in Sleep01 = WDT controlled by the SWDTEN bit in the WDTCON register00 = WDT disabledDS40001609D-page 40 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9bit 2-0 FOSC: Oscillator Selection bits111 = ECH:External clock, High-Power mode: on CLKIN pin110 = ECM: External clock, Medium-Power mode: on CLKIN pin101 = ECL: External clock, Low-Power mode: on CLKIN pin100 = INTOSC oscillator: I/O function on CLKIN pin011 = EXTRC oscillator: External RC circuit connected to CLKIN pin010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: When FSCM is enabled, Two-Speed Start-up will be automatically enabled, regardless of the IESO bit value.2: Enabling Brown-out Reset does not automatically enable Power-up Timer.3: Once enabled, code-protect can only be disabled by bulk erasing the device.

REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) 2011-2014 Microchip Technology Inc. DS40001609D-page 41

PIC16(L)F1508/9

REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1

LVP(1) DEBUG(3) LPBOR BORV(2) STVREN bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 WRT

bit 7 bit 0

Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as 10 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit(1)1 = Low-voltage programming enabled0 = High-voltage on MCLR must be used for programming

bit 12 DEBUG: In-Circuit Debugger Mode bit(3)1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11 LPBOR: Low-Power BOR Enable bit1 = Low-Power Brown-out Reset is disabled0 = Low-Power Brown-out Reset is enabled

bit 10 BORV: Brown-Out Reset Voltage Selection bit(2)1 = Brown-out Reset voltage (VBOR), low trip point selected0 = Brown-out Reset voltage (VBOR), high trip point selected

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit1 = Stack Overflow or Underflow will cause a Reset0 = Stack Overflow or Underflow will not cause a Reset

bit 8-2 Unimplemented: Read as 1bit 1-0 WRT: Flash Memory Self-Write Protection bits

4 kW Flash memory (PIC16(L)F1508 only)11 = Write protection off10 = 000h to 1FFh write protected, 200h to FFFh may be modified01 = 000h to 7FFh write protected, 800h to FFFh may be modified00 = 000h to FFFh write protected, no addresses may be modified

8 kW Flash memory (PIC16(L)F1509 only)11 = Write protection off10 = 000h to 01FFh write protected, 0200h to 1FFFh may be modified01 = 000h to 0FFFh write protected, 1000h to 1FFFh may be modified00 = 000h to 1FFFh write protected, no addresses may be modified

Note 1: The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.2: See VBOR parameter for specific trip point voltages.3: The DEBUG bit in Configuration Words is managed automatically by device development tools including

debuggers and programmers. For normal device operation, this bit should be maintained as a 1.DS40001609D-page 42 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/9

4.3 Code ProtectionCode protection allows the device to be protected fromunauthorized access. Internal access to the programmemory is unaffected by any code protection setting.

4.3.1 PROGRAM MEMORY PROTECTIONThe entire program memory space is protected fromexternal reads and writes by the CP bit in ConfigurationWords. When CP = 0, external reads and writes ofprogram memory are inhibited and a read will return all0s. The CPU can continue to read program memory,regardless of the protection bit settings. Writing theprogram memory is dependent upon the writeprotection setting. See Section 4.4 WriteProtection for more information.

4.4 Write ProtectionWrite protection allows the device to be protected fromunintended self-writes. Applications, such asbootloader software, can be protected while allowingother regions of the program memory to be modified.

The WRT bits in Configuration Words define thesize of the program memory block that is protected.

4.5 User IDFour memory locations (8000h-8003h) are designated asID locations where the user can store checksum or othercode identification numbers. These locations arereadable and writable during normal execution. SeeSection 10.4 User ID, Device ID and ConfigurationWord Access for more information on accessing thesememory locations. For more information on checksumcalculation, see the PIC12(L)F1501/PIC16(L)F150XMemory Programming Specification (DS41573). 2011-2014 Microchip Technology Inc. DS40001609D-page 43

PIC16(L)F1508/9

4.6 Device ID and Revision IDThe memory location 8006h is where the Device ID andRevision ID are stored. The upper nine bits hold theDevice ID. The lower five bits hold the Revision ID. SeeSection 10.4 User ID, Device ID and ConfigurationWord Access for more information on accessingthese memory locations.

Development tools, such as device programmers anddebuggers, may be used to read the Device ID andRevision ID.

4.7 Register Definitions: Device ID REGISTER 4-3: DEVID: DEVICE ID REGISTER

R R R R R R

DEVbit 13 bit 8

R R R R R R R R

DEV REVbit 7 bit 0

Legend:R = Readable bit1 = Bit is set 0 = Bit is cleared

bit 13-5 DEV: Device ID bits

bit 4-0 REV: Revision ID bitsThese bits are used to identify the revision (see Table under DEV above).

DeviceDEVID Values

DEV REV

PIC16LF1508 10 1101 111 x xxxxPIC16F1508 10 1101 001 x xxxxPIC16LF1509 10 1110 000 x xxxxPIC16F1509 10 1101 010 x xxxxDS40001609D-page 44 2011-2014 Microchip Technology Inc.

PIC16(L)F1508/95.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)

5.1 OverviewThe oscillator module has a wide variety of clocksources and selection features that allow it to be usedin a wide range of applications while maximizing perfor-mance and minimizing power consumption. Figure 5-1illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external oscillators,quartz crystal resonators, ceramic resonators andResistor-Capacitor (RC) circuits. In addition, the systemclock source can be supplied from one of two internaloscillators, with a choice of speeds selectable viasoftware. Additional clock features include:

Selectable system clock source between external or internal sources via software.

Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution.

Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL or EXTRC modes) and switch automatically to the internal oscillator.

Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources

Fast start-up oscillator allows internal circuits to power-up and stabilize before switching to the 16 MHz HFINTOSC

The oscillator module can be configured in one of thefollowing clock modes.

1. ECL External Clock Low-Power mode(0 MHz to 0.5 MHz)

2. ECM External Clock Medium-Power mode(0.5 MHz to 4 MHz)

3. ECH External Clock High-Power mode(4 MHz to 20 MHz)

4. LP 32 kHz Low-Power Crystal mode.5. XT Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)6. HS High Gain Crystal or Ceramic Resonator

mode (4 MHz to 20 MHz)7. EXTRC External Resistor-Capacitor8. INTOSC Internal oscillator (31 kHz to 16 MHz)

Clock Source modes are selected by the FOSCbits in the Configuration Words. The FOSC bitsdetermine the type of oscillator that will be used whenthe device is first powered.

The ECH, ECM, and ECL clock modes rely on anexternal logic level signal as the device clock source.The LP, XT, and HS clock modes require an externalcrystal or resonator to be connected to the device.Each mode is optimized for a different frequency range.The EXTRC clock mode requires an external resistorand capacitor to set the oscillator frequency.

The INTOSC internal oscillator block produces a lowand high-frequency clock source, designatedLFINTOSC and HFINTOSC. (See Internal OscillatorBlock, Figure 5-1). A wide selection of device clockfrequencies may be derived from these two clocksources. 2011-2014 Microchip Technology Inc. DS40001609D-page 45

PIC16(L)F1508/9

FIGURE 5-1: SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM

PrimaryOscillator

(OSC)

SecondaryOscillator(SOSC)

CLKIN/ OSC1/SOSCI/ T1CKI

CLKOUT/ OSC2/SOSCO/ T1G

Start-upControl Logic

16 MHzOscillator

Fast Start-upOscillator

31 kHzOscillator

Pre

scal

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PIC16F1509