Philips ftv1.9de_training manual

Published by JvR 9969 Service PaCE Printed in The Netherlands Subject to modification 3122 785 10036

©Copyright reserved 1999 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

Colour Television Chassis

FTV1.9DEAA

CL 965320690-163.eps020999

Contents Page1 Introduction 22 Mechanical instructions 53. Blockdiagram 114 Service modes 125 Preconditioner 266 VsVa supply 387 Audio Video control 548 PDP- Limesco 689 Audio amplifier 8010 LED panel 8111 Switch panel 8212 YUV / YC input 83

2 1. Introduction FTV1.9DE Display Box

Personal notes

1. Introduction

CL 96532069_002.eps240899

RECEIVER BOX

TV-CONFIGURATION

DISPLAY BOX

R, G, B, HS, VS

µP µP

CONFIG_IDENT

CONFIG_IDENT

DIS_RC_5

UART

PERSONAL COMPUTER

MONITOR-CONFIGURATION

DISPLAY BOXR, G, B, H, V

µP µPDDC

CONFIGURATIONS

The successor of the FTV1.5 is the FTV1.9, which had to be cheaper,and had to make as much as possible "re-use" of PWB's from the FTV1.5.

It is built around an E-Box (= Receiver Box) and a 42" Monitor (= Display Box). Within the Monitor a Fujitsu Plasma Display panel - version 5 - is used.

For the FTV1.9, the Monitor can be used in two applications.• Stand-alone configuration, monitor is connected to a PC or

a laptop • TV configuration, where the monitor is connected to the E-

box.

The Monitor is a separate device, which can also be sold and serviced separately.The monitor, as a stand-alone unit, can be serviced by using a test pattern coming from the PDP-LIMESCO panel on the monitor itself or via a PC/laptop by using ComPair via the ComPair connector.

FTV1.9 Family has been set up for Europe, USA, Asian and LATAM markets.The Europe type consisting of 1 version, having no diversity.

FTV1.9DE Display Box 1. Introduction 3

1.1 Description of used panels

Personal notes


CL 96532069_131.EPS120899

VS/VA Supply

PDP Limesco

YUV/YC Input

PDP DischargeAudio Amplifier

Pre-conditioner

AV Control

The panels are:1. VsVa supply. At this panel all the supply voltages will be

generated for the display itself, the electronics of the display and our PCB's. This panel contains also the fan control and the protection circuits.

2. PDP Discharge Panel. Temporarily used in the DEM-models of the FTV1.9. In the final models this panel is either going to be integrated into the VsVa panel or is going to be re-designed as a separate new panel. The function of this panel is to discharge the big capacitor of the Vs-supply and the Va-supply (minor reason). If these capacitors are not discharged it can take up to 60 seconds before the set re-starts after turning it OFF and ON again.

3. Audio amplifier. This panel is almost the same as the GFL audio amplifier. Some small changes have been made like other plugs, deleting a switch and external speaker connectors and an adaptation of the outlines, just to mount the panel at the backside of the Monitor.

4. Preconditioner. At this panel the mains input and mains output (to connect the E-Box) is located. After the mains input, the mains filter is placed. The panel contains also the preconditioner. This is an auto voltage function from 95V ... 264VAC in to 380VDC out and the standby supply for the µP and the NVM.

5. AV Control. At this panel the VGA, audio and control (UART or DDC) signals enter the Monitor. These signals will be buffered and are available at the output of this panel for feedthrough (except the control signals). The same signals will be fed to the Audio part (including an (optional) audio

4 1. Introduction FTV1.9DE Display Box


Personal notesdelay to correct the timing between video and audio) and to the video control IC to control the RGB signals. Also the µP for the panel control in the Monitor is located on this board. The audio filters for the high and low/medium signals are also located on the AV Control board.

6. PDP LIMESCO. This panel converts the analogue video after gamma correction to a digital video signal, which is connected to the PDP itself. The OSD generator is located at the PDP LIMESCO, close to the LIMESCO IC for the insertion of digital OSD information. The LIMESCO IC is responsible for the scaling of the signals of the various standard TV standards, VGA formats at this board. The H and V position is corrected by an EPLD.

7. YUV YC input panel. This board gives the possibility to attach several video formats to the stand-alone display. It also has one stereo audio connection.• Video input signals:

– YUV on three CINCHES (Y, Cb, Cr).– YC on Hosiden connector (SVHS).– CVBS on CINCH.– CVBS on BNC.

• Audio input signals:– L and R on 2 CINCHES.

• Output signal (AV Control):– RBG-signal.– H-sync and Vsync signal.– L and R audio signal.

8. LED Display panel. At this panel, the LED's and the IR-Receiver is located.

9. Switch Display panel. At this panel, the low power mains switch is located. With this switch a relay is controlled to switch ON and OFF the monitor

FTV1.9DE Display Box 2. Mechanical instructions 5

2.1 Introduction:

2. Mechanical instructions2.1 Introduction:There are pre-defined service positions for the following panels:1. VS/VA SUPPLY panel.2. PDP DISCHARGE panel.3. AUDIO AMPLIFIER panel.4. PRE-CONDITIONER panel.5. AV CONTROL panel.6. PDP LIMESCO panel. 7. YUV/YC INPUT panel.8. LED DISPLAY panel.9. SWITCH DISPLAY panel.Before these panels can be accessed, the rear cover has to be removed:

Figure 2-1

1. Place the Display Box in the service stand via 2 reinforced cushions (order code: 3122 126 30181).

2. Remove the 9 fixation screws of the rear cover. 3. Remove the rear cover (during removal push it slightly

upwards).

Figure 2-2

1. All panels are now accessible.

VS/VA SUPPLY panel.

Figure 2-3

1. Disconnect Fan Supply cable from connector FD07 in the upper left corner [1].

2. Remove the 7 fixation screws of the panel [2]. 3. Place panel on the 2 hinges, which are located near the

right corners of the panel [3].4. Use the mechanical service part (extension cable

assembly, 12NC: 3122 785 90006) to extend the Fan Supply cable [4].

5. The copper side is now accessible from the left.

PDP DISCHARGE panel.

As in the FTV 1.5, this panel must be exchanged completely if defective.

CL 96532069_130.EPS120899

2

1

CL 96532069_131.EPS120899

VS/VA Supply

PDP Limesco

YUV/YC Input

PDP DischargeAudio Amplifier

Pre-conditioner

AV Control

CL 96532069_132.EPS120899

1

2

3

4

VS/VA Supply

FD07

6 2. Mechanical instructions FTV1.9DE Display Box

2.1 Introduction:

AUDIO AMPLIFIER panel.

Figure 2-4

1. Some testpoints are accessible at the B-side [1].2. If this is not sufficient, remove the 3 fixation screws of the

panel [2].3. Panel now can be hinged on the left side to access the A-

side (soldering side) [3].

PRECONDITIONER panel.

Figure 2-5

1. Disconnect the 2 grounding wires from the shielding plate by pressing the small lever on the connector while pulling [1].

2. Remove the 2 ferrite ring cores from their fixations [2].3. Remove the 5 fixation screws of the panel [3].4. Place panel on the 2 hinges, which are located, near the left

corners of the panel [4].5. Reconnect grounding wires to the extra connectors on the

shielding plate at the left side [5].6. The copperside becomes accessible now from the right

side.

AUDIO VIDEO CONTROL panel.

Figure 2-6

CL 96532069_134.EPS120899

2

2

3

1

Audio Amplifier

5

CL 96532069_135.EPS120899

11

2 235

5

4

4

Pre-conditioner

CL 96532069_136.EPS120899

AV Control


2.1 Introduction:

This panel has no service position for accessing the A-side, however all service test points are accessible at the B-side (see Service Manual). In case some components must be (de)soldered, all fixation screws (6 for the panel, 5 at the metal connector plate) and all cables must be removed to access the A-side.

PDP LIMESCO panel.

Figure 2-7

All SMC's are located on the B-side, so all testpoints are accessible. In case some components must be (de)soldered, the hinge construction can be used to access the A-side.1. Remove the 4 fixation screws of the panel [1].2. Panel can now be hinged to access soldering side [2].

YUV/YC INPUT panel.

Figure 2-8

This panel has no pre-defined service position. For access of the A-side, the panel has to be removed:1. Remove the 4 screws at the metal connector plate [1].2. Remove the 2 fixation screws of the panel [2].3. Panel can be removed now to access the A-side [3].

LED DISPLAY panel.

Figure 2-9

CL 96532069_137.EPS120899

1

1

1

12

PDP Limesco

YUV/YC Input

2

1

3

CL 96532069_138.EPS120899

SVHS BNC

2

CL 96532069_139.EPS1208991

2

2


2.1 Introduction:

Personal notes1. Remove 2 x 2 screws at the sides and 4 screws at the

bottom of the front cover [1]. 2. Remove the front cover (it hinges at the top). During

removal unplug the cable of the LED DISPLAY panel at the SWITCH DISPLAY panel (connector SD11) [2].

Figure 2-10

1. The LED DISPLAY panel can be removed now by unscrewing 1 fixation screw [3].

SWITCH DISPLAY panel.

1. Remove front cover (for a description see Chapter 2.1.8 'LED DISPLAY panel').

Figure 2-11

1. The SWITCH DISPLAY panel can be removed now by unscrewing 3 fixation screws [3].

CL 96532069_140.EPS120899

3

CL 96532069_141.EPS120899

3


2.2 Exchanging parts

2.2 Exchanging partsSome parts of the FTV1.9 Display Box must be exchanged if defective:1. GLASS PLATE.2. LOUDSPEAKER.3. PLASMA DISPLAY PANEL [PDP].

Exchanging of the GLASS PLATE.

1. First unplug (remove Mains and VGA cable) the Display Box .


Figure 2-12

1. Now the GLASS PLATE can be removed by unscrewing all screws [3] and removing all glass clips [4].

Exchanging of a LOUDSPEAKER.

1. First unplug (remove Mains and VGA cable) the Display Box.


Figure 2-13

1. The LOUDSPEAKER can now be removed by disconnecting its cable and removing the 4 fixation screws at the top and bottom of the speakerbox. Be sure to remove the correct screws, otherwise the speaker system will be damaged (it is an airtight system).

Exchanging of the PDP.

1. First unplug (remove Mains and VGA cable) the Display Box.

2. Place the rear side of the Display Box on a foam cushion (be sure the metal rear cover is mounted in order to prevent damaging of the electronic panels).

3. Remove front cover (for a description see Chapter 2.1.8 LED DISPLAY panel).

4. Now the GLASS PLATE can be removed by unscrewing all screws and removing all glass clips (for a description see Chapter 2.2.1. 'Exchanging of the GLASS PLATE').

Figure 2-14

CL 96532069_142.EPS120899

2

3 4

5

CL 96532069_143.EPS120899

3

3

3

34

4

CL 96532069_144.EPS120899

6



Personal notes1. Remove all copper EMC SHIELDING springs mounted

around the display [6].2. Now flip the complete Display Box and place it with the

Plasma Display down on a foam cushion. Be 100 % sure a large foam cushion is placed underneath the PDP, as it will drop about 10 mm after removing its fixation screws ! !

3. Disassemble metal rear cover (for a description see Chapter 1.1 'Introduction').

Figure 2-15

1. Disconnect the following cables:– Cables coming from connectors CN23 and CN24 of the

PDP DISPLAY panel [3] (for easiest access lift the PDP DISCHARGE panel from its fixations [2]).

– Flat cable on connector PD3 of the PDP LIMESCO panel [4]. Also remove the ferrite 'flat cable shield' completely by unlocking its fixations [5].

Figure 2-16

1. Now remove the 8 large screws which hold the PDP:– 4 screws are located at the top: they also hold the

aluminium wall mount [1].– The other 4 are located at the bottom: the 2 outer screws

are hidden behind panels. Therefor unscrew the VS/VA SUPPLY and the PDP-LIMESCO panel (grey panels) [2].

2. Lift encasing from PDP and replace PDP [3].

CL 96532069_145.EPS120899

1

4

53

2

3

FD173 FD171

PDP Discharge

PDP Limesco

PD3

CN24 CN23

FOAM CUSHION

CL 96532069_146.EPS120899

11

11

22

23

2

FTV1.9DE Display Box 3. Block diagram 11

Personal notes

3. Block diagramFor the block diagram see Service Manual chapter 6.The power is supplied by the VsVa supply (which is an LLC converter). The Pre-conditioner delivers the input voltage of 380 V.

The output voltages of the VsVa supply are: • Va: 55 V + 5 * Vra (Vra varies between 0 and 2 V).• Vs: 165 V + 10 * Vrs (Vrs varies between 0 and 2 V).• +5 V, 8.6 V and the +/- V_audio.

The controls located on the µP panel, which is a panel on the AV Control panel, are activated by the keyboard on the Front I/O and RC5 signals from the remote control receiver on the LED panel. Audio signals coming from the YUV Y/C panel or from the AV Control are selected and processed at IC7940 (TDA9860). The outcoming L/R signals are filtered (HPF) and corrected for low frequency by the DBE-circuit, before they are fed to the Audio amplifier.CVBS signals (BNC connector or CINCH) at the YUV Y/C panel are first passed through a comb-filter IC7012. The output signals (Y and C) of IC7012 and the Y/C signal from the SVHS connector are selected by IC7010. The output Y/C are fed to YUV/RGB matrix IC7013 (TDA8854). The YUV signals (CINCH) are processed separately in a RGB matrix and transferred to IC7013. The selected RGB_YC output signals from IC7013 are fed to the AV Control panel. RGB signals coming from the Receiver Box or PC, the normal RGB_VGA or separate RGB_YC signals are selected by the source select switch (IC7360). The output signals are fed to the video control IC7300. The RGB output signals from IC7300 are buffered and transferred to the PDP LIMESCO panel. Here the signals are prepared and processed (gamma correction; filtered; digitised by an ADC), buffered and fed to the display. OSD-signals are added on the display via the PDP LIMESCO IC.RGB_VGA input signal are buffered and passed through to the VGA-out connector.

12 4. Service modes FTV1.9DE Display Box


Personal notes

4. Service modesFor the FTV1.9, the Monitor can be used in two applications.• A stand-alone configuration, a separate device which can

also be sold and serviced separately. • TV configuration, where the monitor is combined with the E-

box.

The monitor, as a stand-alone unit, can be serviced by using a test pattern coming from the PDP-LIMESCO panel on the rear of the monitor itself or via a PC/laptop by using ComPair via the ComPair connector.

In this chapter the following paragraphs are included:1. Test points2. Dealer Service Tool (DST)3. Service Modes4. Error code buffer and error codes5. The "blinking LED" procedure 6. Fault-finding tips7. ComPair

FTV1.9DE Display Box 4. Service modes 13

4.1 Test points

Personal notes

4.1 Test pointsThe FTV1.9 chassis is equipped with test points in the service printing. These test points are referring to the functional blocks:• A1-A2-A3, etc.: Test points for the Audio amplifier (A)• C1-C2-C3, etc.: Test points for the AV control circuit (AVC)• FD1-FD2-FD3, etc.: Test points for the VsVa supply (FD1-

FD2) and the PDP discharge panel• L1-L2-L3, etc.: Test points for the PDP LIMESCO (PD1-

PD9)• PR1-PR2-PR3, etc.: Test points for the Pre-conditioner

(PR1-PR3)• Y1-Y2-Y3, etc: Test points for the Y/C YUV monitor panel

(UY1-YC4)

Measurements are performed under the following conditions:Video: colour bar signal; Audio: 3 kHz left, 1 kHz right


4.2 Dealer Service Tool (DST)

Personal notes

4.2 Dealer Service Tool (DST)For easy installation and diagnosis the dealer service tool (DST) RC7150 can be used. When there is no picture (to access the error code buffer via the OSD), DST can enable the functionality of displaying the contents of the entire error code buffer via the blinking LED procedure, see also paragraph 5.5. The ordering number of the DST (RC7150) is 4822 218 21232.

Installation features for the dealer

The dealer can use the RC7150 for programming the TV-set with pre-sets. 10 Different program tables can be programmed into the DST via a GFL TV-set (downloading from the GFL to the DST; see GFL service manuals) or by the DST-I (DST interface; ordering code 4822 218 21277). For explanation of the installation features of the DST, the directions for use of the DST are recommended (For the FTV1.9 chassis, download code 4 should be used).

Diagnose features for service

FTV1.9 sets can be put in two service modes via the RC7150. These are the Service Default Mode (SDM) and the Service Alignment Mode (SAM).


4.3 Service Modes

4.3 Service Modes Below described sequence is only valid for the "Monitor Only Configuration". When a Receiver box is connected to the Display Box (TV Configuration), please check chapter 4 in the Training Manual of the Receiver Box.

Service Default Mode (SDM)

The purpose of the SDM is:• Provide a situation with predefined settings to get the same

measurements as in this manual.• Access to the error buffer via the blinking LED procedure.• Inspect the error buffer.• Possibility to overrule software protections via the service

pins (caution: override of software protections! ).

Entering the SDM:• By transmitting the "DEFAULT" command with the RC7150

Dealer Service Tool (this works both while the set is in normal operation mode or in the SAM).

• By pressing on a standard RC the following sequence 0, 6, 2, 5, 9, 6 followed by the "MENU" key.

• By short-circuiting the SDM pin on the µP panel. In the SDM the following information is displayed on the screen:--------------------------------------------------------------F19DBC X.Y_12345 (1) LLLL (2) SDM (3)ERR 02 01 14 ## ## ## ## ## ## ##--------------------------------------------------------------Explanation notes/references:(1) Software identification of the main micro controller (F19DBC X.Y_12345)• F19D is the chassis name for FTV1.9 display • B is the region identification• C is the language cluster• X = (main version number)• Y = (subversion number)• ##### are 5 digits of the Serial number(2) "LLLL" Normal display operation in hours(3) "SDM" To indicate that the TV set is in the service default mode(4) "ERR 02 01 14 ## ## ## ## ## ## ##" This line shows the contents of the error buffer (max. 10 errors). The last error that occurred is displayed at the most left position. When less then 10 errors have occurred the rest of the line is empty. When the errorlist is empty " No errors" is displayed. No duplicate errors.

Exit the SDM:Push the "Standby" button on the Remote Control.The SDM sets the following pre-defined conditions:• Volume level is set to 25% (of the maximum volume level).• Linear Audio and Video settings are set to 50%.• Colour temperature is set to normal.

The following functions are "overruled" in SDM since they interfere with diagnosing/repairing a set• Video blanking.• Slow demute. • Anti-ageing.• Automatic switch to "Standby" when H- and/or V-sync

signals are lost.All other controls operate normally.

Service Alignment Mode (SAM)

The purpose of the SAM is to align and or adjust settings.For recognition of the SAM, "SAM" is displayed at the top of the right side of the screenEntering the SAM-menu:• By pressing the "ALIGN" button on the RC7150 Dealer

Service Tool • Standard RC sequence 062596 followed by the "OSD"

button.• By short-circuiting the SAM pin on the µP panel (Caution:

override of software protections ! ! )

In the SAM the following information is displayed on the screen:--------------------------------------------------F19DBC X.Y_12345 SAMERROR## ## ## ## ##WHITE POINTPDP TEST PATTERN [ON/OFF]STORERESET ERROR BUFFER--------------------------------------------------

The menus and submenus

White pointThe white point sub menu contains the following items:• RED• GREEN• BLUE• COLOUR TEMPERATURE

PDP Test patternBy selecting this item, all OSD disappears from the screen. The screen now changes from light grey to dark grey in a slow regular rhythm. One can so easily check if all pixels of the monitor are correct.

StoreThe change values are stored in the NVM.

Reset Error BufferThis option will reset the error buffer.

Exit the SAM:Push the "Standby" button on the Remote Control.SAM menu control:Menu items can be selected with the "UP" or "DOWN" key. Entry into the selected items (sub menus) is done by the "LEFT" or "RIGHT" key. The selected item will be highlighted. With the same "LEFT/RIGHT" keys, it is possible to increase/decrease the value of the selected item.Return to the former screen by pushing the "MENU" button. The item values are stored in NVM if the sub menu is left.


4.3 Service Modes

Personal notesCustomer Service Mode (CSM) Display

FTV1.9 monitors are equipped with the "Customer Service Mode" (CSM). CSM is a special service mode that can be activated and de-activated by the customer, upon request of the service technician/dealer during a telephone conversation in order to identify the status of the set. This CSM is a 'read only' mode, therefore modifications in this mode are not possible.

Entering the Customer Service Mode. • By pressing on RC03333/01 the following sequence :

Picture, sound, cursor up, cursor down, cursor left, cursor right followed by the button (MUTE)

Exit the Customer Service Mode.• pressing the "MENU" or any key on the Remote Control

handset (except "P+" or "P-")• switching off the TV set with the mains switch.All settings that were changed at activation of CSM are set back to the initial values

The Customer Service Mode information screen

The following information is displayed on screen:--------------------------------------------------CUSTOMER SERVICE MENU• Software version F19DBC X.Y_#####)• Code 1: contains the last 5 error codes• Code 2: contains the first 5 error codes with the last

received error at the most left-hand side.• Service unfriendly modes--------------------------------------------------


4.4 Error code buffer and error-codes

Personal notes

4.4 Error code buffer and error-codes

Error-nr Type of Error Possible defect/cause1 +5V +5V pin at uP is low.

2 8V6 8V6 pin at uP is low

3 Fan_prot Gives an indication that 1 or more FAN(s) does not function, or that 1 ormore fan control circuits is defect

4 Over-temp_prot Temperature at the heatsink of the VsVa supply or the Preconditioner istoo high

5 DC_prot Audio-amplifier IC, its supply or the Audio amplifier is defect6 Over_voltage_prot Vs or Va supply voltage is too high7 Vrr Powersupply of the display is not correct. Ignorance of the signal during

startup by the software.8 Power_OKE Power supply or modules that uses this voltage. If this signal is NOT

activated means that all supply voltages are available (exception Audiosupply )

9 Blocked NVM IIC bus NVM IIC bus is not correct10 Blocked slow IIC bus Slow IIC bus is not correct11 TDA9860 No acknowledge of Audio controller12 TDA4885 No acknowledge of Video controller13 MC141585 No acknowledge of OSD Generator14 uPD93687GD-LBD No acknowledge of Limesco15 PCF8574AT No acknowledge of I/O Expander16 NVM No acknowledge of NVM17 Communication Fault in the communication

Figure 1 : Error-code list of the D-boxch5-table1-mon.eps

041099

The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right.In case of non-intermittent faults, clear the error buffer before starting the repair to prevent that "old" error codes are present. If possible check the entire content of the error buffers. In some situations an error code is only the RESULT of another error code (and not the actual cause).Note: a fault in the protection detection circuitry can also lead to a protection

The error code buffer will be cleared in the following cases:• exiting SDM or SAM with the "Standby" command on the

remote control• transmitting the commands "DIAGNOSE-9-9-OK" with the

DST.

The error buffer is not reset by leaving SDM or SAM with the mains switch.

Examples:ERROR: 0 0 0 0 0 : No errors detectedERROR: 6 0 0 0 0 : Error code 6 is the last and only detected errorERROR: 5 6 0 0 0 : Error code 6 was first detected and error code 5 is the last detected (newest) error


4.5 The "blinking LED" procedure

Personal notes

4.5 The "blinking LED" procedureThe contents of the error buffer can also be made visible through the "blinking LED" procedure. This is especially useful when there is no picture.

There are two methods:• When the SDM is entered, the LED will blink the contents of

the error-buffer. Error-codes = 10 are shown as followed. A long blink of 1second which is an indication of the decimal digit, followed by a pause, followed by n short blinks. When all the error-codes are displayed, the sequence is finished with a led display of about 3 seconds. The sequence starts again.

• With the DST all error codes in the error buffer can be made visible. Transmit the command: "DIAGNOSE x OK" where x is the position in the error buffer to be made visible x ranges from 1, (the last (actual) error) to 10 (the first error). The LED will operate in the same way as in the previous point, but now for the error code on position x.

Example:Error code position 1 2 3 4 5 Error buffer: 12 9 5 0 0 • after entering SDM: 1 long blink of 1 sec. + 2 short blinks -

pause - 9 short blinks - pause - 5 short blinks - pause - long blink of 3 sec. --etc.

• after transmitting "DIAGNOSE- 1- OK" with the DST: 1 long blink 2 short blinks - pause - 1 long blink + 2 short blinks - etc.

• after transmitting "DIAGNOSE- 2- OK" with the DST: blink (9x) - pause - blink (9x) - etc.

• after transmitting "DIAGNOSE- 3- OK" with the DST: blink (5x) - pause - blink (5x) - etc.

• after transmitting "DIAGNOSE- 4- OK" with the DST: nothing happens


4.6 Protections

Personal notes

4.6 ProtectionsAll protections are handled by the hardware. The SW will only monitor the hardware to generate error codes for the service. The hardware switches to protection when one of the following protections becomes active: FAN_PROT, OVER_TEMP_PROT, DC_PROT, OVER_VOLTAGE_PROT and Vrr.When 1 of these protections occur, the HW will switch the set to STANDBY.The error must be read out by the microprocessor and the error code must be generated. The microprocessor keeps the set in STANDBY and starts the blinking red led. It is not allowed to start up as long as the protections are present.For the error code generation, the following levels of the A/D converter are defined:

Input voltage at A/D converter [V]: Sort protection:

< 0.300 V No protection

0.3 < V < 1.875 FAN_PROT

1.875 < V < 2.813 OVER_VOLTAGE_PROT

2.813 < V < 3.75 OVER_TEMP_PROT

3.75 < V < 4.688 DC_PROT


LLC Control

LLC Control

ProtectionCircuit

LLC Converter

DISPLAY SUPPLY MODULE

LLC Converter

DC_DCConverter

FANPROTECTION

Vs

Vrs

Vrr

Vrr to µP

POWER OKPOWER OK

TEMP

380 VDC

Fans (1-5)Speed Control

Delay

OVPSENSE

OVPSENSE

ErrorAmp.

ErrorAmp.

DC PROT (Audio)

STBY

+5V

Vcc

FAN PROT

FanProtectVa OVP

5V OVP

ptc

ptc

ptc

17V

17V

Vs OVP

PROT-FAN (1-5)

+8V6

+/- V Audio

Va

Vs VaVocok

Vra

5VSTBY-SWITCHED TO µP

5VSTBY

On/OffSwitch

AND -1

CL 96532069_112.eps240899


4.6 Protections

Personal notes

POWER_OKE

For ease of start-up and fault diagnosis a POWER_OKE signal is generated. The signal is high when the voltages that are sensed are in the right level. This signal is mixed with signals derived from Vs and the Va. The POWER_OKE signal will be high when simultaneously: 5V = 5V17V >12.8VVs >135VVa > 45VIn all other cases the output is low.


4.6 Protections

Personal notes

CL 96532058_086.eps280999

+5V

TEMP

73017302

3331

3332

3333

3 8

4

2

7371

3134

3138

3133

3136

3137

3384

3394

3385

3135

7113

7114

21352132

7341

FD1[C-14]

7112

2134

7370

SUPPLY-ON[PR3]

CONNECTORFD06-12

VCC

5VSTBY-SWITCHED 5VSTBY-SWITCHED

5VSTBY-SWITCHED

5VSTBY-SWITCHED

5VSTBY-SWITCHED

5VSTBY-SWITCHED

7330-A

7331

17V

7332

7337

3380

3323

3386

3339

45

D09

VDD

CONNECTOR

7333

3379 3378

7339

7338

7003 7103

3039

7103

31113011

PROTECTION-STATUS

7001-PIN10

PROTS

VA

AA

DC

VS

20373034

3058

3033

7012

7013

3035

2032

63717314

17V73217340

7315

7316-7321

2038

3036

3037

3038

7016

7101-PIN10

PROT-FAN 1-6

3139

Protection structure

The protection structure of the FTV1.9 D-box is shown at figure above. The FTV1.9 monitor has one microprocessor, which is situated on the AV-control panel and is supplied by the 5V standby-supply. The microprocessor is even active when the set is switched to standby. The microprocessor controls the "supply-on" line which switches first relay 5680 and then relay 5690. In de standby-mode or the protection-mode the "supply-on" line is "low" and both both relays are switched off. The preconditioner is disconnected from the mains.

The potections of the FTV1.9 monitor can be divided into 5 subgroups:– Fan_prot– Over_temp_prot– DC_prot– Over_voltage_prot– Vrr

For the Fan-, Over_temp, DC and the Over_voltage protections the signals for the µP are latching, using the 5Vstby_switched for powering the circuits permanently. The µP has sufficient time for diagnosis and for storing the error-codes in the NVM. Vrr, which is an indication of the powersupply of the display is correct, is directly fed to the µP.


4.6 Protections

Signal line "PROTECTION STATUS" and errorcodes

When one of the protection mechanism is triggered, the 5Vstby-switched is connected via a saturated transistor and a pre-defined resistor to signal line "protection status", which is connected to the µP.Signal line "protection status" is connected to ground via resistor R3378 and 3379. For each seperate fault condition mechanism we get a pre-defined voltage at the µΠ.This results in the following table

Protection signal Vrr coming from the PDP, to indicate that the powersupply is ok or not ok ( "1" or "0" ) is directly connected to the µP. Error-code 7 is stored in the NVM and the set is switched to standby.When one of the protections is activated, the power supplies of the Vs and Va are shut down and the set is switched to standby.

Fan protection

When this protection is activated, the Va- and Vs power supply are shut down. The set is switched to the standby mode and error-code 3 is stored in the NVM. The fan voltage is powered by 17V, but clamped to 12V to prevent damage. In order to be able to verify whether the fans are running, a fault detection circuit is implemented for each of the 6 fans. A running fan gives pulses in the same speed as the rotation of the blades. The circuit uses these pulses to trigger the discharge of an elcap. The elcap is continuously charged through a resistor.

Example : Capacitor C2319 is charged through R3356 and at every pulse discharged by T7322. When fan 6 is blocked, C2314 is charged via D6326 en triggers thyristor 7315, because C2319 is no longer discharged via T7322. The current now flows from the 5Vstby-switched via resistor 3383 and 3325 driving transistor T7321 into saturation. The voltage "protection status" is now determined by the voltage dividing of R3323 and resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7321. ).

Reset of the VsVa-supply.Transistor T7339 is shorted now by the presence of the "protection status" signal. T7339 connects resistor R3376 and R3389 to ground, switching on T7338. Thyristor 7333 is now triggered, shorting signal PROTS to ground. To follow the signal flow, go to the right upper corner of schematic FD1.

Connecting PROTS to ground, will start a current flow through opto-coupler diode 7103 and the opto-coupler transistor connects supply voltage Vcc2 to the fault input ( pin 10 ) of IC 7101. When the voltage at pin 10 exceeds 1.0V, IC7101 stops oscillating. The Va-supply stops functioning.To continue the signal flow, go to the right upper corner of schematic FD2. Connecting PROTS to ground also results in a current flow through the opto-coupler diode of 7003. The opto-coupler transistor connects supply voltage Vcc1 to the fault input ( pin 10 ) of IC 7001. When the voltage at pin 10 exceeds 1.0V, IC7001 stops oscillating. The Vs-supply stops functioning.

Vs and Va protection

Va protectionWhen this protection is activated, the Va- and Vs power supply are shut down. The set is switched to the standby mode and error-code 4 is stored in the NVM.When the Va-supply exceeds the 68V, regulator 7112 is triggered and will switch on T7113. Capacitor 2132 is charged via the 5Vstby-switched and will trigger thyristor 7114, which will switch on T7341. The voltage "protection status" is now determined by the voltage dividing of R3386 and resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7341 ). See schematic FD2. The presence of the voltage at "protection status" line will eventually reset the VsVa-supply. For more info see subparagraph - Reset of the VsVa-supply.

Vs protectionWhen this protection is activated, the Vs power supply is shut down. The set is switched to the standby mode and error-code 4 is stored in the NVM.When the Vs supply exceeds the 198V, regulator 7012 is triggered and will switch on T7016. Capacitor 2032 is charged via the 5Vstby-switched and will trigger thyristor 7013. Thyristor 7013 is fired and connects signal Aa to ground. To follow the signal flow, go to the right upper corner of schematic FD1. When signal Aa is shorted to ground, T7341 is switched on. The voltage "protection status" is now determined by the voltage dividing of R3386 and resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7341 ). See schematic FD2. The presence of the voltage at "protection status" line will eventually reset the VsVa-supply. For more info see subparagraph - Reset of the VsVa-supply.

Temperature Protection

When this protection is activated, the Va- and Vs power supply are shut down. The set is switched to the standby mode and error-code 5 is stored in the NVM. When the temperture of the heatsink on the Preconditioner panel or on one of the 2 heatsink on the VsVa panel exceeds the 110°C, the PTC resistance increases drastically. The voltage at pin 3 of IC7330 will drop and the output of 7330 will do the same. The current flow through opto-coupler diode 7331 results also in a current flow through the opto-coupler transistor and will trigger thyristor 7332. The fired thyristor switches transistor 7337 on. The voltage "protection status" is now

Protection-mode

Series resistor

Voltage at "protection-status" line

Error-code

None ----- < 0.3V none

Fan_prot 1KΩ 0.30V < Vprot < 1.90V 3

Vs or Va_prot

470Ω 1.90V < Vprot < 2.80V 4

Temp_prot 220Ω 2.80V < Vprot < 3.75V 5

DC-prot 68Ω 3.75V < Vprot < 4.7V 6

Vrr ------ ------ 7


4.6 Protections

Personal notesdetermined by the voltage dividing of R3339 and resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7337 ). The presence of the voltage at "protection status" line will eventually reset the VsVa-supply. For more info see subparagraph - Reset of the VsVa-supply.

DC Protection - Audio Amplifier

When this protection is activated, the Va- and Vs power supply are shut down. The set is switched to the standby mode and error-code 6 is stored in the NVM.In case of a fault in the Audio amplifier or when a DC voltage appears on the speaker output, a signal called DCPROT is generated. See schematic FD2 - F7. In case of a fault, thyristor 7314 is triggered and switches on T7340. The voltage "protection status" is now determined by the voltage dividing of R3380 and resistor R3378 and 3379. ( neglect the Vce of 0.2V of T7340 ).The presence of the voltage at "protection status" line will eventually reset the VsVa-supply. For more info see subparagraph - Reset of the VsVa-supply.

Vrr - PDP supplies

Vrr is a logical signal ( "high" in normal circumstances ) that comes from the PDP. It's purpose is to trigger the switch off of the Pre-conditioner supply in case Vrr becomes "low" , to trigger the shutdown of the VsVa supply and to initialise that error-code 7 is stored in the NVM. When signal Vrr becomes "low", see FD1 - F13, the output of IC7301-B becomes "high". This results in two actions. It will trigger thyristor 7302 and short signal PROTS to ground. This results eventually in a reset of the VsVa supply. Switching on T7371, which again switches on T7370 via the 5Vstby-switched supply. Signal-line "supply-on" is now grounded. This results in switching off relay 5680 and 5690, disconnecting the mains from the pre-conditioner. The standby supply( 5Vstby-switdhed ) is still functional.


4.7 Alignments

Personal notes

4.7 Alignments

Electrical Alignments

Pre-conditioner +5Vstby (PR3)Connect a voltmeter to capacitor C2510 (PR2). With the aid of R3504 adjust the voltage to 5.2 V +/- 50 mV.

Va-supply (Addressing of the PDP - FD1)De-activated the PDP.Connect a voltmeter to capacitor C2120 (FD1). With the aid of R3126 adjust the voltage to 55 V +/- 0.5 V.

Vs-supply (Sustain pulses - FD2)De-activated the PDP.Connect a voltmeter to capacitor C2020 (FD2). With the aid of R3026 adjust the voltage to 165 V +/- 0.5 V.

Software Alignments

See chapter 4.3.2. "Service Alignment Mode (SAM)".

26 5. Preconditioner FTV1.9DE Display Box

5.1 Caution

Personal notes

5. Preconditioner5.1CautionWhen repairing the Preconditioner supply the hidden mains-switch must be used to disconnect the monitor from the mains. The pre-conditioner and the VsVa supply remains under tension if the mains-cable is still connected to the mains socket and the mains switch is NOT pressed.

FTV1.9DE Display Box 5. Preconditioner 27

5.2 Introduction

Personal notes

5.2 Introduction

CL 96532069_119.eps300999

MAINS FILTER PRECONDITIONER

STANDBY SUPPLY+5VSTBY Switched

380V

+5VSTBY

SUPPLY ON

POR

TEMP

PRECON

MAINS IN

+12VSB

Filtered Mains

Voltage

The preconditioner module is designed for the FTV 1.9. It is the interface between the mains input and the VsVa panel of the monitor.

The advantage of a preconditioner in this application is:• reduction of mains harmonics to legal limits• lower mains current for the same output power.• regulated output for the mains isolated power supplies

following the preconditioner module.

The preconditioner consists of 3 functional sub-modules.1. Mains filter2. Main supply3. Stand-by supply


5.3 General description.

CL 96532069_085.eps300999


5.3 General description.

Personal notes

The mains is fed through the mainsfilter to reduce common- and differential noise.

The mains switch - 1004, is added to disconnect the mains input from the pre-conditioner. This ON/OFF relay has to be switched manually, while the other relay is controlled by the SUPPLY ON signal. This signal is low if the standby signal is high, or one of the protections is activated.

The standby supply is a separate power supply to reduce power consumption of the Flat TV set in standby mode. The bridge rectifier rectifies the mains voltage and is applied to a differential mode filter- 5605 for EMI requirements and then to the preconditioner.

The preconditioner has an output voltage of 380V, controlled by the PCF controller (MC3336P) which is independent of the mains input. The output voltage of 380V is delivered to the Vs- and Va supply.

A PTC is connected to the heatsink of the MOSFET, which puts the set in protection, by activating an Opamp on the VsVa panel, when the temperature exceeds a safety limit.


5.4 Mainsfilter

Personal notes

5.4 Mainsfilter

V

AC inlet

RE

S

LIVE_IN

PR30

GROUND_IN

RE

S

PR31

NEUTRAL_IN24

02

F201 GNDEARTH2

470p

F209

I201

1402

DSP

47p

2406

F203

I204

F208

I205

F204 220R

3404

5400 21

43

PR2

GNDEARTH2

F202

12

34

2407

1

2

3

5401CU28D3

F211

0314

CU28D35402

12

34

140047p

2404

2405

I200

F207

F200

I206

4M7

3403

3402

4M7

1004

3 1

4 2

PR1

PR3

F212

3400

2322

595

GNDEARTH2

GNDEARTH2

1M3401

220n

2401

I202

470n

2400

I203

470p

2403F210

1401

CL 96532069_113.eps110899

MAINS FILTER

The AC power is fed to the mainsfilter (0314). A mains switch has been added to switch off the mains while repairing the set. The first filter around coil 5400 is to differential mode filter to reduce H.F. noise produced by the FTV. A second filter around coil 5401 is a common mode filter to reduce noise from the VS/VA supply and the preconditioner itself. Together with capacitors 2400 en 2401, coil 5401 works as a lowpass filter.A second common mode filter is made around coil 5402 and capacitor 2407.Resistor 3400 is a high energy VDR. The advantage of this VDR is that it can handle 380VAC without risk of fire. The mains filters are damped by a spark gap / resistor combination to prevent damage in the mains isolated power supplies of the monitor. Ground leads of the AC inlet and outlet are filtered with a toroid inductor. This is needed to fulfil EMC regulations without the need of a special and expensive filtered mains cord.Resistor 3401 discharges the X capacitors after the mains is disconnected.


5.5 Standby supply

Personal notes

5.5 Standby supply

CL 96532069_087.eps300999

STANDBY SUPPLY

GND

RE

S

RE

S

2508 4u

7

9667

100p

2507PR6

1m

2510

22u

2503

470R

3501

RESET_

MC34064P7520

3

2

IN1

2500

GNDHOT1

6505

BYV27-200

PR8

100p2506

4u7

2505

1R

3508

+5VSTBY

10R

3506

1

2

3

4

5

6

7

8

9

PR10

5500CE165T

3K9

3503

2

1

3

2501

100n

2513

GNDHOT1

7502TL431CLP

33K

3502

7501TCDT1102G

1500

9521

GNDHOT1

+5VSTB

39K

3520

6501

BZ

T03

-C

1K3521

7500TOP 210

6

4

1

2

SOURCE

N/C

N/C

DRAIN

CONTROL

N/C

N/C

CONTROL

5

3

8

7

6503

BYD33D

6502

BZ

T03

-C

PR9

+5VSTBY_SWITCHED

3504 1K

47u

2504

470R

3500

BC547B7521

6504

BYD33D

GNDHOT1

9520

PR7

4K7

3505

1 2

33n

2511

DF06M

6500

4

3

9668

+12VSB

2520

2509

100p

The standby supply is a separate power supply to reduce power consumption of the Flat TV set in standby mode. It has 2 mains isolated outputs:• +5VSTBY for the microprocessor of the monitor and to

power the ON/OFF relay in the preconditioner.• +12VSB to power the inrush relay of the preconditioner.

The AC input is applied through fuse 1500, rectified by bridge 6500 and smoothed by capacitor C2503.The stand by supply is build around the TOP Switch TOP210. The frequency is fixed to 100 kHz. The voltage is controlled by regulating the input current at pin 4 of the TOPSWITCH via the opto-coupler transistor 7501. More current means a smaller duty cycle. The 5VSTBY can be adjusted by resistor 3504. If the 5VSTBY increases, pin 3 of 7502 also increases. The current through the opto-coupler diode 7502 will increases and so the current through the optocoupler transistor 7502. An increase of the input current at pin 4 of the 7500 will decrease the duty cycle. As a result the 5VSTBY will decrease again.Diodes 6501 en 6502 are added to protect the input of the TOPSWITCH against mains spikes.


5.6 POR circuit

Personal notes

5.6 POR circuit

CL 96532069_150.eps250899

POR

>100mstime

+5VSTBY

time

>4.5V

POR will go low if the 5V-STBY is out of specification. The POR signal resets the processor (and if needed other small signal circuits) on the AV Control Board. The POR circuit is build around IC7520 (MC34064P). When starting the set the POR follows the 5VSTBY. Transistor 7521 is switched on with a certain delay defined by R3520 and C2520, and signal POR is grounded. When the 5VSTBY drops below 4.59V pin 1 7520 becomes low, transistor 7521 is switched OFF and the POR changes from "0" into "1". The microprocessor at the AV control will put the set to STANDBY.


CL 96532069_088.eps040899

PRECONDITIONER

+t

+t

+t

t

TE

MP

_PR

EC

_B

RES

TE

MP

_PR

EC

_A

PR

09

res

12R

380V

RE

S

HO

T_G

RO

UN

D

+12

VS

B2605

1u

6642

BY

V10

-40

470p

2640BY

V10

-40

6640

470R

3640

6652

BYV10-40

470R

3641

2652

2u2

PR

17

PG

ND

10

2R

D

VC

C12

VF

B3

VR

EF

1

ZC

7

3

7650

MC

3336

8

8A

GN

D

4C

OM

P

6C

S

13F

C

11G

AT

E

LEB

9

LIN

E16

MU

LT5

15N

C1

NC

214

7684

BC

557B

3606

5

1u

2604

7608

BC

369

2655

1u

3601

10R

2665

470p

2

56

100u

2663

2

56

5690

G4W

34

1

100p

2608

G4W 56

80

34

1

4K7

3685

2666

100p

330u

2615

PR

18

Vref

3650

1M3

BYD33D

6660

3680

4K7

34

5

3682

10K

0315

HE

AT

SIN

K

12

10K

3667

7660

L781

52

13

6662

3665

10K

2

3670

750K

ST

D17

N06

7681

21

36680

BYD33D

3610

3R3

1N41

486608

BY

D33

D

6661

2662

470u

6664

BYV10-40

3613

0R1

6611

BY

V29

F-5

00

3671

10K

3681

10K

10K

3654

4

2600

1n

BC

547B

7690

2656

100n

1n

2601

+5V

ST

BY

_SW

ITC

HE

D

2610

3n3

BYD33D

6681

100u

100R

3642

3663

1R

2683

1

ST

Y34

NB

5076

10

0310

-1

10K

3684

1n5

2611

1N41

48

6641

3652

1M

BYD33D

6691

2616

330u

PR

14

3602

B57

464

1R

9606

6605

1N54

06

BYV10-40

6665

1N54

06

6606

23

45

3615

0R1

3690

10K

HE

AT

SIN

K

0316

1

Vre

f

2606

1u

3600

10R

5612

100MHZ

PR

13

2653

1n

PR

12

1N41

4866

63

PR

15

BC

337-

2576

41

2

3683

10K

Vref

6600

GB

U8

41

3

2651

10n

0R1

3616

BYV10-40

6651

3651

10K

3668

1K

PR

16

2664

100u

2

13

1K

3653

BS

N30

476

40

3608

CE423D5610

1

12

13

14

15

16

2

4

6

1N4148

6654

7654

BC

557B

2654

47u

21

43

6690

BYD33D

2607

1u

CU

20

5605

6609

BZT03-C

3666

100R

0R1

3614

SIG

2

SIG

3

SIG

2S

IG1

SIG

1

SIG

3


5.7 The preconditioner

5.7 The preconditionerThe input voltage of the preconditioner is universal, between 95 V and 264 V. The output is 380 Vdc (370 V - 390 V) to the Vs/Va module with a maximum output power of 500 W (long-term average), and a peak value of max. 1000 W during 1 minute. The preconditioner does not provide mains isolation.

Starting up.

The microprocessor controls the double pole by means of signal SUPPLY ON. This signal switches indirect relay 5680 via MOSFET 7681 and so enables the use of a small low voltage switch.To protect rectifier 6600 and relay 5680 the inrush current is limited to maximum 20 A by charging capacitors 2605,2606 and 2607 through 2 serial PTC's.After approx. 0.5 sec relay 5690 is activated. This relay connects an NTC in parallel with the PTC. The advantage of using an NTC is the fact that the resistance varies with current and hence mains voltage. At high mains voltage, the current is lower for the same power.Two clamp diodes 6605 and 6606 charge output capacitors C2615 and 2616 to the peak voltage of the mains input. During normal operation both diodes are blocked because of the output voltage of 380 Vdc, and will only conduct if there is a mains spike or an output dip. Capacitor 2615 and 2616 deliver via R3668 the start-up voltage at pin 16 of IC7650. After the start-up cyclus, IC7650 is supplied via auxiliary winding 1-2. Capacitor C2663 is charged during the cycle that MOSFET 7610 conducts. While MOSFET 7610 is switched off, capacitor transfers its energy via D6661 to the input of stabiliser IC7660. The output voltage of IC7660 is 15 V and is fed via D6665 to supply-pin 12 of IC7650.The slow start function is realised by the circuit consisting of transistor 7654, D6654, R3654 and C2654.

Preconditioner-circuit

The supply IC generates pulses at pin 11 of IC7650, referred to as SIG2. Because these pulses aren't small enough, a circuit around transistor 7640 and 7641 has been implemented. The duration of the square wave is decreased by 500 nsec. Components R3640 and C2640 set this value.A current sense coil has been used to switch ON the MOSFET when there is no energy left in the transformer. This information is fed to the controller IC7650 pin 7. In this way the dissipation is very low combined with a low EMI.The rectified mains input is connected to pin 5 of IC7650 via voltage divider R3650 and R3651. This voltage is proportional with the mains input and is used to change the duty cycle of the gate-pulses at pin 11.The MOSFET is switched OFF at very high current, up to 30 A. To reduce dissipation, this is done with high speed. Turn off driver T7608 has been added to accomplish this.When there is an error in the supply the supply-IC would like to restart. To prevent this hiccup a RESTART DELAY is build in around pin 2 7650. The delay is set by R3652 and C2625 and can be adjusted up to a few seconds.Resistor 3401 discharges the X capacitors after the mains is disconnected. This is needed to fulfil safety regulations.

Voltage regulation

The output voltage (380 V) is divided by R3670 and R3671 and connected to pin 3 7650. A change of the load will adjust the duty cycle of the gate pulse at pin 11 of the supply IC to maintain the output voltage constant at 380 V. There is no need to adjust the output voltage by means of a potentiometer.

Current-protection.

The current through the FET flows also through the resistors 3613, 3614, 3615 and 3616. The voltage across these resistors are fed to pin 6 of IC7650. If the current becomes too high, then the preconditioner will turn off. A filter consisting of C2666 and R3666 avoid an unnecessary protection due to spikes.C2665 and R3665 on pin 13 determine the maximum osc. frequency.

Temperature protection.

PTC 3606is connected to the same heatsink as MOSFET 7610. If the temp of this heatsink exceeds a safety limit the resistance of PTC 3606 will increase dramatically. This increase will trigger an Opamp on the VsVa panel and this will switch the set to standby. This is done by resetting control IC7001 and IC7101 of the VsVa supply. The module is designed to operate at an ambient temperature from 0° to 45°C and with forced air-cooling. For detailed info about the temperature protection, see chapter 4.6. of the TM Monitor.



Personal notes

CL 96532069_151.eps250899

0 π/2

ûs sin ωst

π

ωst

Application

The European Law describes a reduction of Mains harmonics for apparatus with a power consumption above 75W. Only the ground harmonics are responsible for the power transfer. The power factor should be close to 1.The solution is the Pre-conditioner.

The advantages of a pre-conditioner compared to a mains input filter are:• Stable output voltage• Small• Low weight• Power factor close to 1

Out of the three basic switch mode power circuits, the upconverter was used as pre-conditioner. In the FTV1.9 an upconverter is used with discontinuous current. The switching frequency of the converter will be chosen much higher than the mains frequency (50 - 60 Hz). It is then possible to consider the supply to be constant during every high frequency period and the envelop of all voltage steps during the low frequency period approximates a half sine wave, as given in figure 7. We shall consider only one half period, in which the voltage is a sinus wave-formEvery step gives a current pulse of which the amplitude is determined by the requirement that the low frequencycomponent pulses have the shape of a half sine wave. Figure 8 shows an example.



Personal notes

CL 96532069_152.eps250899

0 π/2 π

is (ωst)

ωst

The smooth waveform between the peaks in figure 8 can be considered as the mains input current after filtering of the high frequencies. A small low pass filter will be necessary to fulfil the interference requirementsFigure 9 shows the basic circuit definition for the up-converter.



Personal notes

CL 96532069_153.eps250899

Ls

uLs

is2

is1

Us S1

S2+

+

-

Us

+

-

-

Two current values have been introduced, Is1 being the current when S1 is conducting and Is2 when the diode start conducting. The up-converter as used in the FTV1.9 is used as a semi-discontinuous mode. The MOSFET is switched on when the energy in the transformer is totally transferred to the secondary side. The circuit can be split up in 2 modesMode 1: MOSFET is conducting - Increase of the current during tonUl = Us = Ls * dI/ dt(Us = input voltage = Vmains rectified) dI = (Us * ton) / LsMode 2: Diode is conducting - Decrease of the current to zero during toffUl = (Uc - Us) * dI / dt(Uc = output voltage = 380 Vdc)dI =((Uc - Us) * toff) / LsDuring its normal operation the current increase equals the current decrease.dI (mode 1) = dI (mode 2) ton = called the duty cycle (d)ton + toff = t = switching period In both equations we find the term Ls, which can be eliminated when solving the equation.Us * ton = (Uc - Us) * toff Us * (ton + toff) = Uc * toffUc = (Us * t) / toffUc = Us / (1 - d) The output voltage of the preconditioner equals the input voltage when the MOSFET is continuous switched OFF, and increases while the MOSFET is switched ON.

38 6. VsVa supply FTV1.9DE Display Box

6.1 General

6. VsVa supply6.1General

CL 96532069_059.eps040899

GENERAL

PRE-CONDITIONER

AV-CONTROL

SUPPLIES

PDP

FANSAUDIOAMPLIFIER

PROTECTIONS

380V Vs Va 5V2Vrs Vra

Vrr

5 Vstby-sw

5 Vstby-sw

5 Vstby

5 VstbyPOR

STBY1)

TEMPPOR

PROT-FAN

DCPROD

FAN-SUPPLY

SND-ENABLE

Supply on

V+V-5 VSTBY-SW

SND-ENABLE

8V6 5V2

The supply delivers the power for the display of the FTV1.9, which includes the power for the PDP itself, the PDP LIMESCO panel, the AV controller and the audio power amplifiers, but not the standby voltage.

Block-diagram

Both Va and Vs supply circuits are based upon the LLC converter technology as usedin the power supply for MG 98 TOP.The supply consists of four parts:

The Vs voltage Is used to supply the power of the sustain pulses, which generate the light in the PDP.The voltage is set by a reference DC voltage (Vrs), coming from the PDP.Vs = 165 V + 10 * Vrs (Vrs varies between 0 and 2 V).

The Va supplyThe Va voltage is used to supply the power for driving the addressing electrodes of the PDP. The value of Va is also depending on a reference voltage (Vra) coming from the PDP. Va = 55V + 5 * Vra(Vra varies between 0 and 2 V).The Va supply also delivers several other voltages like ;• + 5 V for PDP , PDP interface panel • + 8V6 : for AV controller and video controller• +Vsnd : pos. supply for audio amplifier (+19 V)• - Vsnd : neg. supply for audio amplifier (-19 V)SUPPLY-ON signal : indicates if supplies have to switched on ; this signal is controlled by the protection circuit and the standby signal.

The FAN Supply : Provides power for the cooling fans ; controlled by fan speed control circuit

Protection-circuitry : Consists out of an O(ver)V(oltage)P(rotection) , Temperature protection , Fan potections, DC protection (Audio Ampl.) and UVLO (input undervoltage protection).

FTV1.9DE Display Box 6. VsVa supply 39

6.2 The Resonant Power Supply


CL 96532069_061.eps200799

RESONANCE SUPPLY

CONTROL-IC

CONTROLLER

30176008

30146007

FASE

+

VCC VAUX

7005

7006

FAULT INPUT SENSING

+300v

POWERBLOCK

DRIVER

FEEDBACK

T1

T2

Block diagram resonance supply

The start-up voltage for the IC is derived from one phase, the IC starts to oscillate and alternately T1 and T2 are driven into conduction with a dead time in between.This effects that via the resonance circuit and the MOSFETS energy is stored into the transformer.The secondary voltages are rectified and smoothed, these secondary voltages is via a voltage divider fed to the optocoupler that influences the oscillator frequency of the control-IC and stabilises the secondary voltages. If the current becomes too high then the supply is switched of via the fault input of the control-IC.

Advantages and disadvantages.Advantages:• High efficiency (more then 90%, other supplies 75%).• Less radiation.• Cheaper: two MOSFETS of 400 V are cheaper than one

MOSFET of 600 V.• Simpler transformer construction.Disadvantages:• Very low power stand-by impossible.• Realisation + stabilisation more complex.• Optimising is limited at this moment because of the

availability of IC and transformer.

Principle

The LLC supply is a serial resonance power supply.The coil, resistor and capacitor form a trap at the resonance frequency Fr. The impedance is frequency dependent. The smallest impedance is at the resonance frequency, at the right side of Fr is the inductive part and the left side capacitive. In principle the resonance supply could operate at the left side or the right side of the curve, but the supply works only in the right part since higher frequencies causes minor losses. The stabilisation is realised by regulating the frequency as function of the mains voltage, the load is stabilised by influencing the series-loop.The higher the frequency the lower the output power.

In practice two methods can be used:• Method 1: transformer + series coil (Lr ext) + capacitor (Cr).

This has the advantage of a better optimisation, since the value of series coil can be selected individually and the power-losses are distributed among 2 components. The disadvantage is the size/price of the transformer plus coil.

• Method 2: transformer with bad 'induction factor' + capacitor (Cr). This has the advantage of a smaller/cheaper transformer, but the disadvantage of a limited Lr and temperature rise due to dissipation

Method 2 is realised because this is the cheaper version.where Lr: leakage induction Lh: magnetic induction



Personal notesThe coil Lr is the self-induction measured with short-circuited secondary winding (=leakage-induction); thus the worse the coupling factor of the transformer the bigger Lr.The coil Lh is the total inductance of the primary winding minus Lr.


6.3 Resonant mode controller-IC MC34067


CL 96532069_062.eps200799

MC34067 Representative Block Diagram

3

12Output B

13

14

8

7Inverting Input

OscillatorControl Current

16

9

8.0V

Q2

R

C2005

R3003

C2004

R3004

R3005

Vref

4.9V/3.6V

15VCC

Enable /UVLO Adjust

One-Shot RC

Error Amp Output

Noninverting Input

Soft-Start

Fault Input

Power Ground

Output A

Vref

D1Q1

IOSC

Oscillator

One±Shot

Error AmpClamp

3.1V

Error Amp

9.0µA1.0VFault

Latch

S

RQ

Q

QT

SteeringFlip-Flop

4.2/4.0V

Vref UVLOVCC UVLO

7.0k50k 7.0k

50k

4.9V/3.6V

Vref

5.1VReference

1

2

6

11

IOSO

5

10

As control-IC the MC34067P is used for the following reasons :• zero voltage switching• variable frequency oscillator (above 1 MHz)• precision one shot timer for the dead time• 5 V reference output• double high current totem-pole output• soft-start• wideband error amplifier• fault input (protection)

The oscillator

The Oscillator circuit is build around the internal OP-comparator with 2 threshold-voltages; 4.9 and 3.6 V. C2004 is first charged via transistor Q1. If the voltage across C2004 is more then 4.9 V then the output of the upper of the oscillator comparator becomes low, the NOR-port output will be high and Q1 will be blocked because the base will be shortened by Q2. C2004 will be discharged via the resistors R3003 and the oscillator control current (Iosc). If the voltage across C2004 is below the lower threshold of 3.6 V, transistor Q1 is conducting and the capacitor is charged again. The oscillation frequency is modulated by the oscillator control current.The discharge current increases when pin3 MC34067 is loaded even more; thus the lower the voltage on pin3 MC34067 the higher the oscillator control current and the higher the frequency. The maximum frequency is reached when the output of the error amp is minimal (0.1 V). Thus R3005 determines the max freq.

The minimum frequency is reached when Iosc current is zero; C2004 then discharges only via the resistor R3003.

The one-shot timer

The one-shot timer was developed in order to deactivate both outputs simultaneously and provides a dead time so that one output will be high.The one-shot capacity (C2005) is first charged by Q1.The one-shot period begins when the oscillator comparator is switched off by Q1.The one-shot capacity is discharged via the parallel resistance (R3004); if this voltage gets lower than the lower threshold of 3.6 V the comparator will be high and controls the flip-flop, which makes one of both outputs high.If Q1 is reconducted through the oscillator comparator (for the oscillator) the one-shot capacitor is recharged.

Fault detector input

At pin 10 there is a fault detector input. If this voltage reaches 1 V then the output of the op-amp is high and both drive outputs are switched off.In addition, the output of OR3 will be high via the fault latch. The output of OR3 drives Q1 so the oscillator- and the one-shot-capacitor remain charged.Via OR3 the soft-start capacitor is discharged.



Soft start

Due to the soft-start circuit the oscillator starts with maximum frequency.The low voltage on the soft-start capacitor (C2008) is buffered and keeps the error amp. output low (Iosc = max > Fosc = max).The capacity is charged with a current of 9 µA, the output of the buffer gets high and the error amp. input takes charge of the oscillator control current.

Practical diagram

The start voltage of the IC is tapped from one phase and led to pin15 of the IC.The supply IC begins to oscillate, the voltage on pin 15 is taken over by the transfer winding (pin 1 & 2 transformer). Since the transformer has a bad coupling factor the transfer winding is tangled in the secondary, though with a triple isolated wire (TRISO).Via R3026 the Vs can be adjusted and stabilised. Via the alignment/stabilisation for Vs the output voltages are also stabilised.The Vs is fed via a voltage divider to IC 7110If the voltage at pin3 IC7110 is higher than 2.5 V a current will flow from cathode to anode. This current flows also through the secondary of the optocoupler.The voltage at pin7 of the MC34067 determines the output frequency, the higher this voltage, the higher the output-frequency. That results that in case of increasing Vbat the voltage of pin7 increases; the frequency increases and Vs decreases.When the output voltage rises, the voltage at the reference IC 7110 also rises, which causes the current through the diode of the opto-coupler to rise. The transistor of the opto-coupler conducts more, as a result of which the voltage at pin 7 MC34067 increases.The output voltage of the error amplifier gets lower, and the current through R3005 increases.

Driver stage

The two secondary windings of the driver transformer are wound in opposite directions and control the two switching MOSFET's.The primary winding of the driver transformer is alternately controlled by the two totem-pole outputs of the controller.Cross-conduction of both MOSFET's is prevented by the dead time.The gate of each MOSFET is controlled via the resistors 3014/3017 and via the diodes 6007/6008; the transistors 7007/7008 discharge the gate faster by switching off. The diodes at the basis-emitter of 7007/7008 prevent the zener-effect of these transistors. The zener diodes at the gate-source of 7005/7006 are for ESD.C2011 and C2014 form the capacity for the series resonant circuit.

Protection against overcurrent and overvoltage

The voltage at R3021 is a criterion for the current, which flows through the primary.Via C2015 and D6010 the negative information is clamped at -0.6 V.The total amplitude is rectified via D6009 and C2010 and via R3020 and TS7009 supplied to the fault input (pin 10) of the controller.When the fault input is higher than 1 V the protection is activated (= overcurrent-protection).The voltage V at R3010 is the take-over winding voltage; this voltage is also supplied to pin 10 of the controller via a voltage divider R3010/R3011 (= overvoltage protection).

Soft start overcurrent protection

If short-term overcurrent peaks occur the frequency is adapted.The voltage at R3021 is clamped at -0.6 V via C2015 and D6010.The total amplitude is rectified via D6011 and C2008 and supplied to the "capacitive" thyristor T7017/18 via R3012.When the voltage at the emitter of T7017 gets higher than 5 V, the soft-start capacitor is discharged, and the frequency increases as a result of which the Vs drop.If this voltage remains 5 V the supply is interrupted (hick-up).This circuit is adjusted in a way that the voltage does not drop too much if a flash occurs.


6.4 Voltage/current waveforms of the resonance-circuit


CL 96532069_167.eps300999

Lr

Lp

Cr

S1

S2

Vi

+

Br1

D1

D2 Cs

The total switching time can be distributed over 12 phases with different current paths.Only 4 phases are discussed to simplify the explanation.In the 4 phases we have 3 different positions of the switches.1. Switch S1 is closed, Switch S2 is open2. Switch S1 is open, Switch S2 is open ( Dead time )3. Switch S1 is open, Switch S2 is closed

Phase 1: s1 closed, s2 openThe gate of MOSFET 1 is positive which causes S1 to be closed.The input voltage Vi of 380 VDC provides a current flow through S1 and the series circuit.At the same time a current flows through the bridge rectifier in the secondary winding which charges capacitor Cs.The current through Lr starts negative, but it is increasing to change polarityCapacitor Cr is charged sinusoidal, while the voltage at Lr drops which makes the current drop.



Personal notes

Lr

S1

S2

Vi

+

Br1

D1

Cp

CL 96532069_168.eps300999

D2

Lp

Cr

Cs1

2

Phase 2: S1 open, S2 open (dead time)Both MOSFET's are not conductive.The current through the coils wants to continue. The capacity Cp releases its load to the series circuit, and the voltage at Cr continues to rise. (Cp is the sum of several parasitic capacities).The voltage at the drain of MOSFET 2 drops because Cp is discharged at this moment. This causes a voltage inversion across Lr and Lp. The secondary winding begins to feed back, charging capacitor Cs.The voltage becomes negative, and diode D2 start to conduct. The secondary bridge remains conductive.



Personal notes

Lr

S1

S2

Vi

+

Br1

D1

CL 96532069_169.eps300999

D2

Lp

Cr

Cs

Phase 3: S1 open, S2 closed The gate of MOSFET 2 is becoming high. The current through D2 is taken over by MOSFET 2. The switching losses are neglectible, due to the fact that the voltage across the switch is now approx. 1V.The current through Lr starts negative, but is increasing to change polarity. A current flows through MOSFET 2 and the series circuit. The bridge remains conductive but its current gets zero because of the decreasing voltage across Lp. This is caused by the discharge of capacitor Cr. The voltage at capacitor Cr is decreasing sinusoidal and so is the voltage across Lp and Lr.



Personal notes

CL 96532069_170.eps300999

Lr

Lp

Cr

S1

S2

Vi

+

Br1

D1

Cp

D2 Cs

1

2

Phase 4: S1 open, S2 open ( Dead time )Both MOSFET's are not conductive.The current through the coils wants to continue. The capacity Cp releases its load to the series circuit, and the voltage at Cr continues to fall. (Cp is the sum of several parasitic capacities).The voltage at the drain of MOSFET 2 increases because Cp is discharged at this moment ( Cp was charged to 380V ). This causes a voltage inversion across Lr and Lp. The secondary winding begins to feed back, charging capacitor Cs.The voltage becomes higher than 380V , and diode D1 start to conduct. The secondary bridge remains conductive.


6.5 Vs Supply

Personal notes

6.5 Vs Supply

CL 96532069_075.eps200799

Vs SUPPLY

VsOUT

CONTROLCIRCUIT

Vs

GND

HF-BRIDGE

Control is done in the usual way by a TL431 at the secondary side. Vrs is mixed into the feedback voltage using an additional TL431 (7011 at schematic FD2). Vrs , a signal coming from the display, influences the output of the Vs supply. The output voltage of the Vs supply varies between 165V when Vrs is 0V and 185V when Vrs is 2V.Accurate Overvoltage Protection is added, using a TL431 (7012) as reference/comparator and an additional optocoupler (7003) that acts on the fault input pin 10 of the MC34067P. See also TM Monitor at Ch4.6 - Protections.


6.6 Va supply

Personal notes

6.6 Va supply

CL 96532069_060.eps110899

Va SUPPLY

AUDIOSUPPLY

V+

GND AudioV-N.C.

VaOUT

CONTROLCIRCUIT

Va

8V6

GND

5V2

HF-BRIDGE

STAB.

For this supply the same design philosophy as for the Vs supply has been adopted. Main difference is the switching frequency, which is between 50 and 73 kHz (depending on actual output voltage).Vra is mixed into the feedback voltage using an additional TL431 (7111 at schematic FD1). Vra , a signal coming from the display, influences the output of the Va supply. The output voltage of the Va supply varies between 55V when Vra is 0V and 65V when Vra is 2V.Accurate Overvoltage Protection is added, using a TL431 (7112) as reference/comparator and an additional optocoupler (7103) that acts on the fault input pin 10 of the MC34067P. See also TM Monitor at Ch4.6 - Protections.


6.6 Va supply

Personal notes

Audio Supply

It is a floating symmetrical supply for the Audio Power Amplifier. Due to the fact that this voltage is tightly coupled to the Va voltage, this voltage varies considerable, between 15.0 V (full load, Va = 55 V) and 20 V (no load, Va = 65 V).The Audio ground can be connected to the normal secondary ground (ground B in the diagram) with a capacitor and a resistor in parallel, to have the possibilities to suppress spurious oscillations.

17V supply

The second output voltage serves as power supply for the 5 V down converter, supply for the Fans and several other auxiliary circuits. Also this voltage varies with Va, and the levels are identical to the Audio supply voltage. (This output is called 17 V on the circuit diagrams.)


6.7 The 5 V down converter.

6.7 The 5 V down converter.

CL 96532069_079.eps240899

5V DOWN CONVERTER

*

*

L49407203

5206

83R

GNDB

10K

3213

5202

10u

3202

10K

2224

100n

2214

100n

2u2

2203

BC557B7372

GNDB

2212

100u

8

GN

D

7OUT

5R

ES

D

3RESI

4

RE

SO

1

RO

SC

12S

ST

13

SY

NC

9

VI

14VREF

15VST

L4977A7201

6

BT

S

2

CO

SC

11

FD

BI

10

FR

C

2201

1m

2207

2n7

100R

3207

GNDB

PB

YR

745F

6203

2u2

2205

390p

2206

GNDB

22101n

1m2211

22082n

2

5207

3u3

100u

5208

1K33

93

GNDB

3203

1K

3205

15R

1n

2209

100n

2320

GNDB32

01

15K 24 5

CU20v5201

1 10 13

GNDB

2204

100u

GNDB

4K7

3206

10K

3216

3211

100K

2202

2u2

3215

10K

BZ

X55

-C6V

2

6205

GNDB

2223

100n

7202

BT

151X

-500

R

2213

100u30

99

1R

BC557B7204

3204

39K 47

0K

1N41

48

6207

3214

7205BC547B

MP4A

1103

10K

3217

3212

10K

BYD33D

6204

The required 5 V for the AV control and the PDP is made out of the 17 V. The topology is a down converter in the continuous current mode. Control and switch are incorporated in IC 7201, which is the L4977A.

It has all functionality on board, like: • Over Current Protection (at 9 A typ.)• Reference voltage, • Programmable slow start, • Programmable oscillator, • Bootstrap diode, • Reset input

This input also serves as an indication that both the input voltage and the output voltage of the converter are within the specified range. By consequence the IC gives an indication whether to power source is OK or not.The L4977A lacks one protection against short circuit of the switch inside the IC. If that happens, the output voltage becomes equal to the input voltage. In order to prevent that, a voltage higher than 5.8 V (typ.) is detected via 6205 and thyristor 7202 is fired. This thyristor will cause a fuse to blow, and the outputs of the converter will drop to zero, thus preventing the circuits that are supplied by this converter to be damaged.

The coil 5201 of this down-converter has an auxiliary winding. This voltage is rectified and the resulting voltage is added to the 5 V output voltage. Due to variations of the 5 V load this voltage is not stabilised sufficiently. So a linear voltage regulator (7203) is added. To achieve the highest efficiency it is a low drop version, that directly delivers 8.5 V (type number L4940-8V5).


6.8 Vrr delay.

Personal notes

6.8 Vrr delay.Vrr is a logical signal ("high" in normal circumstances) that comes from the PDP. Its purpose is to activate the switch- off of the supplies in case Vrr becomes "low"Vrr is "0" during start-up. So an additional circuit, around 7301, has been designed to prevent the "0" of Vrr to influence the behaviour of the supplies during approx. 3 seconds. The Vrr signal is directly fed through to the µP for fault diagnostics.


6.9 Fan control.

Personal notes

6.9 Fan control.In the monitor 6 fans are implemented. In order to decrease the fan noise as far as possible the fan speed is controlled according to air temperature.A NTC temperature sensor senses the temperature of the incoming air (Tair). Based on this temperature, the fan speed is controlled by controlling the voltage across the fans. The fans are 12 V types, which can also run on lower voltage (though that is not specified in the specification of the fans). The lowest speed is at a fan voltage of 5 V, the highest at 12 V. The sensing circuit, built around a LM358 Opamp, is designed in such a way, that at air temperature up to 25 degree C. the fan voltage is 5 V. Above that temperature the fan voltage rises linearly with temperature, and reaches it maximum of 12 V at Tair = 45 degree C. The fan control circuit is powered from the 17V. Because of the fact that this voltage is varying, a special circuit is designed. The fan voltage is clamped to 12 V, in order to prevent damage to the fans.

In order to be able to verify whether the fans are running or not, a fault detection circuit is implemented for each fan individually. Two types of fault detection are supported. The simplest way of detection is a logical signal that is low when everything is OK and high when a fault occurs. The other way is that a running fan gives pulses in the same speed as the rotation of the blades of the fan. In that case a detection has to be made whether there are pulses or not. In the circuit that is detected using detection of the rising edge of the pulse. The rising edge triggers the discharge of an elcap (C2306). The elcap in turn is charged through a resistor. When for a longer time no pulses appear, the voltage across the elcap rises above a critical level, and the protection is activated (via D6323). The actual circuit implemented is for a fan with pulses (e.g. SUNON), but provision has been made for adaptation to the other protection philosophy, by just omitting most of the components and adding a bridge wire (the PCB is prepared). The time constant is chosen such that at start-up no problems occur, while a fault is detected well within one second.


6.10 UVLO-protection.

Personal notes

6.10 UVLO-protection.

CL 96532069_077.eps180899

Under Voltage Lockout Circuit

**

*

*

*T 2A/250V

**

6024

BZX55-C6V2

6030

1N41484

6

9

5002

1

10

11

12

13

14

15

16

2

GNDAGNDA

3062

47K

3060

2M2

3063

220R

BC547B7014 3002

22R

GNDA

2001

47u

5003

150u

2002

47u

22K

3001

22K

3059

GNDA

GNDA

6001

BYV27-200

2003

1m

1N4148

6026

GNDA306156

K

GNDA

1004

5004

6u8

FD46

BYD33D

6002

6025

1N4148

7015BC547B

380 Vcc2

General: The Protections are described at Chapter 4.6 of this Training Manual : Protections.

Both Vs and Va supplies have an OverVoltageProtection (OVP). They are very accurate and use a separate voltage sensing circuit around additional TL431's. When activated a small thyristor is fired, and this in turn controls an optocoupler. The receiving side of the optocoupler is connected to the fault-input pin of the MC34067 control IC's at the primary side. The optocoupler and the thyristor are fed by the 5V standby-switched. By consequence they are latching, preventing the supplies to hickup.

Under voltage lockout circuit

In order to prevent an uncontrolled hick-up after switching off the monitor, and/or putting it into standby, an Under Voltage Lockout circuit is implemented, that prevents the functioning of the control IC by diverting the starting current (Vcc ) to ground when the input voltage is below approx. 200V. In this way the supply voltage of the IC will be below it's own UVLO. The detection is done with the circuit around T7014 and T7015.

54 7. Audio video control FTV1.9DE Display Box

7. Audio video control

CL 96532069_054.eps110899

AUDIO/VIDEO CONTROL

BUFF

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RGB

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AU

DIO

FIL

TE

RIN

G

LPF

(opt

iona

lly)

DE

LAY

15 p

oles

AV

C32

VG

A In

put

from

E-b

ox o

r PC

5 po

les

15 p

oles

1/2

AV

C35

Aud

ioO

utpu

t

3 po

lesA

VC

89T

o au

dio

ampl

ifier

7 po

les

RG

B O

UT

(3*

)

FB

OX

_MO

DE

_OU

TP

UT

SN

D_E

NA

BLE

1/2 AVC35

R_B

YP

AS

S

L_A

UD

IO_Y

C

R_A

UD

IO_Y

C

SD

A_N

VM

(2*)

SC

L_N

VM

AV

C01

to to P

DP

Lim

esco

+5V

stby

_sw

itche

d

+5V

stby

_sw

itche

d

VG

A_Y

C_M

OD

E

(*)=

NU

MB

ER

S O

F W

IRE

S

2X

FTV1.9DE Display Box 7. Audio video control 55

Personal notesThe Audio Video Control board provides the interface of the Display Box for Audio, Video and Control signals.At this panel the Audio, Video and Control (UART or DDC) signals enter the Monitor. These signals will be buffered and are available at the output of this panel for feedthrough (except the control signals). The same signals will be fed to the Audio part (including an optional audio delay to correct the timing between video and audio) and to the video control IC to control the RGB signals. Also the µP for the panel control in the Monitor is located on this board. The audio filters for the high and low/medium signals are also located on the AVC board.

The AVC interfaces the following signals:

Internal:• RGB/SYNC signals to/from PDP LIMESCO panel.• RGB/SYNC/Audio signals from YUV/YC Input panel.• Control signals (for power supply) from/to VS/VA SUPPLY

panel.• Audio signals to audio amplifier.

External:• RGB/SYNC/UART/CONFIG_IDENT and RC-5 in case of a

Receiver Box via sub_D connector.• RGB/SYNC/DDC in case of a Personal Computer via

sub_D connector.• RGB/SYNC loop-through via sub_D connector (e.g. for

additional Display).• Audio in L and R via CINCH connector.• Audio loop-through L and R via CINCH connector.

The AVC board has no predefined service position, as it is surrounded by other panels and it cannot be hinged due to the fact that the connectors are located all over the panel.Development made, for that reason, all service testpoints available at the B-side (reflow side).As the component placing is very dense, service printing was very difficult to realise. Therefore the testpoint overview of this panel, which can be found in the Service Manual, is of utmost importance in order to service this panel.


7.1 Audio signal processing

Personal notes

7.1 Audio signal processingThe audio part is divided into several sections. 1. An (optional) audio delay to correct the timing between

video and audio.2. Audio control for the source selection and volume function.3. Filters to split the audio signals in high and medium/low

frequencies and Dynamic Bass Enhancement (DBE).4. Audio mute.The output signals are fed to the audio amplifier.

Audio delay (optional)

To compensate for 'lip sync error' (the difference in time between the aural and visual perceptions), audio delay was designed in during initial development. The L/R audio input signals are delayed digitally by two IC's (7910 & 7920), which are controlled by a special M(itsubishi)-bus connected to the µP.Because the FTV 1.9 has no PALPLUS, so less delay in the video signal, this feature was not necessary. That is why it was made optional (it is disabled by using jumpers 4930 and 4931).



Personal notes

CL 96532069_043.eps110899

AUDIO CONTROL

RL

INP

UT

SE

LE

CT

OR

AUX

BA

LA

NC

E

TR

EB

LE

BA

SS

VO

LU

ME

R

R

R

L

L

L

MAIN

SCART

headphonechannelvolume

SCLSDAMAD

CONTROLIIC - BUS

AUDIOMUTE

VOLTAGE

REFERENCE

MONOFORCED

STEREOPSEUDO

L_AUDIO

L_AUDIO_OUT

AVC35

R_AUDIO_OUT

TO FILTER

R_AUDIO

L_AUDIO

R_AUDIO

STEREOSPATIAL

STEREO

R

L

L

R

(RES)

(RES)

49

31

470n

2951

49

30

2948

470n

2935

470n

470n

2915

9

18

15

26 7 20 13

6

25

2

31

1617

28

30

1

32

3

5

23 1024

39813K9

39833K9

39828K2

39848K2

298210µ

298410µ

TDA98607940 22 21

11 1229 274

19

148

470n

2949

2950

470n

Audio control

The audio input signals at CINCH connector AVC35 are directly fed to the audio control IC.The L/R_AUDIO_YC (at internal connector AVC12) signals coming from the YUV/YC Input panel are fed to this IC as well.

This audio control IC, which is I2C controlled, consists of:• an input selector for the direct L/R signals or the delayed L/

R signals (optional), • a L/R constant level signal to the audio output (CINCH

connector AVC35),• a volume control (tone control optional or via E-box) with L/

R_AUDIO output. The undelayed L/R_AUDIO signals (variable level) are fed to audio filtering part.



Personal notes

CL 96532069_044.eps140799

HPF

+8VA

8

4

LM833N7250-A3

2

1

3236

2203

+4VA

L_AUDIO(from audio control) 10n

2238

47p

3238

33K

3237

3K9

2236

15p 3205

100R

AVC89

L_HIGH To audioamplifier

Filters, DBE

The audio signals are filtered before the amplifier. There are some reasons for doing this: • it is now easy to do active filtering and • at less costs (no expensive coils and capacitors).

L/R_HIGH: For L and R separately a High Pass Filter (IC7250A & B) is processing L_HIGH and R_HIGH.The f-3dB for this filter is determined by R3237 and C2203 (for the Left channel).The output signal of this HPF is fed to the audio amplifier board via connector AVC89.For the Right channel the circuit is identical.



Personal notes

CL 96532069_045.eps240899

LPF & DBE

2202

15p 3202

1K

1K

3201

10u

2212

2206

2u2

3211

4K7

39K

3200

+4VA

100n

2204

3208

4K7

1K

3207

680n

2201

2207

10u

3205

100R

2237

10u

390R

3213

3212

1K2231

47p

2200

FromAudiocontrolL_AUDIO

680n

2234

47p

BC847B7203

7202BC847B

15p

2205

+8VA

BA

S21

6

6208

3242

10K

3209

100K

3210

330K

5

6

7

8

4

LM833N7200-B

+8VA

3206

1K

BAS216

6200

3

2

1

8

4

7200-ALM833N

+8VA

2u2

2215

L_MID_LOW

AVC89

To audioamplifier

L/R_MID_LOW and DBE:A Dynamic Bass Enhancement (DBE) circuit, with opamp LM833 and Low Pass Filter, processes the signals L_MID_LOW and R_MID_LOW: The audio signal coming from the TDA9860 enters a bandpass filter (T-filter), consisting of C2200, C2201 and R3211 in series with R3210, which is tuned at a frequency of 65Hz (the resonance frequency of the speaker). The Q-factor of this filter can be influenced by chancing the R-value. Low R means low Q, high R means high Q-factor. In this circuit, the R-value can be influenced by steering transistor T7203.The output signal of IC7200A is fed to a LPF (IC7200B) with a fixed f-3dB via R3202 and C2204. The output signal of this filter is then fed to the AUDIO AMPLIFIER board via connector AVC89 but also to a feed back loop. Here the signal is rectified by D6200 & D6208, then integrated by a RC network (load via R3208/C2206, unload via R3209/C2206) and finally fed to T7202. When the signal amplitude is high enough, this transistor drives 'diode' T7203 and thereby regulates the R-value of the T-filter by shorting R3210. This results in a low Q-factor, so a flat response around 65Hz.



Personal notes

CL 96532069_001.eps110899

DBE

HPF

LPF

DBE frequency characteristic

Hz 100K

65Hz

10010 1000 10000

MAG

However with low signal amplitudes, where you need DBE, T7203 is not activated, resulting in a high R-value (R3211 + R3210) and so a high Q-factor. The filter will now enhance the signal around 65Hz. So in this way the low frequencies are dynamically controlled.



Personal notes

CL 96532069_046.eps110899

AUDIO MUTE

BSH1037969

100K

3978

7972BSH103

BC

857B

7965

7968BSH103

BAS216

6967

R_AUDIO

L_AUDIO

BAS216

SOUND ENABLE

6968

6950

BZX284-C33BAS216

6969

+5Vstby

6970

BAS216

3953

150R4

5

6 0335-BAVC35

L_AUDIO_OUT

R_AUDIO_OUT

100K

3966

3967

100R

BZX284-C33

6951

3970

100K

3968

100K

BZX284-C336960

6961

BZX284-C33BSH1037971

150R

3958

FromAudioControl

Audio mute

The display can go from STANDBY MODE to ON and vice versa (TV-Configuration version). In order to avoid audible plop in the left and right CINCH output signals, an audio mute circuit has been implemented. The audio mute circuit is controlled by the POWER_OK (POK) signal.When the set will be switched ON, first all the power supply voltages become available. After this, the POK signal will become active, and the audio signal will be de-muted.While the POK signal is not available, the audio will be muted by the SOUND_ENABLE signal, which again is controlled by the DEMUTE signal of the µP.For the actual mute circuit, use has been made of MOSFET's to handle the rather large signal amplitudes of 2Veff. Also when there are no sync pulses available, the audio must be muted. When these pulses become available again, the de-mute sequence will be as follows: de-mute the audio amplifier by the mute pin, 5. de-mute the audio processor by the SOUND_ENABLE

signal and 6. then increase the volume stepwise to the last status value.


7.2 Video signal processing


INPUT-CLAMPINGBLANKINGCLIPPING



LIMITING

CONTRAST

TDA4885

OSD-CONTRAST

PEDST

DISO

DISVFPOL

data

CONTRAST

CONTRAST

DISO

1 2 3 4

5 11

7 9

FBL OSD1 OSD2 OSD3

fast blanking

blanking

input clamping

OSD-INPUT INPUT CLAMPINGVERTICAL BLANKING

BLANKINGOUTPUT CLAMPING

6-BITDAC I2C-BUS

REGISTER BLANKING

MODULATION

FPOL

POLARITYSWITCH

PEDESTALBLANKING

PEDESTALBLANKING

PEDESTALBLANKING

BRIGHTNESS

GAIN

GAIN

PEDST

PEDST

PEDST

HFBCLI

GND

DISV

GAIN

BRIGHTNESS

BRIGHTNESS

SUPPLY

4-BITDAC

6-BITDAC

6-BITDAC

6-BITDAC

6-BITDAC

8-BITDAC

8-BITDAC

8-BITDAC

CHANNEL 3REFERENCE

CHANNEL 2REFERENCE

CHANNEL 1REFERENCE

OSD-CONTRAST

OSD-CONTRAST

signal path 1

signal path 2

signal path 3

6

17LIM

SDA SCL12

GM1 GM2 GM3

13 14

8

10

41

2

3

13

3

5

1

2

13

12

15

14

22

VP1

VO1

FB1

VP2

VO2

FB2

VP3

VO3

FB3

VP

27

32

29

30

2831

24

25

2326

19

20

1821

14

[VGA IN]AVC32

[from MONITOR uP]VGA_YC_MODE

R

G

B

R_VGA

G_VGA

B_VGA

HS_SYNCVS_SYNC

1358

9

[from YUV-YC-INPUT]

AVC12

R_YCG_YCB_YC

HS_YC

VS_YC

7300TDA4885

7360

152

5

1

34

H

V

7370

10

5

8

18

2

7

4

1

20

[to PDP-LIMESCO]AVC02

R_VIDEO

N.C.

N.C.

N.C.

CONTRAST

G_VIDEO

B_VIDEO

R_BLACK_FEED

G_BLACK_FEED

B_BLACK_FEED

H

V

15

16

OUTPUTCLAMP

INPUTCLAMP

CL 96532069_047.eps240899

RGB CONTROL

The video part is divided into the following sections which will each be described below: 1. Source selection2. Feedback signals3. Signal loopthroughThe output signals are fed to the PDP Limesco panel

Source selection

Incoming signals, from Receiver Box or PC, are entering the Display Box via a sub_D connector (AVC32). The RGB signals R/G/B_IN_VGA are fed to a source select switch (IC7360), which selects the normal RGB_VGA or a separate RGB_YC signal, coming from the YUV YC INPUT panel.The source select output signals are fed to the high bandwidth (35MHz bandwidth @ -3dB) video control IC (IC7300) with I2C control.The RGB output signals from this IC are buffered via discrete transistors and fed to connector AVC02 which is connected to the PDP LIMESCO panel.The belonging sync pulses, HS_SYNC and VS_SYNC, are buffered via two Schmitt triggers, after which they are fed to a source select switch (IC7370) as well, which selects the HS/VS_SYNC_BUFF or the HV_YC signals coming from the additional YUV/YC Input panel.

Feedback signals

The video control IC, is provided with a black level feedback via signal RGB_BLACK_FEED coming from the gamma amplifier on the PDP Limesco panel. This to ensure proper DC-coupling between the two panels.Furthermore there is a CONTRAST control feedback from the PDP LIMESCO, which controls the Peak White Limiter.Also an INPUT and OUTPUT CLAMP pulse is required. These are also generated by the PDP LIMESCO.



Personal notes

CL 96532069_048.eps110899

RGB BUFFER

100K

3812

22n

2811

BC847B7811

3816

22K

150R

3815

8V6

4R7

3810

7810BC557B

R_LT_VGA

10u

2812

2810

470u

75R

R_OUT3813

150R

381433

0R

3811

+8VC

VGA Output

AVC36

Signal loopthrough

The same RGB_IN_VGA signals are directed via the RGB buffers (with two times amplification and 75 Ohm output impedance) to the VGA OUT connector (AVC36).The belonging sync pulses HS_SYNC and VS_SYNC are buffered as well via two Schmitt triggers in series and fed to the same sub_D connector.


7.3 Control signal processing


CL 96532069_003.eps240899

VGA_INAVC32

LED PANELAVC10

CONFIG_IDENT

DIS_RC5

UART_IN

UART_INUART_OUT

DDC/SDA

UART_IN/DIS_RC5

DDC/SDL

EBOX_PRESENT

µP

TV CONFIGURATION

The circuit consists of the Monitor Microprocessor panel, on which the µP P87C695 is located and a Non Volatile Memory (NVM), to control the AV-Control and the PDP LIMESCO panels via I2C (internal).

The control part is divided into the following sections which will each be described below: 1. Configurations2. Monitor µP panel3. Non Volatile Memory (EAROM)4. Mode detection

Configurations

There are 2 configurations possible:• TV configuration: a Receiver Box connected to the Display

Box.

Communication between the 2 microprocessors, is based on UART and not on I2C. This has been done to handle the VGA-cable length of (max ) 15 m. Via the CONFIG_IDENT pulse (3 level handshaking), which must be generated every 500 ms, the µP in the Display Box detects the presence of the Receiver Box. When there is a valid response, the UART_IN/OUT bus is selected via the EBOX_PRESENT signal. Now the Receiver Box will tell the Monitor the corresponding video mode via UART. At the same time the DIS_RC5 signal is routed to the VGA connector in order to control the µP in the Receiver Box.

• Monitor only configuration: a PC connected to the Display Box.

When there is no valid response on the CONFIG_IDENT pulse, the µP will select the DDC_IN/OUT bus (via EBOX_PRESENT) for communication with the µP (in the Personal Computer). The DDC protocol is based on the I2C protocol. The DIS_RC5 signal is now routed directly to the µP of the Monitor.



Monitor µµµµP panel

The initially chosen µP, the P87C380 had, during design progress, not enough memory capacity. Therefor a new µP was necessary. This new processor could not be placed on the AV Control board without the need for an (expensive) PWB change. Therefor it was decided to develop an 'add on' PWB for this new microprocessor (P87C695).This µP works on 3.3 Volt, so an extra power supply IC has been added on this board.Also a better accessible SERVICE MODE connector has been added (due to this extra PWB, this connector was not longer accessible on the AV control board. See also chapter 7.4).

µP input signals:• DEMUTE : signal for triggering the audio

mute circuit.• CONFIG_IDENT : detects if a Receiver Box is

connected.• FAN_PROT : becomes active if one of the fans

is malfunctioning.• POWER_OK : becomes active if all power

supply voltages are available.• POR : Power On Reset pulse. To be

sure the µP starts from an initialised status. • PRotection_STATUS : combined signal for detecting

several protections.• STANDBY : controls the power supply in case

of malfunctioning.• UART-IN : communication bus between

Receiver and Display box.• VRR :feedback signal if PDP is

switched on.

µP output signals:• EBOX_PRESENT :becomes active when a Receiver

Box (E-box) is connected.• I2C bus(ses) : for NVM, local.• LED green : status signalling.• LED red : status signalling.• UART_OUT : communication bus between

Receiver and Display box.• VGA_YC mode : becomes active when a PC is

connected.• WRite COntrol : for NVM control.

Some µP I/O pins are used to control the correct start up procedure: POK, VRR, STANDBY, SOUND_ENABLE, and one combined PROTECTION_STATUS pin for OVER_TEMP_PROT, FAN_PROT and DC_PROT.

Non Volatile Memory

Following data is stored in the NVM:

Mode detection

The VGA input related sync pulses HS_SYNC/VS_SYNC are buffered and fed to the µP for mode detection. Mode detection is done based on H/V frequencies and polarities. For the E-box mode, the FBX- or the HDIO mode (USA only), an UART command will be send from the Receiver Box to the Monitor. However when 2 Monitors are connected in loopthrough, the 2nd one must detect these modes by itself: • FBX mode can be detected by fv=60Hz, fh=32kHz, negative

H-sync (see TM AV Buffer) and positive V-sync, • HDIO mode can be detected by the fact that the signal is

interlaced.When there is no sync input, a free-running H and V frequency mode is available: 32kHz and 60Hz. This is necessary to reduce the frame flicker, to generate a stable OSD and for test picture generation.

Group Attributes

Audio Volume

Mute

Delay

Video Contrast

Brightness

Decoder Hue

Decoder Saturation

Decoder contrast

Decoder brightness

Decoder peaking

H shift

V shift

White point R

White point G

White point B

Decoder white point R

Decoder white point G

Decoder white point B

Black point R

Black point G

Black point B

Colour temperature

Aspect ratio

Video format

Last colour system

Anti ageing H position VGA

Anti ageing H position

Anti ageing V position

General Operation hours

Error codes

Service default mode

Last Source


7.4 Service

Personal notes

7.4 Service

CL 96532069_005.eps240899

ComPair

AVC39

5

6

7

8

4

3

2

ComPair DEFAULT

1

AVC39

TOPVIEW B-SIDE

5

6

7

8

4

3

2

1

ComPair

For service purposes (ComPair) there is an I2C control connector AVC34, to be used in combination with a hardware switch (jumper setting on connector AVC39) to connect this 'normal slow' I2C bus with the 'NVM' I2C bus. This is done to be able to read/write in the NVM.For detailed information on Error codes etc. see chapter PROTECTIONS.

Entering ComPair mode:1. Switch Display 'OFF'.2. Disconnect Receiver Box if connected.3. Connect ComPair cable with connector AVC34.4. Remove default jumpers on connector AVC39 and re-

connect pins 1 with 2 and 3 with 4.5. Switch Display 'ON'

Leaving ComPair mode:1. Switch Display 'OFF'2. Remove ComPair configuration jumpers: replace default

jumpers (pin 2 with 7 and pin 3 with 6 of AVC39).3. Remove ComPair cable4. Switch Display 'ON'


7.4 Service

Personal notes

CL 96532069_009.eps240899

SDM / SAM

MUP37

TOPVIEW B-SIDE

5

6

7

8

4

3 SAM

2 SDM

1

SAM/SDM

In Monitor only configuration, the display can be set to Service Default Mode (SDM) or Service Alignment Mode (SAM) by short-circuiting the relevant pins of connector MUP37 on the Monitor µP panel, or by RC5 (via the DST).SDM: short-circuit pins 2 and 7.SAM: short-circuit pins 3 and 6.

68 8. PDP LIMESCO FTV1.9DE Display Box

8. PDP LIMESCO8.1Functional Block Description

CL 96532069_111.eps270799

PDP LIMESCO PANEL

A/D TDA8714/6

Limesco uPD93687G

D-LBD

Hirose 68 poles PDP connector PD03

OSD MC141585

Gamma

PLLA: 74HCT9046

PLLD : 74HCT9046

pix divide

pix divide

pix clock (CKD)

CKD

H/V-protection (EPLD) FLEX6k

Freerun clock 4MHz.

R,G,B(d)

H/V/Nblank

R,G,B(a)

R,G,B(d) pix clock

R,G,B(d)

H/V/Nblank

LPF

H/Vok(4)

Underflow/ ADC level

black feedback(3)

23 poles PD02

R,G,B (a)(6)

connector PD01

5V(*2)

GND (*2)

3V5V to 3V

5V

5V

3.3V

5V

5V

I/O expander for mode info

I2C(3)

contrast (via Limesco)

H/V polarity change to

positive (EPLD)

EPLD filter

FTV1.9DE Display Box 8. PDP LIMESCO 69

8.1 Functional Block Description

Personal notes

The PDP LIMESCO board has to do the following tasks:• Anti gamma correction.• Digitising the RGB signals.• Converting different standards to the format required for the

Plasma Display Panel (PDP).• Add OSD information to VGA signals.This is done in different steps, which will be described below.

The RGB signals, coming from the AV-Control board, enter the PDP LIMESCO board through connector PD02. They are fed to the gamma correction circuit, which corrects the gamma for the linear plasma display (i.s.o. the non linear CRT). Then the signal passes a Low Pass Filter, which obscures some effects produced by digitising the signal. The signals are digitised by the 8 bit ADC's (Analogue to Digital Converters).Now the different standards that can be sent to the LIMESCO have to be converted to a format the PDP can understand. This happens inside the LIMESCO.The LIMESCO gives the 3 Colours, in digital format, that are ready to be processed by the PDP.

Around these main blocks, several signals, components are required to make the whole thing work:• Black feedback signals for the 3 colours in order to stabilise

the input black level coming from the AV Control board.• Underflow monitoring to adjust the black reference level of

the ADC's.• Overflow monitoring to reduce the contrast of the video

control on the AV Control board.• 2 PLL'S: one for input clocking and one for output clocking.• A 4 MHz clock intended for display protection purposes

inside the EPLD and as a freerun clock for the LIMESCO.• An OSD generator: because the monitor can be used as a

stand-alone monitor, the OSD has to be generated inside the screen and the E-box OSD generator cannot be used for this.

• I/O expander for video mode selection, bug fix, 4:3 or 16:9 selection.

• An EPLD (Erasable Programmable Logic Device): for various reasons (protection, adjustment of sync signals,...).

• Transistors 7365, 7364 and 7363 were added, see FD1, between the IC bus connections of the LIMESCO panel. When the set is put in Standby, the LIMESCO-IC has no supply. This would cause the IC bus to be drawn to ground potential resulting in an error.


8.2 Block Diagram of the PDP Limesco

Personal notes


Figure 8-1 CL96532069_094.eps

CL 96532069_094.eps041099

GAMMA CIRCUIT

2111

100n

BC847B7120

7116BC847B

22K

3115

18p

2107

+5V

a

33p

220n

2114

2120

10K

3102

7121-A74HCT04D

1

7

142

L34

+5V

a

680R

3137

2122

68p

L30

L29

68p

2100

3146

1M 1M3147

3139

2R2

22R

3111

3124

1K8

3123

1K

2116

470u

+5V

a

+5V

a

2K2

3101

22R

3106

TS9227117-B

5

6

7

8

4

2K7

3107

3100

100R

BF824

7109

BC847B7112

3p9

2102

3145

4K7

74HCT4053D

7118-B

E6

S 10Vdd16

Vee7

Vss8

Y02

Y11 Z 15

7108

BF824

6p8

2104

+5Vc

3K3

3108

+5V

a

3444

270R

330R

3113

BC847B7104

3128

2K2

BF8247111

2106

100n

L23

3458

4K7

2105

39p

2117

220n

9

7

148

3141

120R

74HCT04D7121-D

7124BC858B

150R

3120

3112

100R 1K3118

3116

2K2

4K7

3125

3121

1K

+5Va

15p

2103

1K3122

6E

9S

16Vdd

7Vee

8Vss

5 Y0

3 Y1 4Z

7128BC847B

7118-C

74HCT4053D

7100

BF824

7102BC847B

330R

3105

+5V

a

5100

0u68

2115

220n

+5V

a

3410

1K

4K7

3144

180R

3119

3129

5K6

BC857B7115

4p7

2121

BC847B7127

3127

1K

1n 2018

470R

3110

0u47

510510

p

2101

3126

1MBF824

7101

12K

3138

7110

BF824 LOW PASS FILTER

Gamma Correction (See diagrams PD2, PD3, PD4 of Service Manual)

Unlike a CRT, a plasma display has a linear 'light output versus input voltage' characteristic.Because all the input signals are gamma corrected for use with a CRT, we have to make an anti gamma amplification to make the input signal linear again with the light output.As an example we take the RED Video signal path. Two resistors mainly determine the gamma of this circuit: R3106 and R3111.

The RED signal flow is as follows:1. R-Video signal enters at T7102.2. Amplification by T7109 and T7110.3. Buffers T7111 and T7115.4. Then it passes the low pass filter5. Amplification by T71166. Entry in ADC



Personal notes

Noise Insertion

Because of the limited number of grey levels that can be displayed, dithering is done. This happens with a certain algorithm (Floyd-Steinberg) which produces a time stable pattern. This is visual very annoying. To obscure this effect, some noise is added to the signal, so that the regularity is out of the pattern (every field will have another pattern). This makes it less visible. The amount of noise is smaller than 1 LSB.The noise signal is generated in the EPLD and added in the gamma amplifiers.

Low Pass Filter

This filter serves as an anti-aliasing filter to obtain optimal picture sharpness. For the high-resolution modes, a higher sample frequency is used. When we use a lower sample frequency, we have to limit the bandwidth to avoid aliasing problems when digitising the signal.Therefore, in an earlier design phase, a switchable filter was used with two possible cut-off frequencies: 13 and 22 MHz.The components that form this anti-aliasing filter are L5100 and L5105 together with C2104, C2120 and C2121 for the higher frequency of 22MHz. The switching is done by the EPLD via signal lines 7350_P112 and 7350_P15, depending on the detected standard.In the final version of the FTV1.9 however, the decision was made to use a filter with a fixed cut-off frequency of 18 MHz.



CL 96532069_166.eps011099

Limesco (PD)AVC

1

1

1 2

2

2 2

2

2

2

1

gamma circuit ADC

VRB PWL

EPLD

Limescovideo controllerTDA4885

Black level adjat inputside

2 Black level adjat outputside

3 Aplification adjustments

R

G

B

R digital R

3131

17 31

clamp

clamp

3x8 bits

contrast

(peak white limiting)

H-white

noise

opamp7117-A

(lim)

(every field)

underflowred

30

25

20

H-black-loop

(every line)

output dither

underflow red

3

R-black-feed(every field)

adj gainampl (internal)

via 7117-B

Stabilisations

Three automatic adjustments are performed in the gamma corrector:1. Black level adjustment at the input side. Working with a

CRT, the GFL has a built-in cutoff stabilisation. The same principle is used here: the offset of the amplifier is adjusted so that the feedback voltage during the measuring pulses remains constant (R_BLACK_FEED for red). This is done once every field.

2. Black level adjustment at the output side. This makes sure that the black level (measured between every line) corresponds with the 'zero' of the ADC (TDA8714T/6). Every line, the H_BLACK_LOOP signal from the EPLD becomes active. Then the underflow bit is used to adjust the ADC offset. When the underflow (pin 11) is low, VRB (pin 4) will increase because of the integrator (around OpAmp 7117-A) until the VRB level is higher than the black level. Then the underflow output will go high, which causes VRB to decrease slowly. Thus, the VRB level will follow the black level. However, if we didn't take precautions, this loop could produce oscillations because the adjustment is yet too hard. To soften this up, an OUTPUT DITHER signal is added. This makes the output of the OpAmp increase or decrease less fast so that the underflow bit changes less frequently. Normally the variation of VRB is a couple of tenths of a Volt.

3. Amplification adjustment. Because of spread and temperature influence, the gain of the gamma amplifier may vary. Every field, the EPLD, will toggle the H_WHITE signal.

This inserts a measuring pulse in the gamma amplifier and sets the feedback loop around OpAmp 7117-B on (integration). This will adjust the gain to keep the output of the adjustment pulse constant.



Personal notes

CL 96532069_095.eps270799

AD CONVERTERS

NC

OVERFLOW

TTL OUTPUT

LATCHUNDERFLOW

OUTPUTSTTL

LATCHESCONVERTER

AD

CLOCK DRIVER

PD1/PD7

+5V

a

3131

10K

2110

220n

L31

L33

L32

O|UF 11

VCCA

7VCCD

18

VCCO1 19

VCCO2 21

VI8

VRB4

VRT9

CLK

16

D0 2

D1 1

D2 24

D3 23

D4 15

D5 14

D6 13

D7 12

DGND

17 3 5 10

OGND

20

7123TDA8714T/6

AGND

6

CEn

22

3135

22R

47n

2109

6u8

5102

+5V

a

3406

680R

3447

2K2

3439

10R

3403

1K2

100R

311721

08

100p

+5Vd5101

6u8

+5V

a

2112

220n

3133

3K3

L24

L26

1K3143

6K8

3136

+5V

a

6

S11Vdd

16

Vee7

Vss8

Y0 12

Y1 13Z14

2113

220n

74HCT4053D

7118-A

E

L25

+5V

a

3134

12K

3130

4K7

BC847B7122

2373

220n

+5Vb

3411

1K

4

L27

L28

7117-ATS922

3

2

1

8

AD Converters

3 ADC's (TDA8714T/6) are used to digitise the RGB signals. On pin 8 the signals enter the converter. 256 levels are possible (8 bits) between the VRB (pin 4) and the VRT (pin 9) level. The input clock is connected to pin 16.

The converter produces an under/overflow bit. It is used in 2 ways:• Black level reference setting (see before).• Peak White Limiting: When the incoming signal for the ADC

becomes too high, the over-/underflow bit is set. To distinguish whether it is over- or underflow, this bit can be 'AND-ed' with the most significant bit. When this outcome is true, we have an overflow. This is done for every colour and afterwards, the three signals are 'OR-ed'. This result is used to reduce the contrast in the video controller on the AV board. Signals UNDERFLOW_RED, UNDERFLOW_GREEN, UNDERFLOW_BLUE are led to the LIMESCO, which performs the AND - OR operation. The outcome of this is led to the EPLD, which generates the signal 'CONTRAST' to reduce the contrast.


8.3 Line Memory Scan Converter ( Limesco ) and OSD

Personal notes


CL 96532069_096.eps040899

PIXEL FORMAT

852

480

LIMESCO Pixel Format

The PDP does not accept horizontal line sync frequencies above 35.7 kHz or vertical sync frequencies > 72 Hz. Therefore, to display these standards anyway, we convert them to a fixed format acceptable for the PDP.In the FTV1.5 we were more restricted concerning the amount of displayable standards.In the FTV1.9 the number of standards that can be displayed has increased through the use of the LIMESCO ( item 7320 ). This IC maps different VGA standards (like VGA, SVGA, and XGA) to the standard of the PDP, which is 852x480 pixels.However, we are still bound to standards with a field frequency between 48 and 72 Hz.The LIMESCO expects 8 bit values for R,G,B and horizontal and vertical sync signals. The 3 colours are supplied through buffers. The sync signals come from the EPLD.At the output, the 3 colours are provided as 8 bit digital signals, with the correct timings for the PDP.The horizontal and vertical sync for the PDP are first passed to the EPLD, which performs some adjustments to them because they are not always according to the spec of the PDP.


CL 96532069_097.eps040899

OSD GENERATOR

CI 2 DATA RCVR

RESET

VERTIC CTRL

HORIZONTALCONTROL

SY

ST

EM

LO

GIC

CO

LOU

R D

EC

OD

ER

BC847B7361

+3V3a4M

7352C

ST

100R

3371

L65

5325

100MHZ

3418

100K

+5Vd

3378

1K

7360BC847B

L71

220n

2355

1K3391

L63

L64

+3V3a

5323

100MHZ

L69

L68

L67

L70

L66

L81

10K

3377

3390

1M

L73

L723372

100R

VGA30

VSYNC38

VDD01

VDD120

VDD240

27PWL

REFCLK34

OFB26

OFG25

OFR24

LG02

LG13

LG24

LG35

LG46

LG58

LG69

LG710

LR5

LR6

LR7

HEXT33

HPLLA28

HSYNC39

LB011

LB112

LB214

LB315

LB416

LB517

LB618

LB719

GND213

GN

D22

GN

D23

GND321

GND423

GND531

HBLKA36

HCLMPA37

HCMPA29

FREERUN35

GND17

CKA32

CKS22

L74

uPD93687GD-LBD+5Vd

220n

2353

L80

L76

L77

L78

L79

VDD3

11

VSS1

1

VSS2

16

VSYNC_10B 13

FBKG 12

G 14

HSYNC_5

NC3

PIX-IN2R 15

RESET_6

SCL8

SDA7

4

VDD1

9

VDD2

7327MC141585

10K

3393

10u

2372

220n

2334

11A

21Y

32A

42Y

53A

63Y

94A

84Y

115A

105Y

13 6A 126Y

7

GND

14VCC

735374LVU04D

L75

+3V3a

2335

220n



Personal notesOSD Generator

Also, the RGB signals from the OSD generator ( 7327 ) are fed to the LIMESCO ( 7320 ) to be mixed with the output signals.

Synchronisation and reference clock

IC7353 (74LVU04D) is used for 2 functions:1. A free running 4 MHz, back-up clock that serves as a time

reference. A 4 MHz crystal is connected at pin 1 of IC 7353. This signal is inverted twice and led to pin 34 of the LIMESCO. This time reference clocks two counters: one for field protection and one for line protection. When horizontal or vertical frequencies are too fast or too slow, the EPLD will construct a new sync. This sync-pulse is asynchronous with respect to the incoming synchronisation signals. The image will therefore not be stable.

2. Synchronisation of the input clock and the output clock. During MODE change the input-clock is shorted to the out-put clock, which both work at a different frequency, by transistor 7360 and 7361. If this is not done it could be possible due to bug in the LIMESCO, that the addressing of the internal registers goes wrong.


8.4 PLL

Personal notes

8.4 PLL

GND

PLL

BC847B7362

C1B7

COMPI3

DEMO10

1 8

INH5

PC1O|PCPO2

PC2O13

R111

R212

RB15

SIGI14

VCC

16

VCOI9

VCOO4

220n

2333

731174HCT9046AD

C1A6

+3V3

7314-A74LVCU04D

1

7

142

L94

L91

2303

330n

8

7313-D74LVCU04D

9

7

14

330n

2304

14VCC

733074LVU04D

11A

21Y

32A

42Y

53A

63Y

94A

84Y

115A

105Y

13 6A 126Y

7

GND

74LVCU04D7313-E

11

7

1410

74LVCU04D7313-A

1

7

142

18K

3324

100MHZ+5Va

22R

3321

2322

220n

5306

7313-B74LVCU04D

3

7

144

74LVCU04D7314-D

9

7

148

2330

8p2

2324

47n 68p

2327+3V3

13

7

1412

470R

3320

7313-F74LVCU04D

BC857B7315

150p

2326

3323

22R

146

56K

3318

7314-C74LVCU04D

5

7

7312PMBF170

8p2

2329

11

7

1410

100MHZ

5315

7314-E74LVCU04D

74LVCU04D7313-C

5

7

146

L90

L93

1M3361

2370

220n

7319BC857B

8p2

2328

144

L92

5314

100MHZ

74LVCU04D7314-B

3

7

1M3326

220R

3322

74LVCU04D7314-F

13

7

1412

3330

47R

CL 96532069_098.eps240899

PLL

PHASE DETECTER VCO BUFFER INVERTER

For the pixel clocks, 2 PLL's are used. The PLL around 7311 used as an example, consists of :• a phase detector (inside 7311 )• a loop filter (resistor and 2 capacitors)• a Voltage controlled oscillator (ring oscillator around 7313)• a divider (inside the LIMESCO)

It is important that the PLL has little jitter (phase noise). Otherwise this would reduce the sharpness of the picture. Critical components for the jitter are the VCO and the phase detector.Therefore we do not use item 7311 on its own (it contains also a VCO), but we use the phase detector from it and build a VCO around 3 MOSFET inverters ( 7313 ).The current consumption of the inverters is proportional to the oscillation frequency. Therefore we convert the voltage of the phase detector to a current with a MOSFET and a PNP current mirror.A capacitor of 150pF is added to provide the switching transients of the inverters.


8.5 LOGIC CONTROL AND I/O

EPLD

1D

C1

EN

1D

C1

EN

NC

NC

INTERRUPT

EP

LD-7

350

LOGIC LP FILTER

INPUTFILTER

I2C BUSCONTROL

POWER-ONRESET

I/OPORTS

SHIFTREGISTER

8 BIT

1D

C1

EN

L107

L106

220n

2377

+5Vd

3392

1K

11

2

GND10

1

19

VCC20

7355-AN74F574D

2358

220n

100MHZ

5327

2360

220n

+5V

d

+5Vd

+5Vd

L117

20VCC

N74F574D7355-C11

4

10GND

1

17

100MHZ

5331

8

9

7

6

4

5

22

23

24

25

26

27

28

29

3

30

31

32

33

14

143144

15

16

17

18

19

2

20

21

13

11

12

1

10

EPF60167350

3369

47R

3367

47R

L118

L112

L113

L114

L115

L108

L109

L110

5326

100MHZ

3416

1K

6u8

5329

L103

4

56

89

11 13

OE7

VCC1

23

VCC2

27

17 18 19 20 21 22

24

3

25

2628

2930

32

7307EPC1441

CS_10

DATA31

DCLK2

GND

12

1

14 15 16

2356

220n

1K 3451

L99

L104

L105

L102

10

P6 11

P7 12

SCL14

SDA

15

VDD16

VSS8

7351PCF8574AT

A01

A12

A23

INT_13

DCLK

SCL

SDA

P0 4

P1 5

P2 6

P3 7

P4 9

P5

L111

L116

47R

3368

3387

100R

EPC14417357

6CASC_

4CS_

1DATA

2DCLK

5GND

3OE

8VCC1

7VCC2

100R

3386

+5Vd

+5V

d

10

1

18

VCC20

7355-BN74F574D

11

3

GND

CL 96532069_099.eps270799


8.5 LOGIC CONTROL AND I/O

EPLD

A FLEX6016 EPLD ( 7350 ) is used for different functions to improve performance, correct timings, ...:• Protect the frequency of the Hsync and Vsync :• The spec of the PDP indicates an absolute maximum of

35.7kHz for the horizontal sync and 72Hz for the vertical sync. For reason of protection, the EPLD will construct a sync signal within specification of the PDP when Hsync or Vsync is to low or high. The image will then not be synchronised with respect to the incoming sync signals, and therefore not stable.

• Ensure valid timing for horizontal , vertical sync signals and N-blank signals coming from the LIMESCO. These signals are not always according to spec, so the EPLD corrects that.

• Positioning of H-sync for 16:9 modes.• When the LIMESCO grabs only 640 pixels, these pixels

could be used to construct a 4:3 image, if sidepanels were added. The LIMESCO cannot produce the correct timing for this event. Therefore, the LIMESCO is forced to produce 900 pixels at the output side, and told that 260 pixels are flyback. The LIMESCO will then fill the flyback with the colour that is set inside certain registers. What the EPLD has to do is to move the Nblank to the correct position so that part of the flyback is used as if it were active data.

• Noise generation for the gamma amplifiers. By means of two linear feedback shift registers, the EPLD produces random noise. This noise is added in the gamma amplifiers to obscure stable dither patterns and to improve grey scale tracking.

• Generation of clamping and measurement pulses for black, white and cut-off measurements.

• Pulses to activate the feedback loops for input clamping, output clamping and gain adjustment are generated in the EPLD. Input clamping is adjusted once a frame, output clamping every line, and the gain once a frame (and takes 3 line-times).

• VCR behaviour improvement. The Vsync signal coming out of the feature box during feature box modes is not what it should be. Especially during VCR feature modes this can cause the PDP to flicker annoyingly. In the EPLD, the Vsync signal is sent through a low pass filter to reduce that problem.

• OSD clock generator and positioning. The sync pulses and a pixel clock is generated for the OSD generator (MC141585DW). To make the position of the OSD independent from the video mode, these pulses have to be changed. This is done by the EPLD.

• LIMESCO bug : during conversion modes, there will be a phase jump at the end of a field. This disturbs the output PLL, which in turn disturbs the LIMESCO, resulting in a shifted picture. To prevent this, the output PLL loop is opened for a few lines during vertical flyback.

IO EXPANDER

A PCF8574AT is used to decode information on the video-mode.The meaning of the bits is as follows :P0 : aspect ratio : is used to adjust the sync in 4:3 modes.

4:3 ==> 016:9 ==> 1

P1 : video mode bitP2 : video mode bitP3 : video mode bitP4 : video mode bitP5 : CKD bit : is used for a bugfix of the LIMESCO. Before changing registers DIV or FIL in the LIMESCO, this bit should be pulled low. Afterwards, it must be set high again.P6 : UndefinedP7 : Undefined

The video mode bits ( P1 - P4 ) are encoded as shown in table below :

This information is used by the EPLD.

Mode name Resolution P4 P3 P2 P1

VGA350 640 * 350 0 0 0 0

VGA400 640 * 400 0 0 0 1

VGA480 630 * 480 0 0 1 0

MACVGA 640 * 480 0 0 1 1

SVGA 56Hz 800 * 600 0 1 0 0

SVGA60Hz 800 * 600 0 1 0 1

XGA 56Hz 1024 * 768 0 1 1 0

XGA 60Hz 1024 * 786 0 1 1 1

FBX 840 * 480 1 0 0 0

HDIO 1920 * 1080 1 0 0 1

80 9. Audio amplifier FTV1.9DE Display Box

Personal notes

9. Audio amplifier

CL 96532069_089.eps260799

AUDIO AMPLIFIER

Compared to the FTV1.5, the audio amplifier module has been moved from the E-box to the Monitor.The module is derived from the GFL-ECO-amplifier module. The actual panel contains only two amplifier-IC's, a mute and a protection circuit.The audio input signals L_HIGH, L_MID LOW, R_HIGH AND R_MID LOW originate from the AV control panel.The source for the amplifier can be the audio signals from the SSP (regulation and signal switching), or the sound circuit in the Monitor.The supply voltage of the output amplifiers is symmetrical (+16 V and -16 V). Therefore the outputs from the amplifiers are connected directly to the loudspeakers and as a result during normal operation the signal contains no DC components.If a DC-voltage exists on one of the outputs of the amplifier IC's (e.g. an IC is faulty) as a result the DC_PROT line becomes high and causes the VsVa supply to switch off the supply voltages.This protection can be overruled by unplugging connector A20.

The sound can be muted in various ways in the output amplifiers:• When the supply voltages becomes less than +/- 6 V the IC

will automatically interrupt its non-inverting input. The IC therefore automatically suppresses unwanted signals when switching on or off.

• The mute can also be activated externally (active = low) via the SND_ENABLE line originated by the microprocessor at the AV control panel.

FTV1.9DE Display Box 10. LED panel 81

Personal notes

10. LED panel

LED PANELFRONT I/O

E-BOX (partial)

AV15 LE15JST B03B-EDM-WH JST B03B-EDM-WH

3 fold

CL 96532069_157.eps250899

START-UP CIRCUIT

The LED Panel Display contains a red and green bi-colour LED to indicate the state of the monitor, a RC5 remote control receiver and some additional required discrete electronic components.The bi-colour LED is used to indicate the state of the monitor. The colours of the LED are red or green, and orange when both red and green is on.The remote control receiver enables one-way interaction between the user and monitor by infrared RC5 signals.The switch panel is interconnected between the LED Panel and the AV Control Panel.Figure below shows the functional block diagram of the LED Panel Display.The LED is activated by two logic input signals 'GREEN_LED' and 'RED_LED', coming from the AV Control Panel. Both signals must be low active what should be implemented in software. The logic signals are converted to steady currents to enable the LED to emit light. When both red and green light (=orange light) is desired, the total LED current will be twice every single colour current.The RC5 receiver is used for reception of IR remote control signals. The received signal is led to the Monitor microcontroller.

82 11. Switch panel FTV1.9DE Display Box

Personal notes

11. Switch panel

Soft Switch

+5VSTBY_SWITCHED+5VSTBY_SWITCED_RELAIS

+5VSTBYGND

DIS_RC5LED Green

LED Red

+5VSTBY SWITCHED

GNDDIS_RC5LED GreenLED Red

1234567

CL 96532069_159.eps250899

START-SWITCH PANEL DISPLAYUP CIRCUIT

The Switch Panel Display contains a soft-switch to turn the monitor ON and OFF and two connectors. One connector is going to the LED Panel Display, the other one to the AV Control panel.The Monitor can be turned ON and OFF by using the soft-switch, which interrupts the +5V-Standby line.Figure below shows the functional block diagram of the Switch Panel Display.The soft-switch is a 'low power_dual pole_two position' switch which interrupts the power line '+5V STBY' into '+5VSTBY_SWITCHED' and '+5VSTBY_SWITCHED_RELAIS'. A dual pole switch is used so the relays inside the monitor cannot get unwanted supply from other parts of the Monitor electronics.

FTV1.9DE Display Box 12. YUV / YC input 83

Personal notes

12. YUV / YC input

YUV / YCInput Panel

PDP LimescoPanel

AV-ControlPanel

RGBHV

RGBHV+LR

PDPRGBHVRGBHV+LR

YUV / YC / CVBS / LR

I2C+5V / +8V

YUV / YC Input

VGA Input

CL 96532069_160.eps250899

START-UP CIRCUIT

The YUV / YC Input panel can be present in the display cabinet of the FTV 1.9 Eco. This board gives the possibility to attach several video formats to the stand-alone display. It also has one stereo audio connection.

The input video signals are: • YUV on CINCH (Y, Cb, Cr)• YC on Hosiden connector (SVHS)• CVBS on CINCH• CVBS on BNC

The input audio signals are: • Left and Right audio on CINCH.

The board is designed to handle 1fh video-input signals. The output signals of the board (RGBHV+LR) go to the AV-Control panel that controls (among other things) the inputs of the display. From the AV-Control the signals go to the PDP LIMESCO panel which processes the video and uses line doubling to display the 1fh signal on the 2fh display. Figure 1 shows schematically how the panel is a part of the Monitor. It is placed on the back of the display with the possibility to connect the plugs from the outside world. From there on the signals (RGBHV+LR) go via the AV-Control board to the PDP LIMESCO which processes the signals for the PDP itself.

84 12. YUV / YC input FTV1.9DE Display Box

12.1 Circuit description

CL 96532069_161.eps250899

Cb

CVBS2CVBS1

CombfilterSwitch

Y,Cb,Cr toRGB

matrix

Crystal-Select

BimosTDA8854

Yswitched

YS-Video

Ycombed

Cswitched

Ccombed

CS-video

Ycomponent

Y

Cr

R

BG

R

BG

Y/CVBS(ext) Y CR G B(in)

P6(YC_switch)

SCL

SDA

LR R

L

H

V

P4(Crystal select)

SDASCL

I/O expander

P0 P1 P2 P3 P4 P5 P6

P1 / P2 (CF_Sys1 / CF_Sys2)

P3(CF_Bypass)

P0(CF_Input select)

audio

Yin

Vin

Uin

Yout

Vout

Uout

Hsync /Sandcastle /

RGB blanking

Hout SCin RGB-blanking

vert. Sawtooth

FTV1.9DE Display Box 12. YUV / YC input 85


In the block diagram of Figure 2, a simplified view is given to explain the functionality of the board. The heart of the board is a TDA8854: the BIMOS one chip TV. The main function of this IC is to convert YC into RGB signals and it also gives the possibility to adjust the video, like saturation, contrast and peaking. The Y/C input is via a switch (YC-switch) connected to the TDA8854. A 2D-comb filter TDA9181 processes the two CVBS input signals and converts them to Y and C components. Then via the mentioned switch the signals are led to the TDA8854. The colour difference signals YUV (component video) are converted to RGB video by a discrete circuit. These RGB signals are led into the TDA8854 as well. The H and V synchronisation signals are derived from the Y output of the TDA8854. Also here the sync is removed from this Y output and led back to the IC. This is done because the LIMESCO uses the time during the sync pulse to adjust its black level.

The panel is designed with 2 or 3 quartz crystals to enable global use of the display. Systems that are implemented are the following.• PAL / SECAM (Crystal frequency: 4.433619

MHz)• NTSC (Crystal frequency: 3.579545

MHz)• PAL M (Crystal frequency: 3.575611

MHz)

Left and Right audio is not processed on the panel and led immediately from the CINCH input connectors to the AV-Control Panel.

TDA8854 BIMOS TV PROCESSOR

The TDA8854 BIMOS TV Processor is chosen for this panel because of the following properties:• Y / C input.• Y input is also usable for CVBS (SECAM).• RGB input.• RGB output.• Multi-standard.• I2C controllable.• Small package (QFP64).

The TDA8854 also processes the video attributes like:• Brightness range 0..63• White point• Peaking• Saturation range 0..63• Contrast range 0..63• Hue (NTSC only) range 0..63

COMB FILTER TDA9181

The comb filter is used to separate luminance (Y) and chrominance (C) signals out of a CVBS video signal. The TDA9181 is chosen because of its following properties:• Multi-standard.• Good quality Y / C separation.• Input switch for two CVBS inputs.• Alignment free.• Almost no external components needed.

YUV COMPONENT VIDEO (Y,CB,CR) TO RGB MATRIX

The Y, Cb, Cr to RGB matrix converts YUV component video (Y, Cb, Cr) to RGB video. The RGB signals will be connected to the TDA8854. The Y signal is also directly connected to the TDA8854 for synchronisation.

The Y, Cr, Cb signals are NOT directly connected to the Y, U, V inputs of the TDA8854 because:• The signals Y, Cb, Cr are not the same as Y, U, V of the

TDA8854, so a conversion should always be made.• An extra three-fold switch would be necessary to switch

between YUV out of the TDA8854 and the converted Y, Cb, Cr signals.

Used is the NTSC standard: 0.714 Vb-w (0.714V video + 0.286V sync = 1Vpp)

Input signals (YUV):• Y = 0.7 Vb-w • U = Cb• V = Cr

Output signals (RGB):• R = Y + 1.402 * Cr• G = Y + 0.714 * Cr - 0.337 * Cb• B = Y + 1.772 * Cb

CRYSTAL SELECTION

The board contains 3 crystals to be able to handle PAL, NTSC and PAL M colour standards.Normally the TDA8854 can handle only one or two crystals. With some additional electronics three crystals can be attached. On one pin of the TDA8854 two crystals are connected and one of them can be selected with control line P4: CRYSTAL_SELECT.In the NVM of the Monitor the last detected system per source will be memorised. This will increase the speed of the recognition of the colour system when a certain source is selected. If the colour system is not recognised the TDA8854 will search in 'own intelligence'-mode for the appropriate system. In a three-crystal version the CRYSTAL_SELECT line must be altered if none of the first two crystals is the right one.

86 12. YUV / YC input FTV1.9DE Display Box


Personal notes

CL 96532069_162.eps250899

IO EXPANDER

Functionblock

Schematicsname

Function P7 P6 P5 P4 P3 P2 P1 P0

YC 0YC orCVBS 1/2inout switch

YC switchCVBS 1/2 1

PAL + SECAM +NTSC

1Crystal select XTAL_sel

PAL + SECAM +PAL M

0

SECAM(No combing)

1 X X

NTSC 0 0 1PAL 0 1 0

Comb filter CF_BypassCF_SYS1CF_SYS2

PAL M 0 0 0CVBS 1 (cinch) 1CVBS input CF_inpselCVBS 2 (BNC) 0

IO EXPANDER - PCF8574AT

The user controls the display with a remote control and toggles manually through the source loop. The IO Expander is addressed via the I2C bus with signals coming from the microprocessor. The IO expander controls the settings of the comb filter, the YC switch and the crystal selection.The table below gives a description of the output lines P0-P7and their function.The signals to control the comb-filter (TDA9181) are: CF_BYPASS, CF_SYS1 AND CF_SYS2 , which select the SECAM, NTSC or PAL system.The signal to select the YC input or the CVBS-1 or -2 input is YC_SWITCH. This signal is the select-input for IC7010 that selects either the YC-signal of the Hosiden SVHS or the YC combed output signal from the TDA9181. The selection between CVBS 1 (CINCH) or 2 (BNC) is done by switch-signal CF_INPSEL.Switch signal XTAL_SEL selects one of the crystals, which are connected to pin 51 of the BIMOS.

Documents

Philips ftv1.9de_training manual