PGA450Q1EVM User’s Guide - TI.com4 Jumper Settings There are several jumpers and 0-Ωresistors located on the board, which are used to configure the connections to the PGA450-Q1

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Copyright © 2012–2015, Texas Instruments Incorporated

PGA450Q1EVM User’s Guide

User's GuideSLDU007C–March 2012–Revised November 2015


This user’s guide describes the characteristics, operation, and use of the PGA450Q1EVM. An EVMdescription, GUI description, interface requirements, and complete schematic are included.

Contents1 Read This First ............................................................................................................... 22 EVM Overview ............................................................................................................... 23 Power-Supply Requirements and Connections.......................................................................... 4

3.1 Power Supply........................................................................................................ 43.2 Controlling and Powering the PGA450Q1EVM via the USB Interface Board............................... 43.3 Connecting the Transducer........................................................................................ 4

4 Jumper Settings.............................................................................................................. 54.1 Jumpers .............................................................................................................. 54.2 Default Jumper Settings ........................................................................................... 54.3 0-Ω Resistors........................................................................................................ 5

5 Socket for Programming OTP.............................................................................................. 66 Transformer and Transducer............................................................................................... 67 PGA450-Q1 Communication Interfaces .................................................................................. 7

7.1 SPI .................................................................................................................... 77.2 LIN .................................................................................................................... 77.3 UART ................................................................................................................. 8

8 Controlling the PGA450-Q1 Memory Spaces With the GUI............................................................ 98.1 Using the Register Grids to Manipulate the Register Spaces ................................................ 98.2 ESFR Registers ................................................................................................... 108.3 EEPROM Registers ............................................................................................... 108.4 RAM................................................................................................................. 108.5 OTP ................................................................................................................. 108.6 DEVRAM ........................................................................................................... 138.7 FIFO/ECHO ........................................................................................................ 14

9 LIN Master................................................................................................................... 1610 Keil uVision Settings for Programming Firmware to the PGA450-Q1 DEVRAM or OTP Memory .............. 17

10.1 Objective............................................................................................................ 1710.2 Setup................................................................................................................ 17

11 Use Case .................................................................................................................... 1911.1 Evaluation Through SPI Communication....................................................................... 1911.2 Monitoring the Signal Path ....................................................................................... 20

12 PGA450Q1EVM Schematics and Layout Drawings ................................................................... 22

List of Figures

1 PGA450Q1EVM Setup...................................................................................................... 42 Transformer and Connector for the Transducer ......................................................................... 63 Equivalent Circuit of Transformer-Transducer Sensor Pair ............................................................ 74 LIN Master Transceiver ..................................................................................................... 75 RS232 Transceiver .......................................................................................................... 86 Loading a .HEX File Into the GUI ........................................................................................ 117 OTP Memory Successful Programming Verification................................................................... 12

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Read This First www.ti.com

2 SLDU007C–March 2012–Revised November 2015Submit Documentation Feedback



8 OTP Memory can be programmed while programming the Development RAM................................... 139 Echo Data Stored in FIFO RAM Plotted in Excel ...................................................................... 1410 LIN Master on GUI ......................................................................................................... 1611 DEVRAM Target Options ................................................................................................. 1712 OTP Target Options ....................................................................................................... 1813 DEVRAM STARTUP.A51 Example ...................................................................................... 1814 OTP STARTUP.A51 Example ............................................................................................ 1815 Evaluation Tab Setting .................................................................................................... 1916 Echo Analog Waveform Output (Channel1), Drive voltage (Channel 2) ............................................ 2017 DAC Output of Filtered Signal (Channel 2) and Drive Voltage (Channel 1)........................................ 2118 Schematic, LIN ............................................................................................................. 2219 Schematic, Power .......................................................................................................... 2220 Schematic, RS232 ......................................................................................................... 2321 Schematic, USB Controller ............................................................................................... 2322 Schematic, PGA450-Q1 (TPIC8500-Q1)................................................................................ 2423 PCB Layout, Bottom ....................................................................................................... 2524 PCB Layout, Top ........................................................................................................... 25

List of Tables

1 Jumpers ....................................................................................................................... 52 Default Jumper Settings .................................................................................................... 53 Default 0-Ω Resistor Setting................................................................................................ 54 Transducer and Transformer Manufacturer Part Numbers............................................................. 6

Trademarks

1 Read This FirstThe PGA450-Q1 is an interface device for ultrasonic transducers used in automotive parking assistanceand blind spot detection applications. The device functions as the driver and receiver for a wide range oftransducers with frequency ranges from 40 kHz to 70 kHz. The PGA450-Q1 device incorporates ananalog front end (AFE) and a 8051W microprocessor core. The AFE includes voltage regulators, anamplifier, an ADC, an oscillator, and a temperature sensor. The PGA450-Q1 device also implements aLIN 2.1 physical layer for communication. For more details, see the device data sheet.

2 EVM OverviewThe features of this EVM are as follows:• Single power-supply input for basic operation• Example push-pull transformer and 58-kHz transducer• LIN master transceiver• RS-232 transceiver for UART testing and debug• PC control with a graphical user interface and USB communications board

For a given PGA450Q1EVM installation, the following items apply:• The PGA450Q1EVM can have either a through-hole or surface-mount transformer installed on it.

When a through-hole transformer is installed, ensure that the case corners are not touching thesurface mount pads.

• The PGA450Q1EVM can be used to drive either a single-ended or push-pull transformer. The selectionof the drive method is achieved through jumper selection.

• The USB communication board 5-V power supply must be enabled for LIN communication to work.The 5-V power supply provides power to the LIN master transceiver installed on the board.

• In order to communicate with the PGA450-Q1 device using SPI, the 8051W inside the device must be

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www.ti.com EVM Overview




put in the reset state.


Power-Supply Requirements and Connections www.ti.com




3 Power-Supply Requirements and Connections

3.1 Power SupplyOnly one main power supply is needed. Apply 7 VDC to 18 VDC to the PGA450Q1EVM that suppliespower to the entire board, except for the USB communications board and LIN which are powered by theUSB communication PCB. Connect a power supply to the banana jacks, P1 “VPWR_IN” and P3 “GND” oruse the screw terminal P2.

3.2 Controlling and Powering the PGA450Q1EVM via the USB Interface BoardThe PGA450Q1EVM is shipped with a USB interface board that provides a link from the PC-controlledGUI (described later) to the EVM. Connect the USB interface board to the PGA450-Q1 device byconnecting the 30-pin female header on the interface board to P6, the male 30-pin header on thePGA450Q1EVM. The TI logo on the interface board should face up when it is plugged in. Figure 1 showsthe interface board connected to the PGA450Q1EVM.

Figure 1. PGA450Q1EVM Setup

3.3 Connecting the TransducerA transducer is included with the EVM. Solder the transducer connector to the through-holes at P6.Alternatively, use the screw terminal to connect the transducer.


www.ti.com Jumper Settings




4 Jumper SettingsThere are several jumpers and 0-Ω resistors located on the board, which are used to configure theconnections to the PGA450-Q1 device and the rest of the EVM. The default settings and their effects arelisted below.

4.1 JumpersTable 1 shows the function of each specific jumper setting on the EVM.

(1) The transformer provided with the EVM is push-pull. When using the single-ended configuration, JP4 must be disconnected andJP5 must be closed

Table 1. JumpersReference Jumper Setting Function

VPWR:VOTPClosed VP_OTP power supply input on the PGA450-Q1 device is connected to the 8-V voltage supply on the EVM.

Open VP_OTP power supply input on the PGA450-Q1 device is not connected to the 8-V voltage supply on theEVM.

VPWR:VLINClosed VPWR is connected to V_LIN, which is the LIN bus voltage.

Open VPWR is not connected to V_LIN, which is the LIN bus voltage.

JP3Closed The secondary of the transformer on the EVM is connected to the PGA450-Q1 device on the EVM.

Open The secondary of the transformer on the EVM is not connected to the PGA450-Q1 device on the EVM.

JP4Closed The transformer primary top terminal is connected to the OUTA pin on the PGA450-Q1 device, for push-pullconfiguration. (1)

Open The transformer primary top terminal is not connected to the OUTA pin on the PGA450-Q1 device.

JP5Closed The transformer primary top terminal is connected to the VREG pin on the PGA450-Q1 device, for single-ended configuration.

Open The transformer primary top terminal is not connected to the VREG pin on the PGA450-Q1 device.

4.2 Default Jumper Settings

(1) Ensure the TI-GER USB Interface board has no jumpers populated except for the 5-V digital I/O-level option located adjacent tothe red 5-V test-point. The HEX jumper should not be installed, nor should any of the pins on pin block P3 be shorted; these arereserved for TI only.

Table 2. Default Jumper Settings (1)

Reference Jumper Position Function

VPWR:VOTP Open VP_OTP power supply input on the PGA450-Q1 device is not connected to the 8-V voltage supply on theEVM.

VPWR:VLIN Closed VPWR is connected to V_LIN, which is the LIN bus voltage.

JP3 Closed The secondary of the transformer on the EVM is connected to the PGA450-Q1 device on the EVM.

JP4 Closed The transformer primary terminal 1 is connected to the OUTA pin on the PGA450-Q1 device for push-pullconfiguration.

JP5 Open The transformer primary terminal 1 is not connected to the VREG pin on the PGA450-Q1 device.

4.3 0-Ω ResistorsThe 0-Ω resistor R2 is used to connect the programming voltage to the PGA450-Q1 device that issoldered to the PCB. This resistor is not populated on the PCB. The soldered device has had the OTPprogrammed for DEVRAM usage.

Table 3. Default 0-Ω Resistor SettingReference Install Function

R2 DNP The VP_OTP pin of the device does not have OTP programming voltage.

Although they are installed to default settings in the factory, it is recommended that the user verify that thejumpers and 0-Ω resistors are installed to their default settings before powering on the EVM.


1 6

3 4

2

TI to supplyTR1

TRANSFORMER

XFMR RETURN

VREG

GND

OUTB

OUTA

C21

100uF,SMT,35V,20%,AL

11

22

P5

OUTPUT

C20

2000pF,0805,1kV,10%,X7R

JP3

XFRM

GND

LIM

IN

XFMR RETURN

C19

0.1

uF

,06

03

,50

V,1

0%

,X7

R

R93.3k,1210,1/4W,5%,+-200ppm/C

11

22

DO NOT POPULATE

P6

JP4

JP5

SH5SH4

SH3

Socket for Programming OTP www.ti.com




5 Socket for Programming OTPThe PGA450Q1EVM runs from the PGA450-Q1 device that is soldered to the board. In addition, the EVMprovides a footprint for a socket to enable programming the OTP in devices that are for customer-boarduse. The socket is not populated by default on the EVM. The part number for the recommended socket isOTS-28-0.65-01.

The GUI then can be used to select the target PGA450-Q1 device when programming OTP (the twooptions are the soldered device, or the device in the socket). More details of how to do this are describedin the OTP section.

6 Transformer and TransducerA matched transformer-transducer pair is included on the PGA450Q1EVM.

NOTE: C20 is a temperature compensation capacitor for the XDCR. Match C20 to the selected XDCR. If XDCR isMurata MA58MF14-7N, 2000-pF capacitance is installed, and 1500-pF capacitance is provided as analternative. If XDCR is Murata MA58AF14-0N. 1500-pF capacitance is installed. Alternative specificationsinclude: 1500 pF, 0805, 250 V, 20%, NPO

Figure 2. Transformer and Connector for the Transducer

A matched transformer-transducer pair is included on the PGA450Q1EVM. Table 4 lists closed-toptransducers and tunable push-pull transformers from various manufacturer numbers that can be matchedwith a tuning capacitor to create a sensor pair. By default, the transducer and transformer provided withthe EVM are the Murata MA58MF14-7N and Mitsumi K5-R4, respectively.

Table 4. Transducer and Transformer ManufacturerPart Numbers

Manufacturer Part NumberTransducer (at P5 or P6)

Murata MA58MF14-7NMurata MA58AF14-0N

Transformer (TR1)Mitsumi K5-R4Toko N1342DEA-0008BQE=P3

Murata has provided the following note with regard to the availability and ability to order their ultrasonicsensors:• For small quantity sample requests, inquire online at the Murata website: https://www.murata.com/en-

us/contactform.• For consumer-grade applications exposed to controlled environments, consider open-structure

sensors, such as the Murata MA40H1S-R. Distributors will typically have these sensors readilyavailable for purchase online.

• For automotive-grade sensors (such as the transducers listed in Table 4 for applications exposed to

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TPIC1021AQDRQ1

RXD1

EN2

NWAKE3

TXD4

GND5

LIN6

VSUP7

INH8

U1

LIN TxD GND

LIN RxD

GND

V_LIN

V_LIN

GND

LIN EN

FOOTPRINT OK 4/21/10

BA

V3

00

4W

-7-F

D3

R51.0k,0603,1/10W,5%

C5220pF,0603,50V,10%,X7R

R41.0k,0603,1/10W,5%

C4

0.1

uF

,08

05

,50

V,1

0%

,X7

R

R3

0,0

60

3,1

/10

W,5

%

NWAKE

R6

0,0

60

3,1

/10

W,5

%

GND

5V 5V

V_LIN LINGND

GND

LIN

RT

LT

LSEC

CT

CPT

CTUNE

T TTUNE PT

SEC

C LC C

L

´

= -

www.ti.com PGA450-Q1 Communication Interfaces




harsh environments, consider closed-top waterproof sensors, and inquire with distributors. Thedistributors will then request an order with Murata. Lead times for these sensors may vary up toseveral weeks.

Key ultrasonic sensor specifications are frequency, sensitivity, and directivity. The transformer is used toexcite the transducer. The transformer is center tapped to double the voltage. Typically, a tuning capacitoris needed to match the resonant frequency between the transducer and transformer.

(1)

CPT, RT, LT, and CT are characteristics of the transducer, LSEC is the secondary inductance of thetransformer, and CTUNE is an external capacitor placed across the terminals of the transducer.

Figure 3. Equivalent Circuit of Transformer-Transducer Sensor Pair

7 PGA450-Q1 Communication InterfacesThe PGA450-Q1 device has several communication options including: SPI, LIN, and UART. All of thesecommunication interfaces and related circuitry are present on the PGA450Q1EVM.

7.1 SPISPI is the main communication method on the PGA450-Q1 device. The 8051W inside the device must beput in reset to communicate using SPI. The SPI signals can be monitored with the CS, SCLK, SDI, andSDO test points on the EVM.

7.2 LINThe EVM includes a LIN transceiver, which is the master transceiver. The PGA450-Q1 device is always aslave on the LIN bus and has the slave transceiver integrated inside the device.

Figure 4. LIN Master Transceiver

The 5-V supply in Figure 4 is provided by the USB communication board.


MAX3221EUE+

C1+2

C1-4

C2+5

C2-6

TIN11

ROUT9

EN1

FORCEON12

GND14

V+3

V-7

TOUT (RS232)13

RIN (RS232)8

VCC15

~FORCEOFF16

~INVALID10

U4

1

2

3

4

5

6

7

8

9

11

10

J1

D Connector 9

C230.1uF,0603,50V,10%,X7R

C250.47uF,0805,50V,10%,X7R

C28

0.1uF,0603,50V,10%,X7R

GND

GND_UART

TX_232RX_232

~INVALID

C22 0.47uF,0805,50V,10%,X7R

C24 0.47uF,0805,50V,10%,X7R

TX_232

5VRS232 VCC

RxTx

C27

1uF,0603,25V,10%,X7R

R13

0,0603,1/8W,5%

L1

BEAD

GND_UART

GND_UART

GND_UART

GND_UART

TXDRXD

RX_232C26

100uF,SMT,35V,20%,ALGND_UART

GND_UART

GND_UART

tssop footprint and P/N

TXDR11

10.0k,0603,1/10W,5%

5V

PGA450-Q1 Communication Interfaces www.ti.com




7.3 UARTAn RS-232 transceiver (MAX3221) is present on the EVM that can be used as a debugging interface fromthe 8051 MCU to a host PC. The circuit connects the TXD and RXD pins on the PGA450-Q1 device to theMAX3221 device. The RX and TX RS-232 signals are routed to a standard DB-9 connector on the EVM.The RS-232 circuit is shown in Figure 5.

Figure 5. RS232 Transceiver


www.ti.com Controlling the PGA450-Q1 Memory Spaces With the GUI




8 Controlling the PGA450-Q1 Memory Spaces With the GUIThe PGA450Q1EVM is controlled by the user through a PC with the USB communication board andassociated GUI. The PGA450Q1EVM GUI provides ways to manipulate all of the register spaces presentinside the PGA450-Q1 device (ESFR, EEPROM, RAM, OTP, DEVELOPMENT RAM). The followingsections describe how to manipulate the register spaces.

8.1 Using the Register Grids to Manipulate the Register SpacesMost of the register spaces have register grids associated with them that provide a simple way toread/write the registers in the grid. There are eight buttons that are associated with the grid operations:ZERO GRID, DESELECT GRID, SAVE GRID, RECALL GRID, READ SELECTED, WRITE SELECTED,READ ALL, and WRITE ALL. These buttons perform operations on whichever register grid is currentlydisplayed. For example, when the GUI first loads, the ESFR register tab is displayed, if any of thepreviously listed buttons are pressed they perform operations on the ESFR register space. Each of theGRID functions is in one of the following sections.

8.1.1 ZERO GRIDThe ZERO GRID button replaces the contents of the entire grid with 0.

8.1.2 DESELECT GRIDThe DESELECT GRID button removes any selections that have been made in the grid without performingany operations on the registers that were selected.

8.1.3 SAVE GRIDThe SAVE GRID button takes the contents of the register grid and saves them to a .TXT file. The data issaved in comma-separated-values format.

8.1.4 RECALL GRIDThe RECALL GRID button opens a prompt that allows the user to select a .TXT file that was producedduring the SAVE GRID operation and then loads the grid with the contents from the .TXT file.

8.1.5 READ SELECTEDThe READ SELECTED button performs a read operation on any registers in the grid that have beenselected by clicking the desired register number. Any selected registers are displayed blue.

8.1.6 WRITE SELECTEDThe WRITE SELECTED button will perform a write operation on any registers in the grid that have beenselected by clicking the register number or modifying the register contents. Any selected registers aredisplayed in blue and any modified registers are highlighted in yellow. Any blue or yellow registers arewritten to when the WRITE SELECTED button is pressed.

8.1.7 READ ALLThe READ ALL button performs a read operation on every register in the grid.

8.1.8 WRITE ALLThe WRITE ALL button performs a write operation on every register in the grid.


Controlling the PGA450-Q1 Memory Spaces With the GUI www.ti.com




8.2 ESFR RegistersThe ESFR register displays all the function registers that are specific to PGA450-Q1 functionality. Theuser can set each register manually through SPI or define register values in 8051W firmware. AnEvaluation tab on the right side helps to set the ESFR registers for quick evaluation. More details of theEvaluation tab are described in a later section.

8.3 EEPROM RegistersThe EEPROM in the PGA450-Q1 device comprises 32 bytes of EEPROM and an EEPROM cache. Whenthe EEPROM grid is updated in the GUI, only the cache is updated.

8.3.1 Program EEPROMThe Program EEPROM button writes 0x01 to the EE_CTRL ESFR to program the EEPROM memorycells. The EEPROM memory cells are programmed with the values that are in the EEPROM cache insidethe PGA450-Q1 device.

The contents in the GUI are first transferred to the cache and then the cache is programmed.

8.3.2 Reload EEPROMThe Reload EEPROM button reloads the EEPROM cache inside the PGA450-Q1 device with the values inthe EEPROM memory cells. It then performs a READ ALL to update the grid with the refreshed contentsof the EEPROM bank.

The contents of the EEPROM cache can be updated on the GUI by clicking on the READ SELECTED orREAD ALL button.

8.4 RAMThe RAM tab is set up only for individual register read/writes without the use of the grid. When this tab isdisplayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttons perform thesame operations, respectively.

The PGA450-Q1 device has 512 bytes of general-purpose RAM. This general-purpose RAM is memory-mapped into two different memory spaces inside the PGA450-Q1 device: internal memory space(0x00–0xFF) and external memory space (0x0300–0x03FF).

The user must select the appropriate memory space in the Combo Box before making the Read/Writerequest. Note the valid address range for the two RAM sections.

8.5 OTPThe OTP tab is set up only for individual register read/writes without the use of the grid. When this tab isdisplayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttons perform thesame operations, respectively. The OTP tab also contains buttons used to load a .HEX 8051 program fileinto the 8051 MCU in the PGA450-Q1 device.

The PGA450Q1EVM could potentially have two devices: a device that is soldered on the EVM and adevice that is in the socket. The GUI allows programming of either device. When the device choice ismade, the GUI automatically resets the microprocessor for the respective device so that it is ready to loadOTP through SPI

NOTE: The OTP program requires R2 to be populated and the VPWR:VOTP jumper to be installed.This connects the VPROG_OTP 8-V supply on the VP_OTP pin during programming. Seethe data sheet for more details.






8.5.1 Load .HEX File Into GUIThe Load .HEX File into GUI button is used to load the contents of a .HEX file into the GUI RAM for usewith other operations. When the button is pressed, a second window opens that allows the user to locateand open the desired .HEX file on the PC. See Figure 6 for an example of this operation.

Figure 6. Loading a .HEX File Into the GUI

8.5.2 Program OTP Memory from .HEX FileIf the Program OTP Memory from .HEX File check box was checked (default) when the .HEX file wasloaded into the GUI, the OTP memory is programmed with the contents of the .HEX file.






8.5.3 Verify OTP ProgrammingIf the Verify OTP Programming button was also checked (default), then after the OTP memory is finishedprogramming, the GUI reads the contents of the OTP memory through SPI and verifies against the .HEXfile. If the OTP memory matches the contents of the .HEX file, the GUI displays the message “OTPMemory Verification Successful,” as seen in Figure 7.

Figure 7. OTP Memory Successful Programming Verification

8.5.4 Check OTP StatusPress the "Check OTP Status" button to verify what is currently programmed into OTP. The three possibleresults are:• Programmed to Jump to DEVRAM: The jump to DEVRAM statement has been programmed into the

OTP. This means that programs loaded into the DEVRAM will execute.• OTP Empty: Nothing has been programmed in the OTP.• Programmed: The OTP has been programmed with something other than the jump to DEVRAM

statement.






8.6 DEVRAMThe DEVRAM tab is set up only for individual register read/writes, without the use of the grid. When thistab is displayed, the READ SELECTED / READ ALL and WRITE SELECTED / WRITE ALL buttonsperform the same operations, respectively. The DEVRAM tab also contains buttons used to load a .HEX8051 program file into the 8051 MCU in the PGA450-Q1 device.

The process of loading the .HEX file into the DEVRAM is identical to that of OTP.

For a pristine IC that has never been programmed (OTP Status reads "OTP Empty"), in order to runsoftware from DEVRAM, the OTP memory must be programmed with some specific instructions to redirectthe 8051 µP to DEVRAM. This must only be done once. To do this, check the "Program OTP MemoryAlso" button, and the GUI will program the OTP with this jump statement as well as program the DEVRAMwith the selected HEX file.

Note that OTP programming may be required if the interrupt vectors are not programmed

Figure 8. OTP Memory can be programmed while programming the Development RAM






8.7 FIFO/ECHO

8.7.1 FIFOThe PGA450-Q1 device has a FIFO RAM that contains the output of the digital data path. The contents ofthe FIFO RAM can be displayed on the GUI and/or can be plotted in Excel.

The FIFO RAM is displayed in the form of a grid. The GUI grid contents can be updated either by clickingon the READ ALL button or by clicking on the READ SELECTED button.

The FIFO RAM contents can be displayed on the GUI and plotted in Excel by clicking the Read and SaveFIFO Data to File button.

NOTE: Note: Microsoft Office version 2007 or above is required for this function to work properly.

Figure 9. Echo Data Stored in FIFO RAM Plotted in Excel

8.7.2 EVAL MonitorThis tab graphs the output of the digital data path directly in the GUI. The 8051W microcontroller must bein reset to use this tab.

8.7.2.1 No. of LoopsThis option selects how many times the GUI will transmit a burst and plot the echo data.

8.7.2.2 TriggerIf "Auto" is displayed, the GUI will continue sending bursts and plotting the echo data until the "LoopsComplete" count matches the "No. of Loops." If "USER" is displayed, the GUI will stop and wait for theuser to press the green flashing "Trigger" button before continuing.






8.7.2.3 ResolutionThis button has three options, "FULL", "1/2", and "1/4". The "FULL" setting plots all of the echo datapoints, but takes more time. The "1/2" and "1/4" options reduce the number of data points plotted whichresults in faster plotting.

8.7.2.4 Clear PlotThe "CLR" button clears all data from the graph. If the "Clear Plot" option is checked, echo data will becleared from the plot every loop. If "Clear Plot" is not checked, every loop will plot the new echo data in anew color on top of the existing data on the graph.

8.7.2.5 Export Data to ExcelThis option exports the echo data to Excel for each loop.

8.7.2.6 Start/StopClick on the "Start" button to start the first loop. Click on "Stop" at any time to stop the programimmediately.


LIN Master www.ti.com




9 LIN MasterThe PGA450Q1EVM GUI communicates with the PGA450-Q1 device using LIN. The USB Communicationboard UART is the LIN master, and the PGA450-Q1 device is the LIN slave. The GUI can be used toconfigure the LIN frames that are transmitted to the PGA450-Q1 device.

Figure 10. LIN Master on GUI

In order to transmit data to PGA450-Q1 device using a LIN frame, the user must do the following:1. Enter the Frame PID in Edit Box corresponding to “Tx Frame PID”. The PID must be entered in hex.

Note that valid PID ranges from 0x00 to 0x3F. The GUI software calculates the parity bits using theLIN 2.1 method before the PID is transmitted to the slave.

2. Enter 0–8 bytes of data in the “Data to be Txed” box. Each data byte must be entered in Hex.3. Select the CLASSIC or ENHANCED checksum, which must match the LIN checksum setting in the

PGA450-Q1 ESFR LIN_CFG register.4. Click on the TRANSMIT button

In order to receive data from PGA450-Q1 device using a LIN frame, the user must do the following:1. Enter the Frame PID in Edit Box corresponding to “Rx Frame PID”. The PID must be entered in hex.

Note that valid PID ranges from 0x00 to 0x3F. The GUI software calculates the parity bits using theLIN 2.1 method before the PID is transmitted.

2. Enter the number of data bytes the user expects back from the PGA450-Q1 device.3. Select the CLASSIC or ENHANCED checksum4. Click on the RECEIVE button

The data received from the PGA450-Q1 device is displayed in the Data Received box.

If the data communication is not working, try Reset This Application, which power-cycles the LIN masterIC on the EVM.


www.ti.com Keil uVision Settings for Programming Firmware to the PGA450-Q1 DEVRAM or OTP Memory




10 Keil uVision Settings for Programming Firmware to the PGA450-Q1 DEVRAM or OTPMemory

10.1 ObjectiveTo modify the source code made available through the PGA450Q1EVM firmware installer, download theKeil C51 Development Tool for all 8051 devices, which includes the uVision IDE necessary to open andedit the PGA450-Q1 project file. Keil products use a license management system. Without a currentlicense, the product runs as a lite or evaluation edition with a few limitations.

10.2 Setup

Figure 11. DEVRAM Target Options

To Program to DEVRAM:1. Change the code range to the DEVRAM memory space.

a. Right click on Target 1 in the project window, and select Options for Target.b. Go to the BL51 Locate tab, and modify the Code Range to go from 0x2000–0x3FFF.

2. Copy the following to the Code box:?pr?external1_ISR?PGA450_isrs (0X2100),?pr?timer0_ISR?PGA450_isrs (0X2400),?pr?timer1_ISR?PGA450_isrs (0X2800),?pr?serial_ISR?PGA450_isrs (0X2C00),?pr?linPID_ISR?PGA450_isrs (0X3000),?pr?linSciRxData_ISR?PGA450_isrs (0X3400),?pr?linSciTxData_ISR?PGA450_isrs (0X3800),?pr?external0_ISR?PGA450_isrs (0X3900),?pr?linSync_ISR?PGA450_isrs (0X3D00)

3. Comment out the OTP section in STARTUP.A51, and uncomment the OTP sectiona. An example of this is shown in Figure 13.


Keil uVision Settings for Programming Firmware to the PGA450-Q1 DEVRAM or OTP Memory www.ti.com




Figure 12. OTP Target Options

To Program to OTP:1. Change the code range to the OTP memory space

a. Right click on Target 1 in the project window, and select Options for Target.b. Go to the BL51 Locate tab, and modify the Code Range to go from 0x0000–0x1FFF.

2. Delete everything in the Code box.3. Comment out the DEVRAM section in STARTUP.A51, and uncomment the OTP section.

a. An example of this is shown in Figure 14.

Figure 13. DEVRAM STARTUP.A51 Example Figure 14. OTP STARTUP.A51 Example

Instructions: Build the PGA450.uvproj to generate the custom .HEX file used to program the internal8051 core. The LIN Demonstration using PGA450Q1EVM Firmware Rev 2.1 provides instructions on howto upload the .HEX file using the EVM GUI.


www.ti.com Use Case




11 Use CaseThe purpose of this section is to provide step-by-step instructions on the setup and some basic evaluationprocedures.

11.1 Evaluation Through SPI CommunicationIn order to provide a quick evaluation of the IC performance using the TI EVM and GUI without having todevelop sophisticated 8051 µP software, the GUI provides an intuitive interface tab, Evaluation Tab, thatcollects all necessary information regarding the transducer drive and receive. For transducer drive, itincludes: transducer frequency; transducer drive voltage, VREG; transformer configuration; and number ofdrive pulses. For transducer signal receive, it includes signal-processing parameters: LNA gain setting;BPF and LPF coefficient; clock selection; FIFO mode; and FIFO downsample size.

1. Make sure all jumpers are connected according to the default settings, see Section 4.2.2. Connect the hardware and power supply, see Section 3. Make sure USB cable is connected to the

computer and the interface board. It is recommended to monitor power supply current. Normal idlecurrent is around 6 mA. Active current is around 15 mA.

3. Launch GUI software on computer.4. Click the "OFF (Micro Reset)" button to put the Micro in reset, then click READ ALL to read the default

register values. Some default values are loaded in the table grid. If all are 0 or FF values, this meansthat there is an error with communication to the device. Check the hardware setup or restart the GUIsoftware.Fill out the "Evaluation" tab with the values shown in Figure 15.Use the "Eval Monitor" tab to send bursts and view the resulting echo data.

Figure 15. Evaluation Tab Setting

After all information is entered, make sure the device is in the micro reset state, then hit the TransducerDrive and Receive button to start the burst and receive.


Use Case www.ti.com




11.2 Monitoring the Signal PathThe PGA450-Q1 device has two useful test modes that allow users to quickly observe the echo signal asan amplified analog signal or from a DAC output which converts a digitally filtered echo signal. In theEvaluation tab, quick-access buttons Amplifier Output (unfiltered) and Datapath Output (filtered) areavailable. The signal is viewable on the DACO pin. Only one mode can be selected at a time. SeeFigure 16 and Figure 17 for the captured waveforms.

Figure 16. Echo Analog Waveform Output (Channel1), Drive voltage (Channel 2)


www.ti.com Use Case




Figure 17. DAC Output of Filtered Signal (Channel 2) and Drive Voltage (Channel 1)


VPWR

5V

C1

0.1uF,0603,50V,10%,X7R

GND

5V

VPWR

GND GND

GND

F

P1VPWR-IN

F

P3GND

GND

FLZ8V2C

D2

VPROG_OTP (8V)

GND

JP1VPWR:VOTP

VPWR

R1

62

0,1

21

0,1

/2W

,5%

VP_OTP_SOC

C3

1uF,0805,50V,10%,X7RGND

C2


JP2

VPWR

V_LINV_LIN

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

B260-13-F

A2

C1

D1

R2

DNP,0805,1/8W,5%

VP_OTP

POPULATE RESISTOR TO CONNECT V_OTP

PWR-IN

11

22

P2

GND VPWR-IN

TO THE SOLDERED DOWN PART

TPIC1021AQDRQ1

RXD1

EN2

NWAKE3

TXD4

GND5

LIN6

VSUP7

INH8

U1

LIN TxD GND

LIN RxD

GND

V_LIN

V_LIN

GND

LIN EN

FOOTPRINT OK 4/21/10

BA

V3

00

4W

-7-F

D3

R51.0k,0603,1/10W,5%

C5220pF,0603,50V,10%,X7R

R41.0k,0603,1/10W,5%

C4

0.1

uF

,08

05

,50

V,1

0%

,X7

R

R3

0,0

60

3,1

/10

W,5

%NWAKE

R6

0,0

60

3,1

/10

W,5

%

GND

5V 5V

V_LIN LINGND

GND

LIN

PGA450Q1EVM Schematics and Layout Drawings www.ti.com




12 PGA450Q1EVM Schematics and Layout Drawings

Figure 18. Schematic, LIN

spacer

spacer

Figure 19. Schematic, Power


IO-11

IO-6V_5.0_WORLD

V_3.3_WORLDV_DVM_1V_DVM_2V_DVM_3

GND

GND

IO-3IO-5

IO-10 (SLOW OSC)

IO-8__TX

IO-9__RXPWR-DWN

IO-7

IO-AIO-BDAC_OUT

IO-OSC

GNDGND

IO-SCLKIO-CSIO-MOSI

IO-MISO

IO-0 IO-1IO-2IO-4

5V

SDO

SDICSSCLK

CS_SOCKET

VPWR

LIN TxD

LIN RxD

LIN EN

MISO, SDA1

SCLK, SCL3

CS (SS)5

MOSI7

IO-119

IO-011

IO-213

IO-415

IO-617

V_5.0V (OUT)19

CHIP OSC (OUT)21

V_3.3V (OUT)23

GND2

IO-10 (PIC OSC)24

PWR-DWN22

IO-9, RX20

IO-718

IO-516

IO-314

IO-112

IO-8, TX10

GND8

GND6

GND4

TIGER - A

DVM-125

DVM-227

DVM-329

IO-DAC30

IO-B28

IO-A26

TIGER - A

MAX3221EUE+

C1+2

C1-4

C2+5

C2-6

TIN11

ROUT9

EN1

FORCEON12

GND14

V+3

V-7

TOUT (RS232)13

RIN (RS232)8

VCC15

~FORCEOFF16

~INVALID10

U4

1

2

3

4

5

6

7

8

9

11

10

J1

D Connector 9

C230.1uF,0603,50V,10%,X7R

C250.47uF,0805,50V,10%,X7R

C28

0.1uF,0603,50V,10%,X7R

GND

GND_UART

TX_232RX_232

~INVALID

C22 0.47uF,0805,50V,10%,X7R

C24 0.47uF,0805,50V,10%,X7R

TX_232

5VRS232 VCC

RxTx

C27

1uF,0603,25V,10%,X7R

R13

0,0603,1/8W,5%

L1

BEAD

GND_UART

GND_UART

GND_UART

GND_UART

TXDRXD

RX_232C26

100uF,SMT,35V,20%,ALGND_UART

GND_UART

GND_UART

tssop footprint and P/N

TXDR11

10.0k,0603,1/10W,5%

5V

www.ti.com PGA450Q1EVM Schematics and Layout Drawings




Figure 20. Schematic, RS232

spacer

spacer

Figure 21. Schematic, USB Controller


GPIO1GPIO2

TXD

LIN

XOUT SDOSDI

CSSCLK

TESTO_A

TESTO_DRBIASCIN

INLIM

XINDVDDGND

VREG

RXD

AVDDVREF

GND

GND

OUTB

OUTA

GPIO1GPIO2

TXD

LIN

OUTBSDOSDI

CSSCLK

TESTO_D

VPWR

GND

RBIAS

XINXOUT

RXD

CININ

OUTA

VREFVP_OTP

AVDD

LIM

DVDD GND

TESTO_A

VREG

GND

VPWR1

VREG2

LIN3

GND4

DVDD5

XIN6

XOUT7

GPIO18

GPIO29

RxD10

TxD11

CIN12

IN13

LIM14

GND15

TESTO_A16

RBIAS17

TESTO_D18

NCS19

SCLK20

SDI21

SDO22

OUTB23

GND24

OUTA25

VPROG_OTP26

VREF27

AVDD28

TPIC8500-Q1

U2

SDOSDISCLK

VPWR

GNDVP_OTP_SOC

AVDD_SOC

DVDD_SOC GND

GND

VPWR1

VREG2

LIN3

GND4

DVDD5

XIN6

XOUT7

GPIO18

GPIO29

RxD10

TxD11

CIN12

IN13

LIM14

GND15

TESTO_A16

RBIAS17

TESTO_D18

NCS19

SCLK20

SDI21

SDO22

OUTB23

GND24

OUTA25

VPROG_OTP26

VREF27

AVDD28

TPIC8500-Q1TI to supply, NO PIN1 DESIGNATOR - REVERSABLE

U3

VPWR

VP_OTP

GND

C11

0.1

uF

,06

03

,50

V,1

0%

,X7

R

VPWR VREG DVDD CIN VP_OTP AVDD

C12

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C13

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C14

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C15

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C16

0.1

uF

,06

03

,50

V,1

0%

,X7

RGND GND GND GND GND

R7

100.0k,0603,1/10W,0.1%,+-25ppm/C

RBIASGND

GND

C6

0.1

uF

,06

03

,50

V,1

0%

,X7

R

VPWR VREG_SOC DVDD_SOC VP_OTP_SOCAVDD_SOC

C7

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C8

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C9

0.1

uF

,06

03

,50

V,1

0%

,X7

R

C10

0.1

uF

,06

03

,50

V,1

0%

,X7

R

GND GND GND GND

XIN XOUT

NX3225SA-16.000000MHZ

1 3

4 2

X116MHz,15ppm,8pF

C17

12pF,0603,100V,5%,NPO

C18

12pF,0603,100V,5%,NPO

GNDGND

1 6

3 4

2

TI to supplyTR1

TRANSFORMER

XFMR RETURN

VREG

GND

OUTB

OUTA

C21


11

22

P5

OUTPUT

C20

2000pF,0805,1kV,10%,X7R

JP3

XFRM

GND

LIM

IN

XFMR RETURN

C19

0.1

uF

,06

03

,50

V,1

0%

,X7

R

CS_SOCKET

RBIAS_SOCGND

RBIAS_SOC

R93.3k,1210,1/4W,5%,+-200ppm/C

R8

100.0k,0603,1/10W,0.1%,+-25ppm/C

VREG_SOC

R10

20

0k,0

60

3,1

/10

W,5

%

GND

VREG

11

22

DO NOT POPULATE

P6

JP4

JP5

SH5SH4

SH3

PGA450Q1EVM Schematics and Layout Drawings www.ti.com




NOTE: C20 is a temperature compensation capacitor for the XDCR. Match C20 to the selected XDCR. If XDCR isMurata MA58MF14-7N, 2000-pF capacitance is installed, and 1500-pF capacitance is provided as analternative. If XDCR is Murata MA58AF14-0N. 1500-pF capacitance is installed. Alternative specificationsinclude: 1500 pF, 0805, 250 V, 20%, NPO

Figure 22. Schematic, PGA450-Q1 (TPIC8500-Q1)


13NetU3_13

7NetU3_7

3NetU3_3

1VPWR

19CS_SOC KET

25NetU3_25

11NetU3_11

9NetU3_9

5DVDD_SOC

hole

hole

21SDI

17RBIAS_SOC

15GND

27NetU3_27

2VPWR

1NetC20_1

2XFMR RETURN

23NetU3_23

2NetC20_1

1GND

10NetU3_10

4GND

16NetU3_16

22SDO

26VP_OTP_SO C

28AVDD_SOC

1GPIO2

1LIN

1RXD

1GND

1CS

1OUTA

5GND_UART

8NetJ1_8

30DAC_OUT

26IO-A

24IO-10 (SLOW OSC)

20IO-9__RX

18IO-7

12IO-1

14IO-3

6GND

8GND

4GND

2GND

14NetU3_14

12NetU3_12

8NetU3_8

2VREG_SOC

29V_DVM_3

25V_DVM_1

23V_3.3_WO RLD

17IO-6

19V_5.0_WO RLD

13IO-2

11IO-0

3IO-SCLK

7IO-MOSI

5IO-CS

1IO-MISO

1NetJP1_1

2VPWR

1GND

20SCLK

18NetU3_18

24GND

1VP_OTP_SO C

1IN

1TXD

1XO UT

1DVDD

1VPWR

1GND

1LIM

1CIN

1GPIO1

1XIN

1VREG

1V_LIN

1GND

1LIN

1V_LIN

1GND

1RBIAS

1SDI

1OUTB

1VREF

1GND

2PWR-IN

1GND

1GND_UART

15V

1GND

1NetJP4_2

2VREG

3OUTB

1VREG

2NetJP4_2

1OUTA

2NetJP4_2

1RX_232

1TX_232

6NetC20_1

4GND

5NA_

4NetJ1_4

2TX_232

1NetJ1_1

1GND

9NetJ1_9

6NetJ1_6

28IO-B

22PWR-DWN

16IO-5

6NetU3_6

10IO-8__TX

27V_DVM_2

15IO-4

21IO-OSC

0

9IO-11

1XFMR RETURN

1GND

2NetC20_1

3RX_232

7NetJ1_7

1SCLK

1VP_OTP

1TESTO_A

1TESTO_D

1SDO

1GND

1AVDD

1VPWR

1GND

1NetC26_1

11NetJ1_11

10NetJ1_10

1PWR-IN

0

0

1GND

1GND

1IO-9__RX

2LIN RXD

1IO-8__TX

2LIN TXD

1CS_SOC KET

2IO-11

1SDI

2IO-MOSI

1CS

2IO-CS

1SDO

2IO-MISO

1LIN EN

2IO-0

1SCLK

2IO-SCLK

6NetC25_27

NetC24_18

RX_232

9RXD

10~INVALID

11TXD

2NetC25_2

3NetC22_14

NetC23_25

NetC25_1

12GND_UART

13TX_232

14GND_UART

1GND_UART

16NetC26_1

1NetC20_1

2GND

2LIM

3NWAKE

2LIN EN

15GND

14LIM

17RBIAS

18TESTO_D

12CIN

11TXD

20SCLK

21SDI

22SDO

9GPIO2

8GPIO1

7XO UT

23OUTB

24GND

25OUTA

6XIN

5DVDD

4GND

27VREF

28AVDD

2VREG

1VPWR

6LIN

7V_LIN

4LIN TXD

1LIN RXD

16TESTO_A

19CS

13IN

10RXD

26VP_OTP

3LIN

5GND

8NetU1_8

1NetJP4_2

2VREG

3OUTB

2NetC23_1

15NetC26_1

1NetC25_1

4GND

5NA_

6NetC20_1

1VPWR

1XFMR RETURN

1NetC26_1

2GND_UART

2GND

13NetU3_13

7NetU3_7

3NetU3_3

1VPWR

19CS_SOCKET

25NetU3_25

9NetU3_9

11NetU3_11

5DVDD_SOC

hole

hole

15GND

17RBIAS_SOC

21SDI

27NetU3_27

2VPWR

1NetC20_1

2XFMR RETURN

23NetU3_23

2NetC20_1

1GND

10NetU3_10

4GND

16NetU3_16

22SDO

26VP_OTP_SOC

28AVDD_SOC

1GPIO2

1LIN

1RXD

1GND

1CS

1OUTA

5GND_UART

8NetJ1_8

30DAC_OUT

24IO-10 (SLOW OSC)

26IO-A

18IO-7

20IO-9__RX

14IO-3

12IO-1

4GND

8GND

6GND

2GND

8NetU3_8

12NetU3_12

14NetU3_14

2VREG_SOC

29V_DVM_3

23V_3.3_WORLD

25V_DVM_1

19V_5.0_WORLD

17IO-6

11IO-0

13IO-2

5IO-CS

7IO-MOSI

3IO-SCLK

1IO-MISO

2VPWR

1NetJP1_1

1GND

18NetU3_18

20SCLK

24GND

1VP_OTP_SOC

1IN

1XOUT

1TXD

1VPWR

1DVDD

1GND

1LIM

1GPIO1

1CIN

1VREG

1XIN

1V_LIN

1GND

1V_LIN

1LIN

1GND

1SDI

1RBIAS

1VREF

1OUTB

1GND

2PWR-IN

1GND

1GND_UART

15V

1GND

3OUTB

2VREG

1NetJP4_2

2NetJP4_2

1VREG

2NetJP4_2

1OUTA

1TX_232

1RX_232

5NA_

4GND

6NetC20_1

4NetJ1_4

1NetJ1_1

2TX_232

1GND

9NetJ1_9

6NetJ1_6

16IO-5

22PWR-DWN

28IO-B

6NetU3_6

10IO-8__TX

21IO-OSC

15IO-4

27V_DVM_2

0

9IO-11

1XFMR RETURN

1GND

2NetC20_1

3RX_232

7NetJ1_7

1SCLK

1VP_OTP

1TESTO_A

1SDO

1TESTO_D

1AVDD

1GND

1VPWR

1GND

11NetJ1_11

1NetC26_1

10NetJ1_10

1PWR-IN

1GND

0

0

1GND

15V

2VPWR

1XIN

1VREG

2GND

2NetC26_1

2GND

1VREG_SOC

1VPWR

2GND

1DVDD_SOC

2VP_OTP

2GND

2GND

1RBIAS_SOC

1AVDD_SOC

2GND

1VP_OTP_SOC

1NetD3_1

2V_LIN

1XOUT

1VREG

2GND

25V

1TXD

2GND_UART

1NetC24_1

1GND_UART

2NetC23_2

2GND_UART

1NetC22_1

1NetC23_1

15V

1LIN

2V_5.0_WORLD

1PWR-DWN

1NetD3_1

2GND

2GND

1DVDD

2GND

2GND_UART

1NetC26_1

2GND_UART

1NetC26_1

2GND

1VP_OTP_SOC

1VP_OTP_SOC

2GND

3XOUT

2GND

1NWAKE

2LIN EN

15V

2LIN RXD

15V

2LIN

2GND

2GND

1CIN

2LIM

1IN

2GND

1RBIAS

2GND

1AVDD

2GND

1VPWR

2GND

2GND

1V_LIN

1VPWR

2PWR-IN

1XIN

4NetX1_4

2GND

1VPWR

2GND

1VREG

2GND

2VP_OTP_SOC

1VP_OTP_SOC

1NetJP1_1

2NetX1_2

1VP_OTP

2GND

www.ti.com PGA450Q1EVM Schematics and Layout Drawings




Figure 23. PCB Layout, Bottom

Figure 24. PCB Layout, Top


Revision History www.ti.com



Revision History

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from B Revision (June 2015) to C Revision .................................................................................................... Page

• Changed the Transformer and Connector for the Transducer schematic ......................................................... 6• Changed the Murata part numbers for the transducer in the Transformer and Transducer section ........................... 6• Added Murata note on availability of ultrasonic sensors ............................................................................. 7• Changed the Schematic, PGA450-Q1 (TPIC8500-Q1) ............................................................................. 24• Changed the PCB Layout, Top layout image ........................................................................................ 25


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PGA450Q1EVM User’s Guide1 Read This First2 EVM Overview3 Power-Supply Requirements and Connections3.1 Power Supply3.2 Controlling and Powering the PGA450Q1EVM via the USB Interface Board3.3 Connecting the Transducer

4 Jumper Settings4.1 Jumpers4.2 Default Jumper Settings4.3 0-Ω Resistors

5 Socket for Programming OTP6 Transformer and Transducer7 PGA450-Q1 Communication Interfaces7.1 SPI7.2 LIN7.3 UART

8 Controlling the PGA450-Q1 Memory Spaces With the GUI8.1 Using the Register Grids to Manipulate the Register Spaces8.1.1 ZERO GRID8.1.2 DESELECT GRID8.1.3 SAVE GRID8.1.4 RECALL GRID8.1.5 READ SELECTED8.1.6 WRITE SELECTED8.1.7 READ ALL8.1.8 WRITE ALL

8.2 ESFR Registers8.3 EEPROM Registers8.3.1 Program EEPROM8.3.2 Reload EEPROM

8.4 RAM8.5 OTP8.5.1 Load .HEX File Into GUI8.5.2 Program OTP Memory from .HEX File8.5.3 Verify OTP Programming8.5.4 Check OTP Status

8.6 DEVRAM8.7 FIFO/ECHO8.7.1 FIFO8.7.2 EVAL Monitor8.7.2.1 No. of Loops8.7.2.2 Trigger8.7.2.3 Resolution8.7.2.4 Clear Plot8.7.2.5 Export Data to Excel8.7.2.6 Start/Stop

9 LIN Master10 Keil uVision Settings for Programming Firmware to the PGA450-Q1 DEVRAM or OTP Memory10.1 Objective10.2 Setup

11 Use Case11.1 Evaluation Through SPI Communication11.2 Monitoring the Signal Path

12 PGA450Q1EVM Schematics and Layout Drawings

Revision HistoryImportant Notice

Documents

PGA450Q1EVM User’s Guide - TI.com4 Jumper Settings There are several jumpers and 0-Ωresistors located on the board, which are used to configure the connections to the PGA450-Q1