PEX 8112 AA Schematic Design Checklist

PEX 8112 AA Schematic Design Checklist

Version 1.3

November, 2009

Website: www.plxtech.com Technical Support: www.plxtech.com/support

Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.3

PEX 8112AA Schematic Design Checklist 2 © 2009, PLX Technology, Inc. All rights reserved – Version 1.3

1. Introduction This document provides a checklist of recommendations for successfully implementing the PEX 8112 device in schematic and PCB designs. The checklist contains basic guidelines to consider in schematic design, PCB design, and silicon choices. References to other PLX documents are provided for further details.

2. ORCAD Symbols The OrCAD symbols are available on the PLX Technology, Inc., website.

http://www.plxtech.com/ 8112

3. Silicon Requirements The PEX 8112, as of the date of this document, ships with Silicon Revision AA.


4. Schematic Guidelines Review the PEX 8112 Hardware Reference Manuals for important information about designing with the PEX 8112 The designs used in these manuals have been extensively tested by PLX; therefore, they make good templates for customizing PEX 8112 designs.

4.1. Schematic Connections – Forward Bridge Mode APPLICATION – ADD-IN BOARD EMBEDDED DAUGHTER BOARD UNKNOWN

CUSTOMER – ________________________________ DATE – ___________________ PEX 8112 Schematic Checklist – Forward Bridge Mode

Bridge Configuration Setting Mode Recommendations

Forward Forward Bridge Verify that the FORWARD ball is pulled up.

Arbitration Type Internal Check the EXTARB ball for arbitration status. Ground for Internal

Arbitration.

External If High, provide External Arbitration logic in the schematic for review.

Clock Setup

Master Mode If PCLKO is used, PEX 8112 is a Clock Master. PCLKI must remain connected to Clock source.

Slave Mode Check whether PCLKI source is being buffered between the PEX 8112 and other devices. The Clock buffer can create clock skew between PEX 8112 and endpoint.


4.1.1. Clock Interface Signals Table 1 Clock Interface Connections

Clock Sources/ Signal Names

Ball # (144-Ball Package)


Type Termination Recommendations

External REFCLK Clock Transmitter

N/A N/A External- CML

YES NO

UNKNOWN

For HCSL clock driver, a 33-Ohm series and 49-Ohm shunt is required on each differential pair(See Figure 19-3 in the PEX 8112 databook). Maximum clock frequency tolerance allowed for REFCLK source is ±300 ppm. Confirm that the device’s REFCLK oscillator supports this. Note: REFCLK termination varies depending on the type of clock driver used (see Section 19.4.2 PCI Express REFCLK DC Specification in the PEX 8112 databook for examples)

REFCLK- Input B6 A7 I

DIFF YES NO

UNKNOWN

REFCLK+ Input A6 B7 I

DIFF YES NO

UNKNOWN

4.1.2. Reset Signals Table 2 Reset Connections

Signal Name Ball #

(144-Ball Package)


Type Ball Status Recommendations

PERST# B12 C12 I/O YES NO

UNKNOWN

Input in Forward Bridge mode. Output in Reverse Bridge mode. PCI Express Reset. Must be connected or pulled up on device. Refer also to Section 4.3.2, “Reset.”

PCIRST# F10 G14 I/O TP

YES NO

UNKNOWN

PCI Bus Reset. Driven as an output in Forward Bridge mode. Input in Reverse Bridge mode. Can also be controlled by the Bridge Control register Secondary Bus Reset bit (offset 3Eh[6]).


4.1.3. Serial EEPROM Signals Table 3 Serial EEPROM Connections

Serial EEPROM Type Status Supply Recommendations

AT26540 NOT PRESENT

PRESENT

+3.3V

Other Existing +3.3V supply must be used.

Signal Name Ball #

(144-Ball Package)



EECLK B2 C2 O TP

YES NO

UNKNOWN

SPI serial EEPROM Clock output from PEX 8112 drives serial EEPROM CLK input. Check connections to and from PEX 8112.

EECS# C4 C5 O TP

YES NO

UNKNOWN

Serial EEPROM Chip Select driven from PEX 8112. Check connections to and from PEX 8112.

EERDDATA A1 B3 I YES NO

UNKNOWN

Serial EEPROM data input to PEX 8112. Check connections to and from PEX 8112. This pin should be pulled high using a 10K - 47K ohm resistor.

EEWRDATA A2 A3 O TP

YES NO

UNKNOWN

Serial EEPROM data output from PEX 8112. Check connections to and from PEX 8112.

WP# N/A N/A I YES NO

UNKNOWN

Serial EEPROM ball. Must be pulled up if the serial EEPROM Write Protect Function is not being used. This ball is not used on the PEX 8112.


4.1.4. Strapping Signals Table 4 Strapping Ball Connections

Signal Name Ball #

(144-Ball Package)



BAR0ENB# E8 A10 I

STRAP YES NO

UNKNOWN

Recommend that this signal be pulled up. However, if shared Memory or Memory-Mapped Configuration access on the PEX 8112 is needed, it must be pulled down or Grounded.

BTON M11 M11 I

STRAP YES NO

UNKNOWN Must be Grounded for normal use.

BUNRI D8 C9 I

STRAP YES NO


EXTARB K11 M12 I

STRAP YES NO

UNKNOWN Must be Grounded for Internal Arbitration.

FORWARD L11 M13 I

STRAP YES NO

UNKNOWN

Must be pulled up for Forward Bridge mode.

M66EN D10 D13 I

STRAP YES NO

UNKNOWN

Connected to the edge connector or driven by another device in an embedded application. This signal should be decoupled to Ground with a .01 µF capacitor. If multiple PCI slots are implemented, a 0.01uF capacitor is required at each PCI slot.

PCLKO62SEL# C2 C3 I

PU YES NO

UNKNOWN

When pulled Low with M66EN High, causes the PCLKO clock to be derived from an internal low-jitter PLL. PCLKO is 62.5 MHz, with a 50% Duty cycle. Okay to leave no connect if no external trace is attached.

SMC K1 K3 I

STRAP YES NO


TEST A3 C4 I

STRAP YES NO


TMC C8 D10 I

STRAP YES NO


TMC1 B1 D4 I

STRAP YES NO


TMC2 M1 M1 I

STRAP YES NO



4.1.5. Power Supply Signals Table 5 Power Supply Connections

Signal Name Ball #

(144-Ball Package)



PWR_OK B9 B11 O YES NO

UNKNOWN

Valid only in Forward Bridge mode. When the available power indicated in the Set Slot Power Limit message is greater than or equal to the power requirement indicated in the Power register (offset 101Ch), PWR_OK is asserted.

Signal Name Ball #

(144-Ball Package)



AVDD E7 C8 Power YES NO

UNKNOWN

SerDes Analog circuit power supply. Connect to 1.5V core supply.

AVSS VSS_C

C7 D7

C6 D9

Ground YES NO

UNKNOWN

SerDes Analog Ground return and common Ground return. Connect to system Ground.

GND

A12, B4, C3, C11, D9, E6,

F12, G5, H4, H7, J4, J8,

K2, K10

A4, C13, D5, D12, E4, E11, F11, J2, K4, K11, L4, M6, N9, P12

Ground YES NO

UNKNOWN

Core Ground connections. Ensure all balls are connected to system Ground.

VDD_P D5 B6 Power YES NO

UNKNOWN

REFCLK PLL Power supply. Connect to 1.5V supply. A filtering circuit is recommended to protect against noise. Refer to the PEX 8112 BB Quick Start Design Note for further details.

VDD_R VDD_T

A7 A5

C7 D6

Power YES NO

UNKNOWN

SerDes Digital circuit power supply. Connect to 1.5V core supply.

VDD1.5

C10, D4, F6, F8, G6, G7, J9, K3

B10, C1, C14, G2, G13, L3, L11, N7

Power YES NO

UNKNOWN

1.5V Core and SerDes Power. Can be tied to VDD_R/T. Ensure that all signals are connected on the schematic.

VDD3.3 B3, B11, L2, M10

B4, C11, L10, N3 Power

YES NO

UNKNOWN 3.3V I/O power. Must be connected on all designs.

VDD5 F5, G8, H6

G3, H13, L7 Power

YES NO

UNKNOWN

Optional 5V I/O power supply. Must be used with 3.3V I/O supply. Power Sequencing Guidelines and logic must be used with this supply. Refer to Section 4.3.1, “Power Sequencing.”


Signal Name Ball #

(144-Ball Package)



VDDQ E5, F9, G4, H5, H8, J7

F4, G12, H4, J12, L8, N5

Power YES NO

UNKNOWN

PCI buffer supply. Connect to 3.3V I/O supply. Must be connected on all designs.

VSS_P[1:0] C6, D6 D8, D7 Ground YES NO

UNKNOWN PLL Ground. Connect to system Ground.

VSS_R VSS_T

B8 C5

A9 A5

Ground YES NO

UNKNOWN

PCI Express RX and TX Ground return. Connect to system Ground.

VSS_RE F7 B8 Ground YES NO

UNKNOWN

Additional RX Ground return. Must be connected on all designs.


4.1.6. JTAG Interface Signals Table 6 JTAG Interface Ball Connections

Signal Name Ball #

(144-Ball Package)



TCK M2 M2 I YES NO

UNKNOWN

JTAG Test Clock Input. If unused, pull-down to VSS (Ground).

TDI L3 P3 I

PU YES NO

UNKNOWN

JTAG Test Data Input. If unused, pull-up to VDD33.

TDO L1 M3 O TS

YES NO

UNKNOWN JTAG Test Data Output.

TMS M12 N12 I

PU YES NO

UNKNOWN

JTAG Test mode Select Input. If unused, pull-up to VDD33 with a 3K- to 10K-Ohm resistor.

TRST# L10 N11 I

PU YES NO

UNKNOWN

JTAG Test Reset. Active Low input. Tie to VSS (Ground) through a 1.5K-Ohm resistor when Test Access Port (TAP) is not being used.

4.1.7. No Connect Signals Table 7 No Connect Balls

Signal Name Ball #

(144-Ball Package)



NC –

A1, A2, A13, A14, B1, B2,

B13, B14, E5, N1,

N2, N13, N14, P1, P2, P13,

P14

Reserved YES NO

UNKNOWN

161-ball FBGA package only. These balls must remain open. Do not connect these balls to electrical paths on the board.


4.1.8. PCI Bus Signals Table 8 PCI Bus Connections

Signal Name




AD[31:0]

J10, J12, J11, K12, L9, M9, K8, L8, K7, L7, M7, J6, K6, M6, L6, J5, H2, H1, G3, G2, G1, F4, F3, F2, E4, E3, E2, E1, D2, D1, C1, D3

L13, J11, K12, L12, M10, P11,

P10, P9, L9, N8, P8, M8, M7, L6, N6, P7, K2, J3, J1, H2, H3, H1, G4, F3, F2, F1, E2, E3, E1, D3,

D1, D2

I/O TS

YES NO

UNKNOWN PCI Bus 32-bit Address/Data Bus.

CBE[3:0]# M8, K5, H3, F1

M9, P6, K1, G1

I/O TS

YES NO

UNKNOWN PCI Bus Command Byte Enables.

DEVSEL# K4 M4 I/O

STS YES NO

UNKNOWN

PCI Bus Device Select. Driven by PEX 8112 when a Bus Target and has been addressed by the Master. Must be pulled up, if using an embedded bus.

FRAME# M5 L5 I/O

STS YES NO

UNKNOWN

PCI Bus Frame signal. Output when PEX 8112 is a Bus Master. Must be pulled up, if using an embedded bus.

GNT[3:0]# E11, F11, G9, G10

F12, G11, J13, J14

I/O TS

YES NO

UNKNOWN

Grant outputs from PEX 8112 Internal four-channel Arbiter. EXTARB ball must be low for these outputs to be functional. Otherwise, GNT lines are inputs; at least GNT0# must be driven from external arbitration logic.

IDSEL K9 N10 I YES NO

UNKNOWN

Ground this signal through a resistor to prevent it from floating.

INT[D:A]# E10, D11, E9, E12

E13, E14, F13, F14

I/O OD

YES NO

UNKNOWN

INT[D:A]# require external pull-up resistors, regardless of whether they are used. PCI Bus interrupt signal. Requires mapping in the Configuration Header Interrupt Line/Pin registers (offsets 3Ch and 3Dh, respectively). INTA# is connected to device 0,4,8 … For connecting multiple devices, please use the following connectivity recommendation: INTB# is connected to device 1,5,9 … INTC# is connected to device 2,6,10 … INTD# is connected to device 3,7,11 … See PCI Specification rev 2.3, Section 2.2.6 for additional information as well as the PEX 8112RDK-F Hardware Reference Manual for


Signal Name




schematic example.

IRDY# L5 P5 I/O

STS YES NO

UNKNOWN

PCI Bus Initiator Ready signal. Output when PEX 8112 is a Bus Master. Must be pulled up, if using an embedded bus.

LOCK# M3 P4 O

STS YES NO

UNKNOWN

Output in Forward Bridge mode. Input in Reverse Bridge mode.

PAR J1 J4 I/O TS

YES NO

UNKNOWN PCI Bus Parity signal.


Signal Name




PCLKI D12 E12 I YES NO

UNKNOWN

Must be connected to an oscillator or to PCLKO through a feedback resistor.

PCLKO H10 H14 O TP

YES NO

UNKNOWN

Secondary PCI Bus Clock. Clock output frequency controlled in Device Initialization register (offset 1000h[3:0]).

PERR# J3 L2 I/O

STS YES NO

UNKNOWN

PCI Bus Parity Error signal. Driven by PEX 8112 when a Target. Otherwise, passed across the bridge to the host. Must be pulled up, if using embedded bus.

PMEIN# H12 L14 I S

YES NO

UNKNOWN

Valid only in Forward Bridge mode. When asserted Low, signals request for device to enter Power Management state. Check WAKEOUT# signal to verify that Power Management state has been entered. PMEIN# should be pulled up externally.

REQ[3:0]# H11, G12, H9, G11

H11, H12, K13, K14

I/O TS

YES NO

UNKNOWN

Request Inputs for PEX 8112 four-channel internal Arbiter. EXTARB ball must be low for these inputs to be functional. Otherwise, REQ# lines are outputs; at least REQ0# must be connected to external arbitration logic.

SERR# J2 L1 I/O OD

YES NO

UNKNOWN

PCI Bus System Error signal. Driven by PEX 8112 when a Target. Otherwise, passed across the bridge to the host. Must be pulled up, if using an embedded bus.

STOP# L4 N4 I/O

STS YES NO

UNKNOWN

PCI Bus STOP signal. Driven by PEX 8112 when a Bus Target. Must be pulled up, if using an embedded bus.

TRDY# M4 M5 I/O

STS YES NO

UNKNOWN

PCI Bus Target Ready signal. Output when PEX 8112 is a Bus Target. Must be pulled up, if using an embedded bus.


4.1.9. PCI Express Interface Signals Table 9 PCI Express Interface Connections

Signal Name Ball #

(144-Ball Package)



GPIO[3:0] A11, B10, A10, C9

B12, D11, A12, C10

I/O PU

YES NO

UNKNOWN

General Purpose I/O balls that can be configured for a variety of uses within the device through the General-Purpose I/O Control register (offset 1020h). (Refer to Section 4.3.4, “GPIO[3:0] Balls.”) GPIO[3:1] should be pulled up if unused.

PERn0 B7 B9 I

DIFF YES NO

UNKNOWN

PCI Express negative polarity differential Lane Receive signals.

PERp0 A8 A8 I

DIFF YES NO

UNKNOWN

PCI Express positive polarity differential Lane Receive signals.

PETn0 A4 B5 I

DIFF YES NO

UNKNOWN

PCI Express negative polarity differential Lane Transmit signals. Series 100 nF AC coupling capacitor required on each transmit pair.

PETp0 B5 A6 I

DIFF YES NO

UNKNOWN

PCI Express negative polarity differential Lane Transmit signals. Series 100 nF AC coupling capacitor required on each transmit pair.

WAKEIN# C12 D14 I YES NO

UNKNOWN Pull High in Forward Bridge mode.

WAKEOUT# A9 A11 O YES NO

UNKNOWN

Valid only in Forward Bridge mode. Enable Low after PME# is asserted and device is in the L2 power saving state.


4.2. Schematic Connections - Reverse Bridge Mode

APPLICATION – ADD-IN BOARD EMBEDDED DAUGHTER BOARD UNKNOWN

CUSTOMER – ________________________________ DATE – ___________________ PEX 8112 Schematic Checklist – Reverse Bridge Mode

Bridge Configuration Setting Mode Recommendations

Reverse Reverse Bridge Verify that the FORWARD ball is pulled Low.

Arbitration Mode Internal Verify that the EXTARB ball is pulled Low.

External Verify that the EXTARB ball is pulled High.

Clock Mode

Master Review schematic PCI Clock connection. If PCLKO is being used as a Clock source for PCI Target behind the bridge, PEX 8112 is in Clock Master mode.

Slave Review schematic PCI Clock connection. If PCLKI is being connected to the PEX 8112 and the Target behind it, PEX 8112 is in Clock Slave mode.


4.2.1. Clock Interface Signals REFCLK must be provided to the PEX 8112 even if no devices are connected to the downstream PCI Express port. If REFCLK is not present, configuration accesses on the upstream PCI bus will be continuously retried. Table 100 Clock Interface Connections

Clock Sources/ Signal Names



Type Termination Recommendations

External REFCLK Clock Transmitter

N/A N/A External- CML

YES NO

UNKNOWN

For HCSL clock driver, a 33-Ohm series and 49-Ohm shunt is required on each differential pair(See Figure 19-3 in the PEX 8112 databook). Maximum clock frequency tolerance allowed for REFCLK source is ±300 ppm. Confirm that the device’s REFCLK oscillator supports this. Note: REFCLK termination varies depending on the type of clock driver used (see Section 19.4.2 PCI Express REFCLK DC Specification in the PEX 8112 databook for examples)

REFCLK- Input B6 A7 I

DIFF YES NO

UNKNOWN

REFCLK+ Input A6 B7 I

DIFF YES NO

UNKNOWN


4.2.2. Reverse Bridge Mode-Specific Signals Table 11 lists the settings to check when the PEX 8112 is in Reverse Bridge mode.

Table 11 Reverse Bridge Mode-Specific Connections

Signal Name Ball #

(144-Ball Package)



BAR0ENB# E8 A10 I

STRAP YES NO

UNKNOWN

If pulled Low, BAR 0 space is reserved for Memory-Mapped Configuration and Shared Memory access.

DEVSEL# K4 M4 I/O

STS PU

YES NO

UNKNOWN

PCI Bus Device Select. Driven by PEX 8112 when a Bus Target and has been addressed by the Master. Must be pulled up, if using an embedded bus.

EXTARB K11 M12 I

STRAP YES NO

UNKNOWN

If pulled Low, Internal Arbitration is used on the Primary side. Otherwise, when pulled High, external arbitration logic is required. Pull this ball High when the PEX 8112 is connected to a native PCI slot on the motherboard.

FORWARD L11 M13 I

STRAP YES NO

UNKNOWN

Must be pulled Low to enable Reverse Bridge mode.

FRAME# M5 L5 I/O

STS PU

YES NO

UNKNOWN

PCI Bus Frame signal. Output with PEX 8112 is a Bus Master. Must be pulled up, if using an embedded bus.

GPIO[3:0] A11, B10, A10, C9

B12, D11, A12, C10

I/O PU

YES NO

UNKNOWN

Behavior of these balls depends on the silicon revision. Refer to Section 4.3.4, “GPIO[3:0] Balls.”

IDSEL K9 N10 I YES NO

UNKNOWN

This signal should be connected to one of the upper 16 AD Bus lines, or driven by external logic.

INT[D:A]# E10, D11, E9, E12

E13, E14, F13, F14

I/O OD PU

YES NO

UNKNOWN Connect directly to PCI Bus.

IRDY# L5 P5 I/O

STS PU

YES NO

UNKNOWN

PCI Bus Initiator Ready signal. Output when PEX 8112 is a Bus Master. Must be pulled up, if using an embedded bus.

LOCK# M3 P4 I

STS YES NO

UNKNOWN

Input in Reverse Bridge mode. Output in Forward Bridge mode. Pull up, if unused.


Signal Name Ball #

(144-Ball Package)



M66EN D10 D13 I YES NO

UNKNOWN

Connect to M66EN signal on PCI connector.

PCIRST# F10 G14 I

TP YES NO

UNKNOWN

Input in Reverse Bridge mode, to allow Host to reset PCI Express secondary bus. Refer also to Section 4.3.2, “Reset.”

PCLKI D12 E12 I YES NO

UNKNOWN

Connected to PCI Bus PCI Clock input on primary side of bridge.

PERR# J3 L2 I/O

STS PU

YES NO

UNKNOWN

PCI Bus Parity Error signal. Driven by PEX 8112 when a Target. Otherwise, passed across the bridge to the host. Must be pulled up, if using embedded bus.

PCLKO H10 H14 O YES NO

UNKNOWN

Used to generate PCI Clock output for PCI Bus. Unused in Reverse Bridge mode.

PCLKO62SEL# C2 C3 I

PU YES NO

UNKNOWN

When pulled Low with M66EN High, causes the PCLKO clock to be derived from an internal low-jitter PLL. PCLKO is 62.5 MHz, with a 50% Duty cycle. Okay to leave no connect if no external trace is attached.

PMEIN# H12 L14 I S

YES NO

UNKNOWN

PMEIN# should be pulled up externally. No function in Reverse Bridge Mode.

PMEOUT# L12 M14 OD YES NO

UNKNOWN

Valid only in Reverse Bridge mode. Used to request a change to PCI Power Management state. Output is not 5V tolerant. If interfacing to 5V, I/O Voltage Translator circuits are required. If not used, it is okay to leave as no connect.

SERR# J2 L1 I/O OD PU

YES NO

UNKNOWN

PCI Bus System Error signal. Driven by PEX 8112 when a Target. Otherwise, passed across the bridge to the host. Must be pulled up, if using an embedded bus.

STOP# L4 N4 I/O

STS PU

YES NO

UNKNOWN

PCI Bus STOP signal. Driven by PEX 8112 when a Bus Target. Must be pulled up, if using an embedded bus.

TRDY# M4 M5 I/O

STS PU

YES NO

UNKNOWN

PCI Bus Target Ready signal. Output when PEX 8112 is a Bus Target. Must be pulled up, if using an embedded bus.

WAKEIN# C12 D14 I YES NO

UNKNOWN

Used as an input to wake up a link that is in the L2 Power Saving state.


For Bridge mode-specific connections (those that are not listed in Table 11), refer to the Connection tables provided in Section 4.1, “Schematic Connections – Forward Bridge Mode,” as delineated in Table 12.

Table 12 Bridge Mode-Specific Connections

Signal Type Review the Connections Listed In

Clock Interface Table 1

Reset Table 2

Serial EEPROM Table 3

Strapping Table 4

Power Supply Table 5

JTAG Table 6

No Connect Table 7

PCI Interface Table 8

PCI Express Interface Table 9


4.3. Additional Schematic Guidelines

4.3.1. Power Sequencing It is highly recommended that the power supplies on the PEX 8112 be sequenced in a specific manner. In particular, the VDD5 (VIO) and VDD3.3 (3.3V) voltage should ramp up before the Core Voltage (1.5V). Refer to the PEX 8112AA Data Book v1.0 for details.

4.3.2. Reset The PEX 8112 requires the PERST# signal to be asserted for at least 100 ms, after the board’s power is stable, to allow the device to initialize correctly. Implement Power-On Reset and Power Valid detection circuitry on the board to meet these requirements. Refer to the PEX 8112 RDK Hardware Reference Manuals for suggested reference circuits.

4.3.3. Mid-Bus Probe Pads If the design contains embedded PCI Express links (for example, PCI Express connection(s) between the PEX 8112’s port(s) and endpoint(s) embedded on the same board) it is useful to add probe pads for each embedded PCI Express link connected to the PEX 8112. Probe pads can be helpful when it is necessary to debug a problem on a PCI Express link with a PCI Express analyzer. PCI Express Analyzer manufacturers provide circuitry, called Mid-Bus Probes, to help debug embedded links. If planning to implement Mid-Bus Probe footprints in the PCB design, be aware that they can induce jitter and/or reduce signal integrity on the PCI Express lanes to which they are connected.

Each manufacturer usually provides a probe footprint to be implemented on the board for debugging purposes. For further details, contact PLX Technical Applications.

4.3.4. GPIO[3:0] Balls In the PEX 8112, when GPIO0 is high, link up is successful on the x1 PCI Express link.

The GPIO outputs that indicate successful link up should be connected to an LED so that the Link Up state of the x1 PCI Express lane can be visually inspected. Determining whether the PEX 8112 is correctly linking up can help diagnose system bring-up issues.

In the PEX 8112, pull-up GPIO[3:1] if unused in the design. The GPIO balls can be configured to perform different functions on the PEX 8112. They can buffer Link Training State Machine states, generate interrupts, or buffer the state of internal bit settings in the General Purpose I/O Control register (offset 1020h). Refer to the PEX 8112AA Data Book v1.0 for further details.


4.3.5. M66EN Ball The M66EN ball allows the PCI connector to choose a PCI Bus clock speed of either 33 or 66 MHz by driving the M66EN ball either low or high, respectively. In the PEX 8112, ensure the M66EN ball is connected to the PCI connector.

4.3.6. Spread Spectrum Clocking (SSC) The PEX 8112 supports a Spread Spectrum REFCLK source. The SSC clock must originate from the PCI Express connector on a slot in the motherboard or through a common Clock source that is being distributed to all add-in boards and/or PCI Express devices in the system. If the REFCLK source is non-SSC, it might be necessary to have separate REFCLK sources on different boards or devices, as long as their frequency difference is within ±300 ppm (~30 ps for a 100 MHz Clock source). Refer to the PEX 8112 Quick Start Design Note for further details.

4.3.7. Embedded PCI Buses If the PEX 8112 sources an embedded PCI Bus segment on the Target board, all PCI Interface signals such as FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, PERR#, and SERR#, must be pulled up. This is not required if the PCI interface is connected to a motherboard slot, because the backplane should pull up these signals by default.

4.4. Optimizing for Performance PEX 8112 has specific register and bit settings that allow performance optimization of the device for Memory Read transactions (in particular, the Blind Prefetch, Maximum Read Request Size, and Programmed Prefetch bits). These bits allow the PEX 8112 to prefetch a user-defined length of data during each Memory Read operation. Prefetching Read data by the bridge can improve performance by eliminating host access for each DWORD needed by the PCI Bus. Instead, the bridge prefetches the data and provides it directly from its Read cache to the Target on the secondary bus. Prefetch data block sizes must be adjusted to closely match to the burst size of the read data required from the host. Otherwise, the PEX 8112 must discard the Prefetched data, which can reduce performance.

Changes to these registers must be saved in a serial EEPROM image, so that the serial EEPROM will override the default settings of the PEX 8112 (which disables Prefetching by default), when it exits reset.

4.5. Serial EEPROM Guidelines Use of a serial EEPROM is optional for The PEX 8112, but we highly recommend laying out the EEPROM circuit even though it can remain unpopulated.


5. PCB Routing Guidelines Because PCI Express links operate at high speeds, proper PCB routing of each Receiver (RX) and Transmitter (TX) pair for each lane is critical for maintaining signal integrity on each PCI Express link. The PCI-SIG provides numerous suggestions for correctly designing PCBs containing PCI Express links. Important guidelines are discussed in the following sections. Additional information is available from the PCI-SIG website, http://www.pcisig.com.

5.1. Routing Recommendations Recommended Microstrip Trace Routing Guidelines:

Differential Impedance: 4, 6 layer – 100 Ohms ±20% 8, 10 layer – 85 Ohms ±20%

Single ended Impedance: 4, 6 layer – 60 Ohms ±15% 8, 10 layer – 55 Ohms ±15%

Recommended Stripline Trace Routing Guidelines: Differential Impedance:

6 layer – 100 Ohms ±15% 8, 10 layer – 85 Ohms ±15%

Single ended Impedance: 6 layer – 60 Ohms ±15% 8, 10 layer – 55 Ohms ±15%

Recommended for all differential signal pairs – Maintain ≥20 mil trace edge to plane edge gap. Recommended length matching Intra-pair – Maximum 5-mil delta, matching maintained segment to segment,

match at point of discontinuity, but avoid “tight bends.” Ground-referenced signals are recommended. Use stitching capacitors with PWR referenced signal traces. Use Ground stitching vias by signal layer vias for layer changes. Do not route over plane splits or voids. Allow no more than 1/2 trace width routed over via antipad. Match left/right turn bends, where possible. No 90° bends or “tight” bend structures. The Reference Clock signal pair should maintain the same reference plane for the entire routed length and should

not cross plane splits (breaks in the reference plane). Reference Clock terminating components should be placed as close as possible to their respective device, ideally

within 100 mils of the Clock/Receiver component ball. Match all segment lengths between differential pairs along the entire length of the pair. Maintain constant line impedance along the routing path, by keeping the same line width and line separation. Avoid routing differential pairs adjacent to noisy signal lines or high-speed switching devices, such as clock chips. Recommended Reference Clock differential pair spacing (clock-to-clock#) is <11.25 mils. Recommended Reference Clock trace spacing to other traces is >20 mils. Recommended Reference Clock line width is >5 mils. When routing the 100-MHz Differential Clock, do not divide the two halves of the Clock pair between layers. Recommended Reference Clock trace impedance:

Single ended – 50-60 Ohms ±15% Differential – 100 Ohms ±20%

Recommended PCI Express Reference Clock to PCI Express Reference Clock length matching to within 25 mils. AC Coupling Capacitors

The same package size and capacitor value should be used for each signal in a differential pair. Locate capacitors for coupled traces in a differential pair at the same location along the differential traces.

Place them as close to each other as possible. The “breakout” into and out of the capacitor mounting pads should be symmetrical for both signal lines

in a differential pair. Test points and probing structures should not introduce stubs on the differential pairs. Use Tantalum or Low ESR Lane AC coupling capacitors.


6. Reference Documents PEX 8112AA Data Book, Version 1.0 or higher

http://www.plxtech.com/8112

PEX 8112 Hardware Reference Manuals http://www.plxtech.com/products/pci_express/PEX8112/rdk.htm

PCI Express Add-in Card Compliance Checklist, Revision 1.0, PCI-SIG http://www.pcisig.com/developers/compliance_program/compliance_checklist Note: Membership to PCI-SIG is required to access this document.

PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a

Intersil ISL6123 Power Sequencing Controller Data Sheet http://www.intersil.com/data/fn/fn9005.pdf

Revision History Version Date Comments

1.0 April 16, 2007 Initial release. 1.1 November 7, 2007 Updated EERDDATA recommendation in table 3. 1.2 March 3, 2008 Deleted trace length mismatch section.

1.3 November 12, 2009

Corrected the Table Numbering. Updated the following recommendations: * External REFCLK Clock Transmitter in Table 1 Section 4.1.1 and Table 10 Section 4.2.1 * M66EN in Table 4 Section 4.1.4 * INT[D:A]# in Table 8 Section 4.1.8 and Table 11 Section 4.2.2 * PMEIN# in Table 8 Section 4.1.8 * PMEOUT# in Table 8 Section 4.2.2 Moved PCLKO62SEL# into Table 4 Section 4.1.4 and added it to Table 10 Section 4.2.2. Added PMEIN# into Table 10 Section 4.2.2. Added 4.2.1, REFCLK required in Reverse Mode Revised the following Sections: * Section 4.3.1 Power Sequencing * Section 4.3.4 GPIO[3:0] Balls * Section 4.5 Serial EEPROM Guidelines.