Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline

Jeffrey T. Muehring and John K. AntonioSchool of Computer Science

University of Oklahomaantonio@ou.edu

2000 MAPLD Conference

The 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies

International Conference

September 26-28, 2000

Outline

• Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR)

• Proposed FPGA-based “deep-pipeline” solution for SAR

• An initial comparison of multiprocessor-based and FPGA-based solutions for SAR

• A framework for minimizing power consumption of deep pipelines based on signal activity transformations

• Summary

Typical Scenario for SAR

“Predator”

Targets

Azim

uth

Velo

city

Range

Footprint

Footprint of Aerial Side-Looking SAR

vReal Azimuth Resolution

Rs

Offset Overlapping Beams

Azim

uth

vR

Rs

CompressedResolution

Synthetic Beams

Input Data Stream

Outputs

Phase 1Range Processing

Phase 2Azimuth Processing

Two Main Phases of Computation for a SAR Processing

Time

S1

S2

Proc

esso

r Set

s

Overview of SAR Processing

Typical Timing Diagram for Executing SAR on a Multiprocessor System

Phase 1Range Processing

(shown distributed across 3 processors)

Phase 2Azimuth Processing

(shown distributed across 4 processors)

range samples

puls

es

distributedcorner turn

Typical Communication Requirements for SARon a Multiprocessor System

range processor 1

range processor 2

range processor 3

azimuth processor 1

azimuth processor 2

azimuth processor 3

azimuth processor 4

Reference:T. Einstein, “Realtime Synthetic Aperture Radar Processing on the RACE Multicomputer,” App. Note 203.0, Mercury Computing Sys, 1996.

pulses

rang

e sa

mpl

es

AzimuthProcessing(a-tap FIR)*

Typical Processing Flow for SAR on a Multiprocessor System

Output Image

1 n

1

m

1 n

1

n1 m

1

n

1 m

RangeProcessing(r-tap FIR)*

DistributedCornerTurn

Input Data(Pulse Returns)

*Typically performed using FFT-based fast convolution technique

Outline

• Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR)

• Proposed FPGA-based “deep-pipeline” solution for SAR

• An initial comparison of multiprocessor-based and FPGA-based solutions for SAR

• A framework for minimizing power consumption of deep pipelines based on signal activity transformations

• Summary

AzimuthProcessing(a-tap FIR)

Tracing of Computational Dependencies for a Single Input Range Bin

Output Image

1 n

1

m

1 n

1

n1 m

1

n

1 m

RangeProcessing(r-tap FIR)

DistributedCornerTurn

Input Data(Pulse Returns)

(m/2)-th pulse return

(assume r = 3)

(assume a = 5)

Computation of Output Values Associated with Single Input Range Bin using Proposed Deep-Pipe

1 n

1

n

1 m

Deep Pipeline(a × r)-tap FIR

interspersed with a × (n - r) delay elements

Input Data(Pulse Returns)

(m/2)-th pulse return

(assume r = 3, a = 5, n = 10)

1

n

Computation of Output Image Samples:

1 m

after c cycles

1

n

1 m

after c + 1 cycles after c + n cycles

1

n

1 m

after c + (a × n) cycles

Note: each output value is the sum of a × r weighted input values

a2r1 a2r0 a1r1 a1r0 a0r1 a0r0

Example: no. range bins = n = 4 range kernel size = r = 2 azimuth kernel size = a = 3

Structure of the Deep-Pipeline

R0>

R1>

R2>

R3>

R4>

R5>

R6>

R7>

R8>

R9>

+

input stream

output stream

+ +

+

+

no. registers = (a × n) – (n – r) no. KCMs = (a × r)

Outline

• Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR)

• Proposed FPGA-based “deep-pipeline” solution for SAR

• An initial comparison of multiprocessor-based and FPGA-based solutions for SAR

• A framework for minimizing power consumption of deep pipelines based on signal activity transformations

• Summary

Example SAR Scenarios

300200100v(velocity, m/s)

.512δ(resolution, m)

DifficultMediumSimpleApplication Parameters

.03λ (wavelength, m)

20,000Rs (range swath, m)

100,000R (range, m)

ParameterValues

RadarParameters

The following sets of application parameters define three SAR scenarios

The following radar parameters are assumed for all scenarios

244.5Q(M samples/sec)

6,0001,500375a(azim. ker. size)

4,0962,0481,024r(range ker. size)

40,00020,00010,000n(no. range bins)

DifficultMediumSimpleComputational

Parameters

Computational Parameters for Three Scenarios

Comparison of Multiprocessor-based and FPGA-based Approaches for Three Scenarios

Taps: 24 MRegs: 240 M

Taps: 3.1MRegs: 30 M

Taps: 0.384 MRegs: 3.75 M

FPGA

DSPs: 78 + 73= 151

Mem: 50 + 8,640 = 8.7 GB

DSPs: 13 +11= 24

Mem: 4 + 1,080= 1.1 GB

DSPs: 2 + 2= 4

Mem: 0.23 + 135= 135 MB

Multiprocessor1

DifficultMediumSimpleComputational

Approach

1 Based on SHARC 21060 DSPs and assumes fast (FFT-based) convolutions

• The multiprocessor approach requires complex interconnection network plus significant RAM

• The FPGA approach only needs simple systolic connections among FPGAs

Outline

• Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR)

• Proposed FPGA-based “deep-pipeline” solution for SAR

• An initial comparison of multiprocessor-based and FPGA-based solutions for SAR

• A framework for minimizing power consumption of deep pipelines based on signal activity transformations

• Summary

c0

c2

c1

a0

a1

a2

input signal

activities

M

∑−

=

+=1

0

2

21 W

iiileakavg cafVPP

Deep PipelineWinput stream

output stream

W

Power Consumption Model

Measured and Predicted Power Consumption for FIR Filter on Xilinx 4036

0 2 4 6 8 10 12 14 162.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

4.2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 all measured

Powe

r (W

)

Data Sets

T. Osmulski, et al, “A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA,” Proceedings of The 5th International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC 2000), in Lecture Notes in Computer Science, May 2000, pp. 776-783

Using Activity Transformations to Minimize Power Consumption

• Some input lines are “hot” (high capacitance)other input lines are “cold” (low capacitance)

• May be possible to apply linear transformation to input datato appropriately match input line activity vector to capacitance vector

Deep PipelineAssume Power Model

P(a’)input

stream output stream

-1TT

Min {P(T(a))}T

a a’

• Assuming activity vector a is known or estimated, determine transformation T to minimize power consumption of deep pipeline:

Summary

• An FPGA-based approach was proposed as an alternative to the “traditional” multiprocessor approach for SAR processing

• The proposed FPGA-based approach looks promising in terms of inherent hardware complexity, but is probably not practical for implementation with currently available FPGA parts

• The proposed FPGA-based approach is applicable toother multi-phased embedded radar applications (e.g., STAP – Space Time Adaptive Processing)

• A framework was proposed for minimizing power consumptionfor a class of FPGA designs based on input signal activity transformations