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PDH and SDH 2

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Intersymbol interference in the Detection process (a) typical

baseband digital system and (b) equivalent model

Receiving

filterDetector Xk'channel

Noise

T

Xk

X1 X2

X3T

Transmitting

filter

Xk

X1 X2

X3T

H(f)

h(t)

T

pulse 1 pulse 2

Detector Xk'

(a)

(b)

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Nyquist channels for zero ISI (A) Rectangular system Transfer

function H(f) (B) Received Pulse Shape h(t)= Sin (t/T)

f

H(f)

-1/2T 0 1/2T

T

h(t)

t

-T 0 T

(a) (b)

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Sampling with a jitter reference clock

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output

jitter

amplitudeN=3

N=2

N=1

slope= Bd

Time

d

Timet=T t=T+N/B

Equivalent

input jitter

amplitude

A jitter passed along chain of N repeaters due to a

sudden pattern change at time t=T

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10-2 10-1 1f/B

dB

0

40

20

N=100

N=10

N=1

0dB =jitter introduced at

each regenerator

The normalized power density spectra for a route

containing 1,10 and 100 repeaters

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receiving signal level [mV]

threshold level

time

data transition peak jitter

jitter free data crossing

position of jitter free

reference clock

Jitter free data

crossing (nominal)

JDP

JCP JCP

Ts/2 Ts/2Ts= nominal symbol duration

JSCP>Ts/2 JSCP>Ts/2

SAMPLING WITH A JITTERY REFERENCE CLOCK

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Information

pulseEye jitter limit

clock jitter limitTiming interrogation pulse

(extracted clock)

Eye width WDD

d d

BINARY EYE AND ASSOCIATED CLOCK WITH JITTER

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Received Signal level (mV)

Time

Jitter free data

crossing

Jitter free data crossing

(nominal)

Position of jitter free reference

clock

Ts/2Ts/2

Ts = symbol duration

Threshold level

JITTER FREE EYE PATTERN

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FCC regulations Digital Hierarchy

Authorized

Frequency

Band (GHz)

Allowable

Bandwidth

(MHz)

Minimum

capacity of

Encoded Voice

Channels (N)

Corresponding

PCM Bit rate,

No. of 64Kbps

(In Mbps)

Closet

Hierarchy

Level and Bit

Rate (Mbps)

No. of

PCM

channels

in

HierarchyEfficiency

2.110-2.130 3.5 96 6.144DS-2

6.31296 1.8

2.160-2.180 3.5 966.144

DS-2

6.312 96 1.8

3.770-4.200 20 1152 73.7282 DS-2

Approx 901344 4.5

5.925-6.425 30 1152 73.7282 DS-2

Approx 901344 2.25

Table- FCC-Authorized Frequency Bands and the North American Digital Hierarchy

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FDM Digital

CCIR Rec.Frequency

Band

(GHz)

Frequency

Range

(MHz)

Channel

Spacing

(MHz)

Channel

Capacity

Band

Capacity*

Channel

Capacity

Band

Capacity

2

1700-1900

1900-2100

2100-2300

2500-2700

14 60,120,300 6 __ __ 283-2

1700-2100

or

1900-230029 600-1800 6 __ __ 382-2

4 3700-420029

40

600-1800

1260

6

6

__

__

__

__

382-2

382-2

65925-6425

6430-7110

29.65

40

20

1800

2700

1260

8

8

16

__

__

__

__

__

__

383-1

384-2

384-2

Table-2 CCIR Frequency Allocations

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FDM DIGITAL

Frequency

Band

(GHz)

Frequency

Range

(MHz)

Channel

Spacing

(MHz)

Channel

Capacity

Band

CapacityChannel Capacity

Band

Capacity*CCIR Rec

7 7425-7725 7/14 60, 120/300 20 __ __ 385

88200-8500

7725-8275

11662

29.65

960

1800

6

8

__

__

__

__

386-1

386-1

11 10700-11700 40 1800 12MEDIUM

(480-960)11 387-1

1312750-

13250

28

14

35

960

300

__

8

Additional

__

960#

240

720

8

Additional

497

497

497

Table 3- CCIR Frequency Allocations

*Go and return channels

# using 480 channels on both polarizations

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FDMFrequency

Mod Mixer RF stage

RF Local

oscilattor

voice

data

video

BB IFRF

Analogue Microwave Transmitter

Antenna

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Digital Microwave Transmitter

TDM PSK orQAM Mod Mixer RF stage

RF Local

oscilattor

voice

data

video

BB IFRF

Antenna

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RF

stage

Frequency

DemodMixer

Local

oscillator

FDM

MUX

voice

data

video

BBIFRF

antenna

Analogue Microwave Radio Receiver

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RF

stage

PSK or QAM

DemodMixer

Local

oscillator

TDM

MUX

voice

data

video

BBIFRF

antenna

Digital Microwave Radio Receiver

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Down

ConverterDeMod

Pulse

RestorationMOD

UP

Converter

IF BB BB IFRFRF

Regenerative Repeater

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(n,k) FEC

encoder

K K r

n = K + r

K= message bits

r = check bits

n = code words

A Block Encoder

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TX

Input

Data

Outer

Encoder

Inner

Encoder

Inner

Decoder

Outer

Decoder

RX

Output

Data

Link

Concatenated Code

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11 1 1 10 00 0Voltage

t

ASK

FSK

PSK

t

t

t

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Phase

state

or

Phase

state

or

Baseband input

1

0

D2

D1

D4

D3

BPSK Modulator (Ring Modulator)

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MODBaseband

carrier

0 1

Phase state when

Baseband signal is 0

(out of phase)

Phase state when

Baseband signal is 1

(inphase)

Space diagram

Baseband Input Diode Mod Output

1D1,D2 short

D3,D4 open

In-phase

0D1,D2 open

D3,D4 shortOut of phase

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Serial toparallel

converter

Tx

osc:

Phase

shift BPF

0

90

0180

90

270

I

Q

11

1000

01

Baseband

data input

Symbol

rate fb/2

Symbol

rate fb/2

IF

4 QPSK Modulator

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Power

Splitter

Carrier

recovery

Phase

splitter

Symbol timing

Recovery

STR

Output

data0

90

I

Q

IF

LPF

LPF

Threshold

Comp

ThresholdComp

Parallel tp

serial

converter

4 QPSK Demodulator

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Data

distributor

2 level to

4 levelconverter

2 level to

4 level

converter

Inverter

DSB-SC

Mod

DSB-SC

Mod

90

Local

osc: BPF

Fb/3

Fb/3

Fb/3

IFBaseband

input

8 PSK Modulator

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a amplitude state of

the a vector

b amplitude state of

the b vector

Single state space diagram of 8 PSK Modulator

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/2

+

I

/4Q

/4

DQPSKModulator IF

Baseband

input

0 /2

3/2 2

/2

+

I

/4Q

/4

DQPSKModulator IF

Baseband

input

0

0

3/2

3/4

/2

/4

7/45/4

/4 DQPSK Modulator and its Signal Constellation

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/m

-/m

Phase Decision

Threshold

=0 noise free

ref: vector

Errorregion

E1

E2

01

10

11

00 Vector transmitted error free

01 Vector transmitted erroneous

f

BW

N

C

N

E

b0

b

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Eb= Average energy of a bit

fb = Transmitted Bit rate (1/Tb) Tb= Unit Bit Duration

C= Average Carrier Power

N0= Noise Power Spectral Density that isaverage Noise Power in 1KHz Bandwidth

BW = Noise Bandwidth of Receiver

f

BW

N

C

N

E

b0

b

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+

Delay Tb

Encoded

Data out

Modulo 2

Adder

Input

data

Differential Encoder For Differential

Phase Shift Keying Modulator

DPSK is often used instead of BPSK because DPAK

receiver does not require a carrier synchronizer circuit.

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Delay Tb

90

Phase shift

dtT

0

dtT

0

Synchronizer

Sampler

Sampler

b1

b2

/4 DQPSK Demodulator

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00

10

01

11

01

00

10

11

M = 4, =0 M = 4, =/4

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High Speed Digital

Communicate Multiplexer

Analog

BPF

Band Limited

8PSK Output

DIGITAL PHASE SHIFTER

0 45 90 135 180 225 270 315

Digital IF Local Oscillator

fb

fbfb

8 PSK High Speed Modulator

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Data

2 to L

level

Converter

2 to L

level

Converter

Pre-Mod

LPF

Pre-Mod

LPF

Local

osc:

Phase

Splitter BPF

I

P

fb/2 . 1/log2

L

fb/2 . 1/log2 L

fb/2

fb/2

DSB-SC

AM MOD

DSB-SC

AM MOD

0

90

16 State QAM Modulator

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Amp

LPF

LPF

S

T

R

C

R

0

90

l

O

g

I

c

Vn1

Vn2

Vn(L-1)

L to 2 level

converter same as

design for I ch

X2 data

combiner

Data

Output fb

0

90

M-Ary QAM or M-Ary PSK Demodulator

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1 0

FskModulated

output

NRZ

data

Fsk

modulator

carrier

0 T

1 0 1

MSK Minimum Shift Keying

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Gaussian Minimum Shift Keying

Input

Binary

Data

Gaussian

FilterMSK MOD

GMSK

Output

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SVLGC1

PS

RX

PS

DSC1(VF/DGTL)

B-U/U-B(WS)

MODEM

RX

TX

TX

MODEM

SVLGC2or3

No.1 No.1No.1 No.1No.2 No.2No.2 No.2

BR NTWK [Branching network]

-DSPL is removed-

Front view of uncovered DM7G-1000

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B IN/OUT 1

B IN/OUT 2

FG

WS IN

WS OUT

WS IN/OUT

G -V G -V

EXL**

EXT

EQP

ALM 1ALMEXT

SV

EXT

CONT

G : positive supply wire

(Grounded)

-V: Negative supply wire(-

24/-48V)

**VF/DGTL

EXT TEL

EQPALM 2

No.1 No.2

Rear Panel DM7G-1000

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161 MHz

56 MHz

7725 MHz300 MHz

7425 MHz

V(H)

H(V)

1

5

9 17

13

1'

5'

9'

13'

17'

f0= 7575 MHz

Lower half of the band : fn = f0 -154+ 7n

Upper half of the band :fn = f0 +7+ 7n

Where n = 1,2,3,4,----20

RF channel Arrangement

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B-U/TDP

(ws)

WS IN

WS OUT

optional

U-B/RSW

TDP MODOSC

IFA MIX HPAPLO

RDP TVE DEM

OSC

IFA MIX LNA

PLO

IFA MIX HPA

PLO

IFA MIX LNA

PLO

TDP MOD

OSC

RDP TVE DEM

OSC

1*

3*

2*

4*

B IN x 16

B OUTx 16

RF IN/OU

B-U/U-B MODEM (No.1)

RX (No.1)

MODEM No.(2)

TX (No.1)

TX (No.2)

RX (No.2)

Branching Network

Main Signal Flow Diagram of Radio Equipment

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B-U = Bipolar to Unipolar

TDP = Transmit Data Processing RDP = Receive Data Processing

PLO = Phase Locked Oscillator

TVE = Transversal Equalizer

IFA = IF Amplifier MIX = Mixer

HPA = High Power Amplifier

LNA = Low Noise Amplifier

WS = Wayside Signal

MOD = Modulator

DEM = Demodulator

A ili Si l fl (AS 30 EXL)

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VF/

DGTL

DIG

CON

DSC INTF

(MUX/DMUX)

(STF/DSTF)

TEL/

BR NET

30EXL INTF MPU

DI

SW CONT

COM.

RAM

MPU

INTF

EXT .SV

/EXT .CONT

DRVPIU

DISPLAY

Operation

Optional

DSPL 3

spk

DSC 1

Handset

SV Logic 2 or 3 (Optional)SV Logic 1

VF/DGTL(user ch)

Other

AS-30EXLs

repeat/branchOW TEL

branch

RADIO

Multi-LVL

monitor

Alarm 2-level

RSW Control

Station

Supervisory

Control

*1

*2

*3

*4

*** At mount of SV Logic 2 unit , two serial lines.At mount of SV Logic 3 unit, parallel relay contacts.

***

Auxiliary Signal flow (AS-30 EXL)

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AS = Auxiliary signal

MPU = Microprocessor Unit

DRV = Driver

PIU = Peripheral Interface Unit

STF/DSTF = Stuffing and Destuffing

SPK = Speaker

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RX

RX

DEM

DEM

U-BB-U

MOD

MOD

TX

TX

DSC

U-SW

No.1 Modem

No.2 ModemNo.2 Modem

No.1 Modem

and

nput

B-U/U-BB-U/U-B

DSC

Input

Protection Switching for Twin-path System

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TEL

TALK

VOL

COMMON

DISP OFF Sys

almsv

almnorm

BZ off

AL-RA

IND

CHK

BZ

RST

HST

RST

SUPERVISORY

Eqp No.

8

MASTER

EQP

ALM1

2

3

4

5

67

8

ALM/STATUS

T ALM

R ALM

CH ALM

PS ALM

WS ALM

SV FL

AIS REC

AIS SEND

MAINT

AL-RA

No.1 No.28

MONITOR

COUNT1 2

No. SEL

ITEM SEL

T LVL

R LVL

+ 5.3V

+10V

-10/-5.5VDC IN[V]

EC

BER

ES

SES

DMPT

(SEC)

ON

EXEC

ON

EXEC

No.1

No.2

No.1

No.2

AUTO

INI OPNG

RSWEXT SV

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Layout of functional section of DSPL-3

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