This material exempt per Department of Commerce license exception TSU

Xilinx On-Chip Debug

Chipscope 2

For Academic Use Only

Debug and Verification is Critical

• Debug and verification can account for over 40% of an FPGA design time

• Serial nature of debug and verification can make it difficult to optimize

• Inefficient strategy may result in product launch delay – Loss in market share– Loss of first-to-market advantages

Final DeviceFinal Device

Design Design ImplementationImplementation

DesignDesignSpecificationSpecification

40%40%of of

Design Design TimeTime

Design VerificationDesign Verificationand Debugand Debug

Chipscope 3

For Academic Use Only

Traditional Debug Challenges

• Limited Internal Visibility– How do I access the embedded

system bus…• Hard IP Cores

– Can’t get internal access to…• Full Scan Insertion

– Increases overhead…• It’s Too Late Anyway!

– Re-spins are ENORMOUSLY expensive

• Co-Verification– Tools are cumbersome and slow– Modeling issues

IO Pads

IO P

ads

IO P

ads

IO Pads

Logic BIST Memory BIST Access

MemoryArray

CPUCore

IPCore

Custom Boundary Scan TAP Controller

Embedded System BusEmbedded System Bus

CustomLogic

CustomCore

Chipscope 4

For Academic Use Only

Built For Debug - the Platform FPGAIO Pads

IO P

ads

IO P

ads

IO Pads

Boundary Scan TAP Controller

Embedded System BusEmbedded System Bus

MemoryArray

PPC405Core

IPCore

CustomCore

ICON

ILA

ILA

ILA

IBA CustomLogic

ILA

• FPGA Enables Full Internal Visibility– ChipScope Pro tools provide complete

on-chip access• Access Processor System Busses

– ChipScope Pro Integrated Bus Analyzer• Flexible On-Chip Debug

– Small, efficient cores access any node or signal and can be removed at any time

• It’s Never Too Late in an FPGA!– Fix problems during development AND

after product deployment• Enable Complete System Verification

– Debug systems in real-time– No need to extrapolate behavior

Chipscope 5

For Academic Use Only

Traditional Logic Analysis MethodDedicated pins connected to logic analyzer

External Logic Analyzer

Pins

Virtex-II Pro

XC2VP20FF1152

Probepoints

• Requires Extensive Dedicated I/O for Debug– Driving signals to external I/O introduces additional problems

• Inflexible solution– Difficult or impossible to add additional debug pins if needed

• Limited visibility to on-chip activity

Chipscope 6

For Academic Use Only

JTAG

ChipScope Pro

ChipScope Pro On-Chip Debug Integrated Logic Analyzer Core

Virtex-II Pro

XC2VP20FF1152

ILA BlockRAM

Probepoints

• No I/O pins required for debug– Access via the JTAG Port

• On-Chip access to every signal and node in the FPGA design– Driving signals to external I/O introduces additional problems

• Add and remove cores at any time in the design process

Chipscope 7

For Academic Use Only

ChipScope Pro On-Chip Debug Integrated Bus Analyzer Core

ChipScope Pro

JTAGVirtex-II Pro

XC2VP20FF1152

IBA BlockRAM

SystemBusses

• No I/O pins required for debug– Access via the JTAG Port

• On-Chip System Bus Analysis– ChipScope Pro Integrated Bus Analysis of the CoreConnect On-Chip

Peripheral bus (OPB)– Includes transaction debug and protocol violation detection

Chipscope 8

For Academic Use Only

Auro

ra

OPB SDRAM

User Logic

PLB

Bus

OPB

BusBridge

OPB GPIO

Arbi

ter

Choose the Core that Best Meets Your Design Requirements

Integrated Bus AnalysisCore (IBA)

• PLB and OPB specific Bus analysis cores

• Protocol detection • Debug and verify control,

address, and data buses Agilent Trace Core 2 (ATC2)• Agilent created core enabling

On-chip debug of Xilinx FPGAs usingAgilent FPGA Dynamic Probing

Virtual Input Output Core (VIO)

• Virtual Inputs and Outputs• Stimulate logic with pulse

trains

Integrated Logic AnalysisCore (ILA)

• Access internal nodes and signals• Debug and verify signal behavior• Define detailed trigger conditions

Chipscope 9

For Academic Use Only

Debug Logic Anywhere Within the FPGA

ClockClock

Trigger 0Trigger 0Trigger 1Trigger 1Trigger 2Trigger 2Trigger 3Trigger 3

Trigger OutTrigger Out

Memory ControllerMemory

Controller

AddressAddress

DataData

ClockClock

ILAILA

• Identify logic that you need to debug and verify• ChipScope Pro cores are placed directly within the logic and …

– Function as “virtual test headers” – Provide access any signal or node with the FPGA– Debug at the system clock rate

Chipscope 10

For Academic Use Only

ChipScope Pro Tools Allow You to Add Cores at Any Time in the Design

• ChipScope Pro Core Generator– Generate and add cores at the beginning of the

design process• ChipScope Pro Core Inserter

– Target existing signals and generate and insert cores into a synthesized design

• ChipScope Pro configuration– Simplify iterative debug and verification process

Chipscope 11

For Academic Use Only

ChipScope Pro Interface Makes FPGA Debug Easy

• Access ChipScope cores via JTAG or user defined Trace port• Configure FPGA, define trigger conditions, and view data via

ChipScope Pro analyzer running on a PC

ChipScope Pro Analyzer functions as a logicanalyzer, bus analyzer, and control console

Chipscope 12

For Academic Use Only

ChipScope Pro Analyzer server connected to Xilinx development board enabled for remote

debug and verification

ChipScope Pro Analyzer server connected to Xilinx development board enabled for remote

debug and verification

Remote Debug and Verification

Debug remote systems from your office via ChipScope Pro Analyzer

client

Debug remote systems from your office via ChipScope Pro Analyzer

client

ChipScope Pro Analyzer server connected to fielded system enabled for remote debug and

verification

ChipScope Pro Analyzer server connected to fielded system enabled for remote debug and

verification

Chipscope 13

For Academic Use Only

Measures new groups of internal FPGAsignals in seconds without

– Recompiling the design – Impacting the timing of the designSave 15 min to 10 hours per new measurement

Achieves wider internal visibility over a fixed number of pins – 64 internal probe points for every pin conserves

FPGA resourcesSave 8 hours per problem by not having to create a

testbenchEliminates error prone & time consuming tasks

– Automates signal/bus labeling from FPGA design to logic analyzer

– Automatically maps FPGA pins from board layout to logic analysis channels

Save 2 to 30 minutes per new measurement

Exclusive Capability Combines On-Chip Debug with External Logic Analysis

Chipscope 14

For Academic Use Only

Compatibility

Xilinx FPGAs• Virtex-4• Virtex-II Pro• Virtex-II• Spartan-3E• Spartan-3

Core insertion/distributionChipScope ProISE design software

JTAG Cable SupportXilinx MultiLINK Parallel, Xilinx MultiLINX USB, Xilinx Parallel-IV

Agilent Logic Analyzers

1680-series1690-series

16900-series with following modules:• 16740 series• 16750 series• 16910 series• 16950 series

ProbingSoft touch, mictor, samtec, flying lead,

Chipscope 15

For Academic Use Only

Xilinx ChipScope ProEnabling Complete FPGA Debug Solutions

IBA(EDK Integration)

ILA, VIO

FPGADynamic Probing

Syst

em C

ompl

exity

Debug and Verification Resources(Deep Storage, Complex Triggers)

ILA, VIO

Chipscope 16

For Academic Use Only

What’s Next• View the ChipScope Pro

product demo online – Learn how to insert ChipScope Pro

cores into a design– Learn how to use the ChipScope Pro

analyzer to debug and verify

• ChipScope Pro for the engineering curriculum– Donations available to Professors– www.xilinx.com/univ