Xilinx Confidential – Internal © 2009 Xilinx, Inc. All Rights Reserved ChipScope Pro Software +Labs

Xilinx Confidential – Internal

© 2009 Xilinx, Inc. All Rights Reserved

ChipScope Pro Software

+Labs

Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx

Welcome

Page 2

If you are new to FPGA design, this module will help you to learn some of your debugging options

This software makes it easy to debug and verify your FPGA design


After completing this module, you will able to:

Page 3

Describe the value of the ChipScope™ Pro software and describe how it works

List the ChipScope cores and supported flows

Use the Core Inserter, CORE Generator, or PlanAhead tool flows to add ChipScope cores

Plan for debugging


What Engineers are Saying

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FPGA designs are becoming more complex– Designs are becoming faster

– Design times are becoming shorter

Debugging and verification are more challenging– Debugging and verification consume a significant portion of FPGA

design time• An FPGA design survey conducted by Xilinx indicates that FPGA debugging

and verification accounts for nearly 50% of the FPGA design time

– Debugging and verification need to be easier and integrated into the FPGA design flow


Logic of Debugging

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Debugging is problem solving– Break a problem into basic parts

– Remove or reduce variables and variation

– Predict and verify

Debugging is an iterative process

Verification is a component of debugging

– Confirming no problems remain

Modify designModify design

Probe Probe designdesign

Analyze Analyze debugging datadebugging data

Identify fixIdentify fix

Verify designVerify design

Create designCreate design

Reconfigurable nature of FPGAs enables an iterative debugging process


ChipScope Shortens Debugging

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Works the way you solve problems

– Divide a problem into basic parts

– Remove variation introduced by external debugging solutions

– Enables a very fast, iterative process of prediction and verification

Provides what you have requested

– Reduction of debugging and verification time

– A powerful tool that is easy to use

– Focus on solving the problem, not on learning the tool

– Integrated part of the Xilinx FPGA design flow

Final DeviceFinal Device

Design Design

ImplementationImplementation

DesignDesign

SpecificationSpecification

20%20%of of

Design Design

TimeTime

ChipScope™ ProChipScope™ Pro

On-Chip VerificationOn-Chip Verification

and Debuggingand Debugging

40%40%of of

Design Design

TimeTime

Shrink overall design Shrink overall design time by 25%time by 25%

Shrink overall design Shrink overall design time by 25%time by 25%


The ChipScope Pro Software

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Use the ChipScope Pro software for

– Verification and debug

– Injecting short signal sequences

– Capturing data for post-bench analysis

– Do not use the ChipScope Pro software for• A replacement for a simulation tool

– Accessing the System Monitor

– Testing high-speed I/O

– Remote diagnostics/monitoring


Optimized Debugging Cores

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Aur

ora

OPB SDRAM

User Logic

PLB

Bus

OPB

Bus

Bridge OPB GPIO

Arb

iter

Integrated Bus

Analyzer (IBA) Core– IBA/PLBv46-specific bus

analysis cores integrated with EDK

– IBA/OPB and IBA/PLB still supported

– Protocol detection

– Debugging and verification of control, address, and data buses

Agilent Trace Core 2 (ATC2)

– Agilent-created core enabling on-chip debugging of Xilinx FPGAs via Agilent FPGA Dynamic Probe

Virtual Input/Output (VIO) Core

– Virtual inputs and outputs

– Stimulate logic with pulse trains

Integrated Logic Analyzer (ILA) Core

– Access internal nodes and signals

– Debugging and verification of signal behavior

– Define detailed trigger conditions

View cores as “virtual test headers”View cores as “virtual test headers”placed anywhere in the designplaced anywhere in the design


Core Resources

ChipScope™ Pro software cores utilize FPGA resources– For what?

• Block RAM: trigger and data storage• Slice logic: trigger comparisons

You must leave room for the ChipScope Pro software cores in the FPGA

– This may require using a larger part in the same package as you will use in production

– The CORE Generator and Core Inserter tools can estimate block RAM usage, but the design may still end up with too many block RAMs

– If MAP issues an error, reduce the number of observed signals or the sample data depth to reduce block RAM usage


Using ChipScope Pro Software

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Core Core OrOr Core CoreGeneratorGenerator Inserter Inserter

ChipScope Pro Core Generator

ChipScope Pro Core Generator

Instantiate Cores into Source HDL


Connect Internal Signalsto Core (in Source HDL)


SynthesizeSynthesize

ImplementImplement


ChipScope Pro CoreInserter (into netlist)


Download and debuggingUsing ChipScope Pro software

Download and debuggingUsing ChipScope Pro software

Place ChipScope™ Pro cores into the design

– Attach internal nodes for viewing to the ChipScope Pro core

– Generate the ChipScope Pro cores by using the Core Generator, Core Inserter tool, or PlanAhead software

Place and route the design with the Xilinx ISE™ implementation software tools

Download the bitstream to the device under test and analyze the design with the ChipScope Pro software


Adding the ChipScope Pro Cores

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Use the icon or click ProjectNew Source

Select ChipScope Definition and Connection File (CDC)

– Specify a name for the core

Only one CDC file is allowed in the project at a time

– But multiple CDC files can be stored in the working directory


The ICON Core

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ICON (Integrated Control) core: This core controls up to 15 capture cores

– The ICON core interfaces between the JTAG interface and the capture cores

Capture cores: Customizable cores for creating triggers and data storage

– Customizable number, width, and storage of trigger ports • ILA (Integrated Logic Analyzer) core: Capture core for HDL designs• ATC2 (Integrated Logic Analyzer with Agilent Trace) core: similar to the

ILA core, except data is captured off-chip by the Agilent Trace Port Analyzer

• IBA/OPB (Integrated Bus Analyzer for CoreConnect On-Chip Peripheral Bus) core: Capture core for debugging CoreConnect OPB

• IBA/PLB (Integrated Bus Analyzer for CoreConnect Processor Local Bus) core: Similar to the IBA/OPB core, except for the PLB bus

• VIO (Virtual Input/Output core): Define and generate virtual I/O ports


The ILA Core

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User-selectable, one to four trigger ports

– Up to 256 channels per trigger port

– Multiple match units on the same trigger port

• Up to 16 match units- For example, 4 trigger ports, 4 match

units each = 16 match conditions

Trigger condition sequencer– Defines complex trigger sequences that

include up to 16 states or levels


Things to Know About ILA Cores

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Integrated Logic Analyzer (ILA) cores can be added with either the CORE Generator or Core Inserter tools or PlanAhead tool

A design can contain up to 15 ILA cores

Maximum speed of the ILA core varies according to device family and selected features

– Turning on more “features” generally slows down the performance of the core and causes it to consume additional fabric resources


ChipScope Pro Software VIO Core

Insert virtual pins into your design using VIO

– Inputs are virtual LEDs• Driven by internal FPGA signals

• Different refresh rates are available

– Outputs are virtual DIP switches• Force value or pulse train into the

FPGA

VIO core can be defined – Input or output

– Synchronous or asynchronous• System clock or JTAG clock

– Up to 256 bits each

Page 15


Things to Know About VIO Cores

Can only be created by the CORE Generator tool

Uses no block RAM, only logic

Inputs are like LEDs for examining signals

Outputs are switches or pushbuttons for driving signals

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CORE GeneratorCORE Generator






ImplementImplement




Download and DebugUsing ChipScope Pro Software


Core InserterFlow

Core Inserter inserts cores directly into the netlist

– HDL code is untouched

– Only post-synthesis nodes are available

– Bypass this tool to remove cores

– Inserter must perform the first portion of translate

– Core generation and insertion are done together

– ChipScope Pro Core Inserter tool is run from within Project Navigator/PlanAhead

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Things to Know About the Core Inserter and PlanAhead Flows

It is strongly recommended to set the synthesis option for “keep hierarchy” to “yes” or “soft”

– Preserves the netlist hierarchy which makes it easier to locate signals for debugging

– Enables filtering according to the design hierarchy

Design implementation will take an extra 2-3 minutes to generate the cores for the ICON and a single ILA

– Only required if new cores are added or existing cores modified

The PlanAhead and Inserter flows are not compatible with the Core Generator flow

– This flow is not available when in ISE Integration mode

Pre-existing debug cores may be viewed, but not changed Only the ChipScope Pro ICON and ILA cores may be created and connected

using the Inserter flow Probing inside NGC core files is prohibited

– Only interface signals are accessible

PlanAhead 12, ISE 12, and ChipScope Pro 12 tools must be used with this flow

– Mixing and matching tool versions is not supported


Lab 1: Core Inserter Flow

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In this lab, you will add an ILA core to an existing design and debug a clock design that is not working correctly

Objectives of the lab– Use the Core Inserter to add ILA cores to an existing design

– Define and use the ILA core within a design

– Use the ChipScope Pro software tools to configure an FPGA, set trigger conditions, analyze, and debug a design

The lab source files and instructions are included with the zip file that contains the slides and script

– Look in the support directory for more information about the labs


Integration With PlanAhead

Interactively select signals to probe– From Netlist and Schematic views, Find

command Requires a synthesized netlist

Wizard walks through the process – Configure clocks, triggers, multiple cores

– Reports number of cores, type, and clock, for example

Updates the PlanAhead tool netlist– Inserts and compiles the cores

– All subsequent runs will use cores Maintain inserted cores

– Modify probed signals, configuration Launch the ChipScope Pro Analyzer

from the completed run– Available after running BitGen Support for ILA and ICON cores

only


Selecting Signals to Debug

Select nets in the PlanAhead tool by any means

– Netlist view (nets folders)– Each level of logic hierarchy

– Schematic Add nets using Add to

ChipScope Unassigned Nets popup menu command

Find results


Exploring Core Logic

Netlist now populated with implemented core logic

– NGC module icon displayed in Netlist view (red lock)

– Expandable logic Analyze internal core logic

– Resource statistics – Block RAM requirements

– Schematic

– Connectivity Floorplan the cores

– Close to critical logic

– Away to avoid congestion


CORE Generator Tool Flow

Generate cores that are instantiated directly into the HDL

– Allows access to all HDL nodes

– Requires changes to the code

– Must comment out cores to remove them

– Uses standard implementation flow

– Core generation and insertion done separately

Core Generator tool can also be launched from latest 12.1 PlanAhead

CORE GeneratorCORE Generator






ImplementImplement






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Lab 2: Adding an ILA and VIO Core

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In this lab, you will add an ILA core and a VIO core to the clock design by using the ChipScope™ Pro software Core Generator

Objectives of the lab– Use the Core Generator to add two ChipScope Pro software cores to a

design

– Define and use the VIO core and VIO console

– Control and monitor a design by using the ChipScope Pro software

– Describe advantages and disadvantages of both ChipScope Pro flows (Core Inserter versus Core Generator)

The lab source files and instructions are included with the zip file that contains the slides and script

– Look in the support directory for more information about the labs


Summary

Page 25

Shorten debug time – Break the problem into manageable parts

– ChipScope™ Pro software enables rapid iteration

Add ChipScope Pro software cores at any time– Debug in three simple steps

Specialized cores allow you to focus on solving problems– ILA for viewing results

– VIO for driving changes

Minimal impact to FPGA design– Design at system speed

– Optimized cores consume minimal FPGA resources


Where Can I Learn More?

Visit the ChipScope Pro and Serial I/O Toolkit web page– http://www.xilinx.com/tools/cspro.htm

– ChipScope Pro 12.1 Software and Cores, User Guide, UG029

– View recorded ChipScopeTM Pro software demos• Learn how to insert Chipscope Pro Cores• Learn how to use ChipScope Pro software to debug

and verify

– Access a 60-day free evaluation version of theChipScope Pro software tools

– Obtain information on Agilent FPGA Dynamic Probe technology• Combine on-chip debugging with the power of a logic

analyzer

Page 26


Where Can I Learn More?

Xilinx Training– www.xilinx.com/training

• Xilinx tools and architecture courses• Hardware description language courses• Basic FPGA architecture, Basic HDL Coding Techniques, and other free

training videos!• Minimizing Your Design Time with the ChipScope Pro Debug and

Verification Tools course

– Includes labs and lecture on all three flows– Discusses how to get your cores to meet timing– Detailed explanation of trigger options and configuration– Explains the options for data visualization– Introduces scripting options, including TCL scripting to automate

data flow– Many techniques and case studies described– Remote access

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Trademark Information

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Xilinx Confidential – Internal © 2009 Xilinx, Inc. All Rights Reserved ChipScope Pro Software +Labs