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8/3/2019 pd design 6
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1
Objective
The objective of this module is to introduce Placement flow
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Prerequisite
Must have attended the Phase-I of ADAD program
Must be aware of commonly used terms and basic design
Must have attended the “Floorplanning “ module
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Agenda
What is placement and its need.
To identify the purpose of the pre, In and Post Place optimization
stages.
To introduce how the Timing and congestion driven setting affectplacement.
To understand the recommended Auto-Place flow , additional analyis &
optimizations as needed, after initial Auto-Placement.
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Timing Driven Placement
Drawbacks of traditional placement
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Wire Load Model based Timing
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Placement affects timing
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Detailed Routing effect
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Advantages of timing-driven placement
Timing Driven Placement
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Net Delay Calculation
Calculation uses pin to pin Steiner Routing
Each net is calculated individually. Net delay is accurately determined
using the precise location of cell and pins
No wire load models used (less loading estimation). Estimation doneafter coarse placement and legalization
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Placement Goals
Guarantee the router can complete the routing step
Minimize all the critical net delays
Make the chip as dense as possible
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Placement Flow
Design setup & Floor-plan
Detach Scan Chain
Set placement and
common options
Auto Place
Back to the Floor-plan
To CTS
Additional Optimization
No
Yes
No
Yes
Congestion OK
Timing OK
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Astro Placement Flow
Critical Range
Optimization
High-effort PPO
Iterate as
needed
Back to
Synthesis
TNS>>WNS
setup/max cap/trans
violations ?
Pass Timing
Sanity check?
Design setup & Floor-plan
Detach Scan Chain
Set placement and
common options
Auto Place
Back to FP
To CTS
No
Yes
No
Yes
Congestion OK
Timing OK
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What are Scan Chains?
Scan chains are groups of FFs that are serially connected through SI/SO
pins
Scan chain paths are active only during “test mode”, not during
“functional mode”
FFs are typically connected in alphanumeric order during synthesis –
irrelevant for DFT, but not optimal for routing
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Issue with scan Chains
If serially connected FFs are placed far apart this may require a lot more
routing resources than necessary
If FFs are placed close together, according to their scan chain ordering,
this may hurt timing along functional critical paths
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Disconnect the scan chains prior to placement to allow Astro to
focus on the functional critical paths
– Chains are ‘annotated’ first to capture the FF “grouping”
Scan chains will be reconnected after CTS
– Same grouping of FFs– Different ordering: based on placement, to
minimize routing resources
Scan-chain handling
IN[0]
SCAN_IN
OUT[0]
SCAN_OUT
IN[1] OUT[1]
IN[0]
SCAN_IN
OUT[0]
SCAN_OUT
IN[1] OUT[1]
Auto-Place
Detach Scan Chains
CTS
Connect Scan Chains
Timing
OK?
Analyze Congestion
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Placement setting
Optimization Mode
No cell under pre-route
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Location Constraint Examples
Standard cells
METAL5
No cells under Preroute of M5 Cells under Preroute of M5
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Timing options
Settings
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Auto Place
Effort : Medium
Stage: Pre-Place, In-Place,
Post-Place, Post-CTS
Optimization Tasks
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Create Minimal “seed” Netlist for Placement
Pre-Place optimization removes all WLM effects to create a minimal “seed”
netlist uses RC = 0 to
- Perform logic synthesis to meet setup timing
- reduce total cell area by gate down sizing and buffer/inverter
removal along paths with positive setup slack.
Uses estimated RCs, based on quick “throw- away” placement, to buffer non-
clock high fanout nets.
HFN: A high fanout net is,by definition within Astro, a data (non-clock) signal
net that fans out to 10 or more cells.
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High Fanout Nets are NOT Minimized
Non- clock High Fan-out Nets aresignals that fan out to many gates.
Fanout > =10
HFN trees can contain a large
number of buffers which cansignificantly impact placement.
Instead of minimizing HFN buffer
trees using RC = 0, Astro rebuilds
the HFN trees based on moreaccurate RC estimates
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
HFN
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In -Placement Optimization
Places all standard cells
Optimizes the gates for setup
timing based on VR
Performs HFN on re-synthesisbased on actual placement.
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Post-Place Optimization
Optimizes logic and placement
for setup timing
Buffers all gates based on
tran/cap constraints
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Bad placement Good placement
Placement Examples
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Definition of Congestion
Routing demand = 3
Assume routing supply is 1,
overflow = 3 - 1 = 2 on this edge.
Overflow = overflowall edges
Overflow on each edge =Routing Demand - Routing Supply
(if Routing Demand > Routing Supply)
0 (otherwise)
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Correlation between Wire-length and Congestion
Total Wire-Length = Total Routing Demand
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Wire-length = Congestion
A congestion minimized placement A wire-length minimized placement
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Analyzing congestion: 2-D map
Colors represent overflow
of demand vs. supply
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Analyzing congestion: 1-D map
Vertical routing
Horizontal routing
0.48
0.57
0.49
0.53
Average congestion as a
percentage of all routing
resources across the
vertical plane
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Analyzing Timing and Max tran/cap buffering
Generate a “Timing summary” report
Generate a detailed timing report to analyze violating
paths/nets in more detail
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Example Summary of Timing Analysis
WNS # of violationsTNS
Setup violationsIs this concern? Small # of max tran/cap
violations
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What Does it mean if TNS >> WNS?
A large TNS implies that there could be many sub-critical violations that
are almost as bad as the critical path violation
It is also possible that these paths are 'related', or share logic.
We can verify by analyzing the sub-critical paths with detailed timing
reports.
D Q
D Q
D Q
D Q
CLK
ZRelated paths
with similar
violations
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What does Optimization Do By Default?
By default, logic optimization during placement works only on the
critical path of each clock domain, and stops when it cannot further
improve its timing
Sub-critical paths are not optimized!
Critical path is optimized
Sub-Critical paths are not
optimized
paths
Timing
Timing Goal
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If TNS >> WNS Critical Range Optimization
Critical Range Optimization (CRO) works on the sub critical paths,
which reduces the total number of violations paths and the TNS
CRO may also help to reduce the critical path violations if it is 'related'
to some of the sub-critical paths
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If Still Violating – High-effort PPO
Iterate CRO and High effort
PPO if further improvements are
seen, or until the remaining
violations are acceptably small.
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Zero Interconnect Timing Analysis
After PPO+CRO you may still be left with a few timing violations
Perform a 'Timing Sanity Check', or zero-interconnect timing analysis.
Check the violations
– If zero violations : Continue on to CTS
– If still violating : Go back to Synthesis!
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Module Takeaway
After completion of this program students will be familiar with the
Placement flow, Placement optimization, and will be ready to do the
placement for any design
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Backup
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Groups and Regions
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Groups and Regions
Grouped
cells are placed together
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Groups and Regions
Grouped
cells are placed together
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What is a Floorplan?
Floorplan is the physical plan of your chip. Among other things, it defines the
size, shape and pin locations of the chip. It also defines the placeable areas for
STD cells.
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What is “placement” ?
● “Placement” is a way of assigning physical locations for the cells
described in the logical gate-level netlist.
● “Placeable” cells will be placed onto “sites” (sitting on site arrays)
which are defined in the floorplan.