PCI

Team 3: Adam Meyer, Christopher Koch, Michael Beck, and Patrick Gerber

WHAT IS IT/WHAT DOES IT DO

• PCI• Peripheral Component Interconnect

• High speed bus• Began in 1990 • Intel• PCI 1.0 on June 22, 1992

• PCI special interest group

BASIC STRUCTURE

• 32-bit or 64-bit bus• 5 functional groups of mandatory signal lines• 4 functional groups of optional signal lines

MANDATORY SIGNAL LINES

• System Pins – Clock and Reset Pins• Address and data pins – 32 lines that are time

multiplexed for addresses and data. Also contains lines used to interpret and validate signal lines carrying addresses and data• Interface control pins – Control timing of

transactions and provide coordination among initiators and targets

MANDATORY SIGNAL LINES

• Arbitration pins – Non-shared lines (unlike most other PCI signal lines); each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter• Error reporting pins – Report parity and errors

OPTIONAL SIGNAL LINES

• Interrupt pins – Provided for PCI devices that must generate requests for service; also non-shared lines as each PCI device has its own interrupt line(s)• Cache support pins – Necessary to support

memory on PCI that can be cached; support snoopy cache protocols

OPTIONAL SIGNAL LINES

• 64-bit bus extension pins – 32 lines that are time multiplexed for addresses and data combined with mandatory address/data lines; Some lines used to interpret and validate signal lines carrying addresses and data; two lines that enable two PCI devices to agree to 64-bit capability• JTAG/boundary scan pins – Support testing

procedures defined by IEEE Standards

PCI COMMANDS

• Activity occurs in form of transaction• Initiator• Target

• Initiator determines next type of transaction• During the address phase of the transaction, the

C/BE lines are used to signal the transaction type

PCI COMMANDS

• Interrupt Acknowledge• Special Cycle• I/O Read• I/O Write• Memory Read• Memory Read Line• Memory Read Multiple• Memory Write• Memory Write and Invalidate• Configuration Read• Configuration Write• Dual Address Cycle

PCI COMMANDS

• Interrupt Acknowledge• Read command intended for the device that functions as

an interrupt controller

• Special Cycle• Used by initiator to broadcast a message to one or more

targets

• I/O Read Write Commands• Transfer data between the initiator and an I/O controller

PCI COMMANDS

• Memory Read Write Commands• Specify the transfer of a burst of data to and from

memory

• Configuration Commands• Allows initiator to read and update configuration

parameters for the connected device

• Dual Address Cycle• Indicates 64-bit addressing

TYPES OF PCI

Conventional PCI

PCI-X (Extended)

PCI-e (Express)

CONVENTIONAL PCI

Originally 32 bit data path 33 Mhz bus

frequency Throughput of

133MB/sec

After Improvements 64 bit data path Up to 533MHz bus

frequency Throughput of up to

532MB/sec

First Proposed by Intel in 1990

PCI-X

Designed to supersede PCI

Backward compatible with PCI cards and slots

Focus is on server technologies

Throughput of up to 8.5GB/sec

Widely being replaced by PCI Express

PCI EXPRESS

Different architectural structure

Uses a serial bus system as opposed to parallel

Five different types- PCIe x1, x4, x8, x16, x32

Replacing AGP video slots

PCI DATA

PCI SLOTS