Pawan Agarwal | Research Assistant

ARMAG, WSU.

Present: 1920 NE TERRE VIEW DR APT M312, Pullman, WA-99163, US Homepage

Ph: +1-509-263-8208 pawaniitm@gmail.com

EDUCATION

Program Institution Year of completion

Doctoral Student (EECS) Washington State University, Pullman, USA 2015 (expected)

B.tech in Electrical

Engineering with M.tech in

Microelectronics and VLSI

Design.

Indian Institute of Technology Madras,

Chennai, India

2009

PROFESSIONAL EXPERIENCE

Applied Micro, Pune, India – Senior Design Engineer (August’09-July’11)

• Applied Micro is a fabless semiconductor company designing network and embedded Power

Architecture, optical transport and storage solutions. All the projects described in this section has been

fabricated and silicon proven. The project details are as follows:

• “A Spread Spectrum Carrier Generator” (Septemeber’10 – May’11):

o A SSC generator with triangular modulation is being implemented in TSMC 40nm technology.

o It generates clock from 500MHz to 3GHz using a delta sigma modulator for fractional N divider

to realize the triangular modulation.

o My responsibilities included generating specifications for individual blocks, PLL top level

modeling, design of a Delta Sigma (MASH 1-1-1) based fractional divider (integer range from 1

to 2047), Charge pump, PFD, Regulator and integration of all the blocks.

• “A high speed integer N PLL” (August’09-August’10):

o An integer N PLL is being fabricated in TSMC 45nm technology. The output clock ranges from

2GHz to 6.8GHz.

o My contribution included designing the feedback divider (range from 10-512), a folded cascode

op-amp for the loop filter, dual loop based low drop out regulator, Charge pump, layout of

various blocks of PLL and integrating them.

ACADEMIC PROJECTS

• Ongoing Research Projects (under the guidance of Dr. Deuk Heo): (Dec’11-ongoing)

• Design of an ultra-low power and ultra-low jitter RF PLL. The project aims at devising innovative and

industry friendly methods to reduce the phase noise and the reference spurs of the PLL.

• Co-Designed a 60GHz injection locked LC VCO for RF transceiver’s frontend in TSMC 65nm.

• Design of a 60GHz LNA and PLL for beam-forming arrays.

• Dual Degree Project (under the guidance of Dr. Nagendra Krishnapura): (July’08-May’09)

• The project involved designing of a 16-bit current steering D/A converter for audio application with

a self-calibration scheme, novel flicker noise reduction technique and layout for the same in

UMC180nm technology.

• Achieved more than 80% reduction in power consumption as compared to the existing design.

• Designed a Deserializer for a high speed Delta-Sigma A/D converter

• This project was undertaken under the guidance of Dr. Nagendra Krishnapura.

• Convenient for measuring of very high speed output data without the need of a sophisticated

measurement device.

• An improved Fiduccia and Mattheyses (FM) Algorithm for circuit partitioning (March’08 - April ‘08)

• Proposed several improvements to the existing FM Algorithm and implemented the modified FM

Algorithm in C++.

• Achieved reduction in the simulation time by 16% as compared to the original algorithm.

• Designed the front end of a Digital Storage Oscilloscope – Self Study (January’08-June’08)

• Designed it for signal conditioning and capturing high frequency random signals with spikes (for more

than 1ns). Also did a preliminary design for signal processing and displayed it on LCD screen.

SUMMER INTERNSHIP(S)

• Applied Micro, Sunnyvale, CA – Student Internship (May’12-July’12)

• “A 32-to-2, 16Gbps Serializer” (May’12 – July’12):

o A 32 to 2, 16Gbps serializer was designed in TSMC 28nm CMOS technology. The schematic and

layout was completed. The post layout simulation results were satisfactory with significant

margin of error.

• “A 9-bit controlled 3GHz-to-8GHz Phase Interpolator for DLL” (May’12 – July’12):

o A wideband Phase Interpolator was designed for DLL using 9 control bits. The PI was designed

in both, TSMC 28nm and TSMC 40nm technology. The digital parts of the circuit were modeled

behaviorally using VerilogA. The layout and post layout simulations were completed.

• Bit Mapper Integration Technologies Limited, Pune - Summer Trainee (May’07-July’07)

• The project involved working on Aurora protocol to be used for high speed data transmission (10 Gbps)

using RocketIO (present in Xilinx Virtex-5 FPGA) and designing a PCB for the same.

• This was implemented for the first time in India.

• Bharti Teletech, Delhi - Summer Trainee (May’06- July’06)

• I worked on Microcontroller Programming and PCB designing for Fixed Cellular Terminal.

• Used in phone booth & Coin phones manufactured by Bharti Teletech.

COURSE AND LAB WORK

• Analog IC Design

• Analog Circuits

• VLSI Data Conversion Circuits

• Digital IC Design

• VLSI Broadband Communication Circuits

• VLSI Technology

• Analog and Digital Filters

• RF & Microwave circuits and systems

• System on Chip (SoC): design and test

• Advanced Wireless Integrated Circuits and

Systems

SKILLS

• Languages: C, C++ , VHDL , Verilog, VerilogA

• Software Tools: Cadence Virtuoso, Eldo, ModelSIm, XilinxISE Project Navigator, MATLAB, Scilab, Octave.

EXTRA CURRICULAR ACTIVITIES

• Chairman of Applied Micro (APM) cultural group and editor of APM’s In-house newsletter.

• Coordinated the event, Switch craft (Mixed Signal Circuit Design Event) at Shaastra’08-Annual Technical

Festival of IIT Madras. The event had over 300 participants from many colleges.

• Member of the Quality Management Team at Saarang’07 – Annual Cultural Festival of IIT Madras.