PATTERN GENERATION 0 binational digital circuits. …courses.cse.tamu.edu/walker/csce680/ATPGpaper.pdfis to automate it. To do this, we use an automatic test pattern generation, or

A /&T TUTORIAL

ALGORITHMS FOR

PATTERN GENERATION TOM KIRKLAND

Microelectronics and Computer Technology Corp.

M. RAY MERCER University of Texas

Three well-known algorithms for the automatic generation of test patterns for

digital circuits are the D algorithm, Podem, and Fan. This tutorial introduces

the concept of test generation and analyzes the way each algorithm uses

search and backtracking techniques to sensitize a fault and propagate it to an

observable point.

ne task that may be a perfect candidate for automation is test pattern generation for combinational digital circuits. Many engineers con- 0 sider this work more tedious and less

rewarding than other aspects of the design process, but they also recognize that it is essential to the quality of the final product.

Algorithms for automatic test generation focus primar- ily on ways to produce tests for combinational circuits.’ Tests for these circuits involve choices from many possi- bilities, so classical computer search methods are usually the basis for the algorithm. These search techniques use information in the network topology to specify the inputs that form the test pattern. The techniques have become more efficient over time as we have learned more ways to use this information.

Three of the best known algorithms for combinational ATPG are the D algorithm;* Podem, short for path- oriented decision making;3 and Fan.4 All three algorithms operate only on combinational circuits. Our analysis focuses on the search and control mechanisms of each algorithm. We also look at the heuristics used to guide ATPG search and the notation used to represent circuit values. Fujiwara5 and Bottorff‘ give alternative views of the same algorithms.

0740-7475/88/0600~43$100s~ 1988 43 June 1988

TPG TUTORIAL

GEMERATINC A TEST SET The obvious reason to test circuits is to sepa-

rate good ones from faulty ones. Consider the digital circuit in Figure la, which is also repre- sented by the graph in Figure lb. The graph nodes represent circuit devices, or gates, while graph edges represent circuit interconnections, or wires. The inputs to the circuit are called primary inputs. These are the only places we can apply test patterns. The outputs from the circuit are called primary outputs. These are the only places we can observe the effects of the tests.

Thus, test pattern generation is the task of finding a set of input patterns that will fully test the circuit. These patterns, called the test set, must cause all faulty circuits to exhibit different behavior from good circuits at the primary outputs. A failure is revealed when at least one primary output is different and a failure is present.

The test set must be reasonable-that is, we must be able to apply it economically to all circuits produced. Testing that uses all possible input patterns will, of course, reveal faulty circuits but will be too expensive for large circuits with many inputs.

For large circuits, the alternative to exhaustive testing is to start with some simplifying assump- tions about the possible failures. First, we assume that only stuck-at faults are failures. This type of fault manifests itself as a node in the circuit, which permanently assumes a value of 0 or 1. If the node’s value is 0, it is called a stuck-at-0 fault; if it is a 1, it is called a stuck-at-1.

Second, we assume that only one stuck-at fault is present in a faulty circuit. This single- stuck-at fault model might seem artificial on the

surface, but it has been quite useful in practice. The reason is that if we can detect a large percentage of the single stuck-at faults, we will usually get a test set that detects a correspond- ingly high percentage of all failures.’ We can also use stuck-at fault models that have been developed for a particular technology with good tracking between predicted and actual results.*

To amplify our previous definition of test pattern generation, then, it is the task of generating a test set that reveals all detectable single stuck- at faults. We say detectable faults because a circuit can have undetectable faults, also called redundant faults. The test set must consist of binary input patterns that will reveal a difference at the primary outputs.

To generate such a test set, we must produce a difference at the fault location. This process is called fault sensitizing. We must also propagate this difference to one or more primary outputs. This process is called fault propagation.

Consider the circuit in Figure 2a, which we will call a good circuit. If this circuit had a stuck-at-0 fault on the output of gate S, it would be modeled as shown in Figure 2b.

FAUL T SENSITIZING To sensitize the fault, we must find a pattern

that produces a value of 1 at the output of S for the good circuit. In the faulty circuit, the output of Swill be stuck-at-0 (s-a-0), which is different from the good circuit. To set S to 1 in the good circuit, we must set both L and M to 1. The fault is now sensitized, since the good circuit and the faulty circuit have different values at the fault location.

Figure 1 . A sample combinational circuit (a) and its circuit graph (b).

44 IEEE DESIGN & TEST OF COMPUTERS

FAULT PROPAGATION The next step is to propagate the difference

created by fault sensitizing to a primary output where we can observe it. Since Tis connected to a primary output, we must set the input from R to T to 0. To produce a 0 on the output of R, we must set one of its inputs to 0. Since L is already a 1. K must become 0.

PUTTING IT TOGETHER The output of T is now different in the good and

faulty circuits. We have propagated the fault to the output of T-a primary output-using K = 0, L= 1, and M = 1. If the circuit is good, output Z will have a value of 1, while if the s-a-0 fault is present at s, 2 will be 0. To recap, we got where we are now using the following procedure: 1. Sensitize the fault (set S to 1 in good circuit)

a. Set L to 1, and b. Set M to 1

2. Propagate the fault effect (through T) a. Set R to 0 b. Set K to 0

AN OVERVIEW Now that we have a procedure, the next step

is to automate it. To do this, we use an automatic test pattern generation, or ATPG, algorithm. The ATPG algorithm attempts to find a test for all the possible stuck-at faults in the fault set of interest. The attack on the problem can vary, from pseudo-random assignment of inputs to very complicated searching schemes. The algorithms we have chosen have the following basic sequence of operations in common: 1. Pick a fault that has not been detected. 2. Construct the search graph for the circuit with

the chosen fault. 3. Search the search space until either

a. a test is found, or b. the space is exhausted

If the algorithm terminates at 3a, the test is recorded along with the expected output and the target fault. If it terminates at 3b, then no test exists and the fault cannot be detected; that is, it is undetectable, or redundant.

These operations give a good overview of what an ATPG algorithm should do. In the next

M s-a-0

Primary@ input

Figure 2. A sample good circuit (a), afaulty circuit (b), and the search graph for locating the fault (c).

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ATPG TUTORIAL

section, we will go into much more detail, but before we do, we need to stop and clarify some “sound-alike” terms that we will be using in the explanation. Pairs of words such as circuit graph and search graph and backtracing and backtracking when used in proximity can cloud even the simplest examples. These similar sounding labels were not devised to deliberately confuse. In fact, they were not always in one discipline, but evolved separately within computer-aided design and artificial intelligence. Now these areas are merging, but it is too late to change the terms: all we can do is be aware of their differences.

The circuit graph and search graph are very different, for example. One is the graph of the circuit, while one is the graph of the search space. Figure 2c depicts the search graph for the faulty circuit in Figure 2b. The circuit graph never changes for a given circuit and is used to build the search graph.

The search graph, on the other hand, depends on both the target fault and the search procedure. It is always a tree and is usually built by going forward from the fault site to the primary outputs and going backward from inter- mediate goals to the primary inputs.

Backtracing and backtracking also differ. Backtracing is used to build the search graph, while backtracking is used to change a decision in the search graph. Backtracing is the process of working backward in the circuit graph to build the search graph, while backtracking is the process of correcting for some conflict between node values.

K

L

M

N

Figure 3. A circuit with reconvergent fanout.

THE ALGORITHMS As mentioned earlier, we have selected what

we consider a representative set of ATPG algorithms for discussion here: the D algorithm, Podem, and Fan. These algorithms differ in the size of the search space, the global search strategy, and the heuristics that can be used to help guide that search. The size of the search space is very important, since it determines an upper bound on the search time. The order of searching also greatly affects search time. Con- sequently, both the global search strategy used to build the search graph and the heuristics used to guide the search are just as important as the size of the search space.

No matter how good the heuristic is, however, if there is a redundant fault, the search algorithm will conduct an exhaustive search before it con- cludes that the fault is indeed redundant. In this case, the size of the search space becomes the dominant factor, rather than the order of the nodes in the search graph.

ATPG would be quite simple for combinational circuits if it were not for something called reconvergent fanout. A fanout point is the point at which a circuit node drives more than one other node. Node M in Figure 3 is an example of a fanout point, or fanout stem. Fanout stem M has two branches to gates T and S.

When successor nodes of the same signal come together at a subsequent node, such as node U in Figure 3, that node is called the point of reconvergence. Each reconvergent fanout introduces dependencies in the values that can be assigned to nodes. As we will see, it is this node dependency that causes conflicts in the ATPG process. If no reconvergent fanout is present, conflicts will not occur, and we will never have to backtrack.

THE D ALGORITHM The D algorithm was the first true algorithm for

ATPG.* We can use it to generate tests by com- bining what we know about the primitive ele- ments of the circuit with what we know about their interconnection network. The method that Roth proposed is based on the intersection of d- cubes, a notation for the difference calculus. Breuer and Friedman’ give a good background treatment of the testing aspects of the D algorithm in their text, while Roth offers a complete mathematical analysis in his original paper.

46 IEEE DESlGN & TEST OF COMPUTERS

For our discussion, we examine Roths algorithm as a search of a state space. We begin with the binary values 0 and 1 and add three new values. The first added value is X, which denotes an unassigned node value. To describe the difference between the good and faulty circuits, D and are introduced, denoting a difference and a difference bar, respectively. These five values are summarized as

0 - binary zero in both the good and faulty

1 - binary one in both the good and faulty

X - unassigned value (not one of the other

D- binary one in the good circuit, zero in the

D- binary zero in the good circuit, one in the

The search graph for the D algorithm contains all the nodes of the circuit graph arranged as a tree. For the circuit in Figure 3, this space con- sists of nodes K, L, M, N, R, s, T, U, and Z. The D algorithm searches this nine-node space for each fault considered. The search continues until a test is found or until the search space is exhausted. The order in which the algorithm assigns a value to a node depends on where in the search graph it is located. The value assigned depends on the desired goal. Since there is no global strategy for the order of search in the D algorithm, the order depends on the implementation.

Note that the search space for the D algorithm contains nodes that depend entirely on other nodes in the space. In Figure 3, for example, node T is determined completely by the values assinged to nodes K, L, and M. If, as the search progresses, these nodes have been assigned values, there may be a conflict that voids current assignments. Using this example, a conflict would be M = O and T=l. If the conflict is not detected and resolved at this point, a great deal of time may be spent on subsequent assignments to other nodes in an impossible quest.

These conflicts can be discovered by a process called implication. In implication, the effects of each assignment are carried backward and forward in the circuit through a process like simulation. If this process reveals that a node must take on inconsistent values (such as 0 and 1 simultaneously, or D and 0 simultaneously), then a conflict exists and must be resolved.

circuits.

circuits

four)

faulty circuit

faulty circuit

-

FAUL T SENSITIZING After the algorithm constructs the search

graph, either explicitly or implicitly, it initializes all the nodes to X. It then chooses a target fault and assigns a value of D to the fault site for a s-a-0 fault orDfor as-a-1 fault. For simplicity, suppose it assigns a value of D. The search then begins, and a value of 0, 1, D, or is assigned to some unassigned node. Some values are not tried, since they conflict with the value at the fault site or with another already assigned value.

After each assignment, the implications of that assignment are propagated forward and backward in the circuit. After implication, the algorithm checks to determine if a test has been generated. If so, it stops. If not, it continues the search until it has assigned all plausible values to every node in the search graph.

If the value at the fault site is preserved and the algorithm has found a nonconflicting set of

By carrying the effect of each assignment backward and forward in

the circuit, conflicts can be discovered and resolved.

assignments for nodes all the way to the primary inputs, then the fault has been sensitized. That is, the algorithm has justified the value at each node to the primary inputs-and hence the value at the fault site. Now the value at the fault site must be propagated to at least one primary output where we can observe the difference.

FAUL T PROPAGATION

The algorithm keeps a list of the gates that have a D or on one or more inputs and an X on the output. This collection of nodes is called the D frontier. The algorithm must choose one of the nodes in the D frontier and drive the fault effect to a primary output. As you may recall, this driv- ing process is called fault propagation.

Considering again the circuit in Figure 3, assume that the fault selected is a s-a-0 at the output of the AND gate T. Figure 4a shows the search graph for this fault. Here, we have chosen to sensitize the fault before propagating it.

June 1988 47

COMMON TERMS IN AUTOMATIC TEST PATTERN GENERATION

Backtrace: Moving a goal value backward in the circuit space from the output of a primitive element to one or more of its inputs until a primary input is reached. Backtrack: Retracing in the search graph to resolve a conflict by trying alternative assignments at previously assigned nodes. D frontier: The set of gates closest to primary outputs that have one or more D values on their inputs and an X value on their output. Fanout: Any circuit node that drives more than one primitive element. Fault: A failure in a circuit that causes its logical behavior to differ from that of the circuit without the failure. Most faults are assumed to be static; that is, they are present from the time they first occur until the circuit is repaired or replaced. Fault coverage: The number of faults expressed as a percentage of all faults that are detected by a set of test patterns. Fault propagation: Moving the effect of afault to a primary output by assigning values to the nodes in the search space. Fault sensitizing: Finding a set of primary input values that causes the fault site in the good circuit to have a value opposite to the faulty value (s-a-0 or s-a-1). Faulty circuit: A replicaof the original circuit with each fault site replaced by the particular fault model. The most common fault model is the single stuck-at fault. Free line: A circuit node that has no reconvergent fanout nodes among its predecessors. Good circuit: The original circuit with no faults present. Headline: A free line that drives a reconvergent fanout node. Also called the root of a tree of free lines in the circuit.

Implication: Determining the unique values implied by already assigned values. This process can cause both forward and backward assignment of values.

Justification: The process of finding a set of primary input values that cause a node to take on the desired value; essentially the same as backtrace with conflict resolution.

Primary inputs: The externally accessible input pins of a circuit through which we can inject logical values into the circuit.

Primary outputs: The externally accessible output pins of the circuit through which we can observe logical values from the circuit.

Reconvergent fanout: A fanout node, two or more of whose branches eventually are used as inputs to the same element. The element (one or more) at which the branches reconverge is called the point of reconvergence.

Redundant fault: A fault that because of redun- dancy in the circuit cannot be detected by any static test. Also known as an undetectable fault.

Sensitized path: A path that begins at the fault site and ends at a primary output. A change in the logical value of the fault site changes the logical value at the output.

Single-fault assumption: The assumption that one and only one fault is present in a given circuit at a time.

Stuck fault: A fault model in which the fault site has a permanent binary value (either 0 or 1). The value is assumed to be caused by the presence of afault.

Test: An input pattern that will cause one or more circuit outputs to differ, depending on whether a given fault is present or absent. A test may detect more than one fault, and a set of tests is required to detect all detectable faults.

All circuit nodes are initially set to X. A value of D is assigned to node T. T now has a 1 in the good circuit and a 0 in the faulty circuit. The next step is to justify this assignment. That is, we must make sure that the assignment results in no conflicts.

Since the faulty circuit is assumed to be stuck at 0, the assignment must first of all cause the good circuit to have a 1 at T. Both inputs of T must be 1, so M and R are assigned a 1. Since M is a

primary input, its value is already justified. To justify R to 1, K and L must also be 1. Once again, since these nodes are inputs, they are immediately justified. Thus, R is justified, and T is justified. At this point, the fault is sensitized with justified values and the goal becomes fault propagation.

If the D value is to propagate from T to a primary output, it must pass through AND gate U. For this to be successful, all the other inputs to

IEEE DESIGN & TEST O f COMPUTERS 48

the gate must be set to 1. The result is that S is assigned a value of 1. Since M is already assigned 1, the only way to produce the 1 on S is to set N to 0. Because N is a primary input, the 0 at N is immediately justified.

We have propagated the D to the output of U. We must now propagate it to Z. Fortunately, since Z is directly connected to U, we do not need to set any more nodes. We can observe the D at primary output Z, so we have found a test. The algorithm records the test, along with the expected good circuit output of 1 at Z and the target fault for which the test was generated.

BACKTRACKING The example just given is somewhat straight-

forward in that we found no conflicts. If we had encountered a conflict, we would have needed to backtrack, node by node, in the search space. Backtracking, as we said earlier, con- sists of reexamining each node’s assignment starting backwards from the location of the conflict. The algorithm checks to see if untried alternative assignments will remove the conflict. Backtracking continues until the conflict disap- pears or until the entire search space has been exhausted. If the space is exhausted, then the fault is redundant and no test exists.

To illustrate this process, we return to the fault propagation example (Figure 3). Suppose we try to propagate the D at T through U before justifying the inputs to T. Figure 4b shows this case. We begin by setting S to 1. If we justify this assignment by setting M to 0, then when we try to justify the D value at T, we will encounter a conflict. The already assigned value of 0 at M will conflict with the 1 value required to justify T=D.

To resolve this conflict, we would have to backtrack through the entire tree we used to sensitize the fault as well as the one we used to propagate it until we reach node M. At that time, we could choose N as an alternative way to set S to 1, as depicted by the dashed line in Figure 4b, and the search would proceed.

ANALYSIS The D algorithm is relatively blind to global cir-

cuit details. In our example, sensitizing the fault before propagating it worked best. For many circuits, however, it is better to propagate before sensitizing. We will always need to backtrack for some circuit with some target fault unless the circuit graph is a tree. Because very few circuits

June 1988

Figure 4. A D algorithm search graph without a conflict (a) and with a conflict (b).

49

ATPG TUTORIAL

...-.............. “.U,...- All nodes are set to X

except M ...... r

have this tree-like property, we must provide for backtracking.

In addition, because of node dependencies in the search graph, the D algorithm contains hidden conflicts that often cause it to continue beyond the conflict point before the conflict is detected. The example we looked at had only one path for propagating D from the fault site to a primary output. Many circuits have more than one such path. If more than one path exists, then the algorithm must try each path individually as well as all possible combinations of two paths, three paths, etc., up to the total number possible.

Implications

R=l, T=D

S = l , U=D, Z = D

Implications

T=O, S = l

I 1

1 R=l, T=D

I S = l , U = D Z = D

Figure 5. A Podem search graph without backtracking (a) and with backtracking (b).

The result is an explosion of algorithmic complexity. Armstrong, lo among others, has tried to reduce this complexity by using a single-path approach to fault propagation. This approach, called single-path sensitization, restricts the number of paths under consideration to each single path. This method can significantly reduce the search space, but it removes the algorithmic property. A test may exist but the procedure will fail to find it if more than one simul- taneous path is needed for propagation. ’’

To summarize, the D algorithm will find a test for a fault if a test exists, but it has several drawbacks: 1. It establishes no strategy for the order of fault

sensitization, justification, or fault propagation.

2. It contains hidden conflicts that are due to dependencies in the search space, which cause unnecessary work before detection.

3. It is algorithmically very complex because all combinations of paths must be examined.

The D algorithm has been improved, however. Kirkland’* has used guidance heuristics to address the search strategy problem, while Murakami et al.13 and Takamatsu and Kino~hita’~ have enhanced the notation from the original five values to nine values, to address the path complexity problem.

PODEM In 1981, Goel proposed another way of look-

ing at the search problem in ATPG. He called the algorithm Podem, short for path-oriented decision making.3 Goel noticed that the search graph used by the D algorithm includes every node in the circuit. For combinational circuits, however, we really need to consider only nodes that are primary inputs. All other nodes are a function of some set of the primary input nodes. Thus, when we choose inputs as nodes in the search space, we will have no hidden conflicts and each node can be assigned independently.

Further, suppose that we already have a set of primary input assignments and another primary input has been assigned a value that causes a conflict. We would have to try only one other value at that input (the complement of the current value) to determine if the current assignment will ever be compatible with the goal. If the complementary value also conflicts, then the goal cannot be achieved with the existing input

IEEE DESIGN & TEST OF COMPUTERS 50

assignments, and we will need to backtrack further. Since we do not have to try any assignments below this point, we can prune a large portion of the search graph and never search it when such conflicts arise. The savings in computer time is enhanced because the total search space is smaller than that of the D algorithm.

To illustrate this process, we again consider the circuit example used to explain fault propagation and backtracking (Figure 3). Our goal is again to find a test for s-a-0 at T. Podem first tries to identify a value to be assigned to an input. It does this by backtracing from T. (Recall that backtracing is the process of working backward in the circuit graph to build the search graph.) The path chosen depends on the heuristics chosen to guide backtracing.

For discussion, we assume that the algorithm first assigns a 1 to input M, although the order is really arbitrary. It must then determine the effect of this assignment, so implication is done using traditional simulation, not just a simulation-like process as in the D algorithm. If the simulation does not reveal any conflicts with the goal- which is to set T to l-then the algorithm chooses a new input and assigns a value to it. This process proceeds until either a test is found, a conflict occurs, or there is no path that can be used to propagate the fault. The algorithm may find a test accidentally (without explicit propagation) when the simulation reveals a D or D value on a primary output.

Podem continues to look for X paths to propagate the fault from the current D frontier (the D values closest to primary outputs) to the primary outputs. It backtracks when it discovers that no such path exists.

-

To illustrate, we assume that the search graph is ordered as shown in Figure 5a. After the algorithm assigns a 1 to input M, no internal circuit nodes have a value other than X. Similarly, when K is assigned a 1, simulation reveals no implications. When L is assigned a 1, however, node R becomes a 1, and T becomes a D (since it is assumed to be s-a-0 in the faulty circuit). Finally, when N is assigned a 0, these implications remain plus S goes to 1, U to D, and Z to D. Since Z is a primary output with a value of D, the fault has been propagated and a test has been found.

But what if one of the assignments had produced a conflict? Assume that we had first tried to assign a 0 to M to produce the needed 1 at S. This case is illustrated in Figure 5b. The implication of assigning a 0 to M is that T has a value of 0 in the good circuit. This value conflicts with our goal of having a D value for T, since to have a D there, we must have a 1 in the good circuit.

When Podem discovers this conflict, it checks the value assigned to M to determine if it is the first or second value assigned to this input. If it is the first value, then it is complemented and the search continues. For example, in this case, M is changed to a 1, and the process continues as in the original example. The only difference is that Podem has assigned M its second value and cannot complement it again.

As we have seen, this new assignment eventually succeeds, since we can make further

If no test exists when an input is at 0 and when it is at 1, then no test exists for the input assignment.

assignments to primary inputs that will produce a test. But what would have happened if the complemented value of M had also conflicted? The answer becomes obvious if we consider the question more deeply. If no test can be found with a particular input at 0, and no test can be found with the same input at 1, then no test exists for the current input assignment.

Consider the circuit in Figure 6a with the fault s-a-0 at S. Figure 6b shows the resulting search graph. Assume that Podem begins by assigning a 1 to node K. The implication of this assignment is that S becomes O-a conflict with our goal of setting S to 1. Podem must therefore backtrack to try assigning a 0 to K. This assignment also conflicts, which tells us that no test exists for the target fault because it is a redundant fault.

Now, suppose Podem had already assigned values to other inputs before it detected this conflict. The implication of the conflict is that there is no test for the current assignment, so Podem must backtrack until it finds a nonconflicting assignment. If it backtracks until the search

June 1988 51

Z L >

Implications

s=o

All nodes are set to X

s=o

Figure 6. Circuit with a redundant fault (a) and a Podem search graph for that fault (b).

Implications

T= D

S=l U = D Z=D

-I

Figure 7. A Fan search graph.

graph is empty without finding a test, then once again, none exists and the fault is redundant.

Podem will eventually try all the primary input combinations, either explicitly or implicitly, until it finds a test. It will explicitly try all the combinations actually assigned, and implicitly try those rejected because of the double conflicts. Those not tried are effectively pruned from the search space and need never be tried (dotted lines in Figure 6b). It is this pruning of the search graph through implicit assignment that gives Podem its designation as an implicit enumeration technique. For this reason, Podem is usually more efficient than the D algorithm, especially for circuits with a large number of Exclusive-OR gates, such as parity trees and error-correcting circuits.

THE FAN ALGORITHM In late 1983, two Japanese researchers pub-

lished an algorithm similar to Podem, which they called Fan.4 The algorithm was so named because it tries to reduce the number of backtracks in the search graph by considering fanout branches as a special case. Fan searches a space made up of two types of nodes, fanout stems and headlines. Fanout stems, as we said earlier, are simply the fanout points. Headlines are a bit more complex, involving another concept called free lines. Free lines are gate outputs whose predecessors are not in any fanout loop. A headline is a free line that drives a gate that is part of a reconvergent fanout loop.

In Figure 3, for example, nodes K, L, R, M, and N are free lines, but only R, M, and N are headlines, since K and L are predecessors of R. Another way to describe a headline is to call it the root of a tree that forms a subgraph of the circuit. The leaves of the tree are the primary inputs.

Fanout stems must be assigned values that are consistent with all unblocked paths from the fanout to the point of reconvergence. Headlines, on the other hand, can be assigned values arbitrarily, since they are independent of all nodes already assigned. Thus, when backtracing reaches a headline, it stops, since the headline can be assigned an arbitrary value. That is, the algorithm does not have to complete the backtrace to a primary input.

This principle is one of the reasons that Fan’s performance is better than Podem’s. Figure 7 shows how Fan handles the generation of a test for s-a-0 at T. Figure 5a shows how Podem han-


dles the same case. Comparing the two, we find that Fan begins in the same way as Podem, setting M to 1. When Fan reaches R = 1, however, it can stop backtracing because it knows that R can later be justified without conflict. Instead, Fan goes on to set N = 0, resulting in the state depicted in Figure 7. At this point, Fan knows that a test is possible-all that must be done is to fin- ish justifying the headline values. It does this in the same manner as Podem, choosing a particular headline value as a goal, backtracing to primary inputs and simulating the results until the goal is achieved. As soon as it justifies all the headlines, it determines the final input values for the test.

Higher performance is not the only charac- teristic of Fan that sets it apart from the other algorithms, however. It uses a technique called multiple backtrace to reduce the number of backtracks in the search graph for most circuits. In most cases, the amount of work done at each backtrace in the circuit graph is less than with other algorithms.

To illustrate, we look at the test generation for the s-a-0 at U fault in Figure 3. Podem sets a goal of U = 1 and begins backtracing along one of the paths to the primary inputs. Suppose that it decides to try the path U- S- M. It sets S = 1 and M=O. After simulation, the circuit looks like the one shown in Figure 8. Since this assignment obviously cannot satisfy the goal, Podem com- plements the value of M to give the values shown in Figure 9. Now the goal can be achieved and the process proceeds as described earlier.

Suppose, however, that the reconvergent fanout is buried deep in a circuit, as shown in Fig- ure IO. As Podem backtraces from Y to U, it assumes a value at U and pushes on to R, etc. Only when it reaches a primary input is simulation done, and only then will any conflicts with the goal be found.

Fan solves this problem by causing each fanout to be explicitly enumerated when it is originally assigned. For the circuit in Figure 10, Fan stops the backtrace when it reaches U along one path and goes back to the goal to trace another path. Only when it has traced all paths from the point of reconvergence to the fanout stem will it assign a value to U. It then simu- lates this value to determine if any conflicts are present. If so, the value on U can be changed to resolve the conflict.

L -

X K

L X

0 M

Z N

Figure 8. Circuit state when M = O .

Figure 9. Circuit state when M =1.

Figure 10. Embedded reconvergent fanout.

53 June 1988

ATPG TUTORIAL

In multiple backtracing, the backtrace does not proceed along a single path to inputs, but along multiple paths to fanout points. As Fan proceeds, it collects and then resolves the fanout assignments, postponing the resolution of the headline assignment.

GUIDANCE HEURISTICS How to select the best path during backtrac-

ing is one of the most critical problems in ATPG. Regardless of the search space used, if the paths we choose result in conflicts, we will have to waste computation time resolving them. The most straightforward path is not always the best choice either. Suppose all the inputs to a gate must be set to a particular value to achieve the goal, for example. We are better off trying to set the hardest input to a 1 first, rather than the easi- est. Since the hardest is most likely to fail, the failure is likely to occur sooner, and there is less time spent finding the failure. Conversely, if the hardest succeeds, then the others are very likely to succeed also.

Breuer and associate^'^ published one of the first proposals for ATPG guidance, in which they used a rough cost measure derived from the level of the gate and the number of its inputs. Later, Goldstein" introduced a technique called SCOAP (short for Sandia Controllability/Observ- ability Program) to calculate the testability of a circuit. As we said earlier, Podem uses a reduced form of SCOAP as its guidance mechanism. Modified versions of SCOAP have also been used in other test generation system~.'*, '~. A measure similar to SCOAP, called Camelot, has also been proposed as a heuristic guidance for ATPG.'*

PERFORMANCE It is difficult to compare the performance

of the D algorithm, Podem, and Fan in any depth, since most of the literature provided by the authors of the algorithms contains insufficient detail. Moreover, the algorithms were written in different languages, executed on different machines, and used only for a small set of circuits and implementations. However, although the results cannot be used to accurately predict relative performance in an actual ATPG environment, they are worth reviewing.

The largest Podem application reported by its author involves a system that also uses a biased

Table 1 . Characteristics of ATPG algorithms.

Alaorithm D Podem Fan

Space All nodes All PIS All headlines Order of Depends on 1 PI at a time Fanouts,

assignment implementation (most likely) then headlines

Heuristic None Controllability Podem plus used and level fanout weiaht

random pattern generator. '' Podem is used in the system to improve fault coverage beyond what the random technique could obtain alone. Approximately 50,000 gates were tested, requiring 1372 minutes of IBM System 370/168 time. The result was 89% fault coverage of approximately 90,000 faults.

The largest reported Fan application reported by its author combined the algorithm and nine- value notation.20 This example involved approximately 20,000 gates and required 291 minutes of NEC System-1000 time. The result was 95% fault coverage of approximately 33,000 faults.

'he characteristics of the three algorithms are compared in Table 1. As this table shows, the trend in ATPG algorithms is toward smaller, node-

independent search spaces, with more atten- tion paid to the problem of reconvergent fanout and improved heuristics for guiding the search process.

These algorithms do not constitute a complete test system. All of them must be combined with an efficient fault-grading mechanism and used in conjunction with a design philosophy that allows the sequential testing problem to be separated into a set of independent combinational testing problems. However, we can use these algorithms in such an environment to auto- matically produce good test sets for quite large circuits. Since we still have a great deal of room for improvement, we can look forward to better and more efficient algorithms for ATPG in the future. It remains to be seen, however, whether such improvements will be able to keep pace with the rapidly expanding size and complexity of VLSl circuits.


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M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Computer Science Press, New York, 1976. D.B. Armstrong, “On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets,” /€€E Trans. Nectronic Computers, Feb. 1966, pp. 66-73.

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Tom Kirkland is a senior member of the technical staff at MCC’s Test Technology Laboratory, where his research interests are automatic test pattern generation, functional testing, and testability analysis and planning.

Previously, Kirkland worked for GE/Calma as director of CAE research and for CSC in testability analysis. He was also a patent attorney with the Comsat legal department. He holds a BSEE, an MSE, a JD, an MBA, and a PhD in electrical engineering-all from the University of Texas at Austin. He is a member of the Computer Society, ACM, Eta Kappa Nu, and Phi Kappa Phi.

Questions about this article can be directed to M.R. Mercer, University of Texas, Dept. of Electrical and Computer Engineering, Austin, TX 78712.

M. Ray Mercer is an associate professor of electrical and computer engineering at the University of Texas at Austin, where he holds the Werner W. Dornberger Centennial Teach- ing Fellowship in Engineering. His research interests are design for testability, ATPG, fault-tolerant computing, and CAD of VLSl devices.

Previously, Mercer worked for AT&T Bell Laboratories, Mur- ray Hill, and for Hewlett-Packard, Palo Alto. He holds a BSEE from Texas Tech University, an MSEE from Stanford Univer- sity, and a PhD in electrical engineering from the University of Texas. He was a National Science Foundation Presiden- tial Young Investigator in 1986, and is now D&T’s design for testability editor and a member of the International Test Con- ference Program Committee. He holds two patents in design for testability.

June 1988 55

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PATTERN GENERATION 0 binational digital circuits. …courses.cse.tamu.edu/walker/csce680/ATPGpaper.pdfis to automate it. To do this, we use an automatic test pattern generation, or