Deterministic Diagnostic Pattern Generation (DDPG) for

Compound Defects Fei Wang1,2, Yu Hu1, Huawei Li1, Xiaowei Li1, Jing Ye1,2

1Key Laboratory of Computer System and ArchitectureInstitute of Computing Technology

Chinese Academy of Sciences2Graduate University of Chinese Academy of Sciences

Yu Huang3

3Mentor Graphics Corporation

International Test ConferenceSanta Clara, CA, Oct 26-Oct 31, 2008

Purpose

• Object– Faulty circuit contains compound defects

• Problem– How to diagnose scan chains when existing compound

defects?– How to guarantee diagnostic accuracy, resolution and

efficiency?

• Method– Deterministically generate diagnostic patterns under

certain constraints– Statistically failure analysis to locate the faulty scan cell

scan chain defects and system logic defects

co-exist on the chip

Outline

• Background– Motivation– Related work– Our contributions

• Proposed method– DDPG algorithm– Compound defect diagnosis process

• Experimental results

Motivation

• Why compound defect diagnosis– Both scan chains and system logic occupy

significant area• Scan chains associated area: 30% [Kundu VTS’93]• Scan chain failures: 50% [Yang ICCD’05]

– Assume system logic is fault-free will lead to misdiagnosis

Related Work

Scan chain diagnosis

Hardware based solutions Software based solutions

Partnerscan chain

Partnerscan chain

Insert XOR gates

Insert XOR gates

[Schafer VTS’92]

[Narayanan ITC’97]

Customscan cell

Customscan cell

[Edirisooriya VTS’95]

Simulation based

Simulation based DDPGDDPG

[Huang ITC’07]

[Tzeng TCAS’07]

Production test patterns

Production test patterns

Functionalpatterns

Functionalpatterns

[Guo ITC’07]

[Li TVLSI’05]

Capturestate

Capturestate

Propagatestate

Propagatestate

Related Work

Scan chain diagnosis

Hardware based solutions

Partnerscan chain

Partnerscan chain

Software based solutions

Customscan cell

Customscan cell

Simulation based

Simulation based DDPGDDPG

High area and routing overhead Unconventional DFT flow

Unguaranteed resolution Unguaranteed accuracy

Impractical assumption: system logic is fault free！

Insert XOR gates

Insert XOR gates

Our Contributions

• Features – First DDPG for compound defects– Effectively diagnose scan chains with dozens of system

defects• Approach

– Propagate the state of the targeted scan cell to multiple observation points

– Statistical failure analysis to locate the faulty scan cell• Key results

– Accurately diagnose faulty cell with dozens of system defects

– Tolerate system logic faults without degradation of chain diagnostic resolution

Outline

• Background– Motivation– Related work– Our contributions

• Proposed method– DDPG algorithm– Compound defect diagnosis process

• Experimental results

7

Fault Model

6 5 4 3 2

SIDownstream

Upstream

SO

Fault Model Expected Unloading Actual Unloading

SA1 00001111 11111111

SA0 11110000 00000000

STR 11110000 11100000

STF 00001111 00011111

FTR 11110000 11111000

FTF 00001111 00000111

1 0

Basic Idea of DDPG

21

20

19

18

16

15

14

13

8

7

5

4

3

0

SI

SO

G1

G4

G2

21

20

19

18

16

15

14

13

8

7

5

4

3

0

SI

SO

G3

G5

g

ea

b

c

f

O3O3

PI1=0

PI2=1

i

xx

0/0x

1/00/0

x

xx

0/0

1/11/0x

x

1/01/1

x

xx

x

1/0

x

x1/0

x

x

1/1

1/1

0x

xx

xx

x

0x

x

x1x

x

Targeted cell

Vulnerable-PPIProtection-PPI

Trigger-PPI

Vulnerable-PPO

Protection-PPO

Actual

STR

System defect

DDPG Algorithm OverviewSelect celli from Suspect_Cell_Set, build Output_Seti

Generate a pattern to propagate celli state to n reliable observation points (ROP) within Output_Seti

Success?

Output_Seti ∈ Ø?

Suspect_Cell_Set ∈Ø?

Save the pattern, delete the n ROPs from Output_Seti

Y

Delete the targeted celli from Suspect_Cell_Set

Y

N

N

EndY

N

n>1 ?

n=n-1

NY

DDPG Constraints-Loaded Value

• Constraints on loaded values

– Not constrain all scan cells on the faulty chain• only constrain the cells that sensitize fault propagation paths

– The constrained scan cells can be anywhere on the faulty scan chain

• Guarantee the patterns can be loaded correctly

– The targeted scan cell can be sensitized and its state can be propagated to ROPs

DDPG Constraints-Captured Value

• Constraints on captured values

– The state of ROPs can be safely unloaded– For stuck-at faults, ROPs could be

• downstream cells of LB in the faulty scan chain• good scan chains• POs

– For timing faults, ROPs could be• all cells except the targeted cell in the faulty scan chain• good scan chains• POs

11110100

DDPG Constraints-Sensitization

• Sensitize Fault Propagation Path– off-path inputs of all the gates on propagation

path are constrained to non-controlling values– Specify the minimum number of ROPs (n≥2)

Pick 3 observation points

Pick at least one observations points

SA0

j

SA0

j j

SA0

Pick 2 from 3

Apply Constraints to Netlist

16

15

14

5

4

G4G2 8

7

4

3

G5

b

c

f

PI1

i

h

P1

P1P2

P2

SI SI

SA0

j(b, f, h)

(b, f, i)

Constraint Circuit

Sensitized path number ≥ 2 ？

STR

Compound Defect Diagnosis Process

Calculate a weight w(patCi,j) for each pattern patCi,jw(patCi,j)= # of ROPsCi,j / # of total ROPs

Calculate a load error probability LEP(Ci,j)for each scan cell Ci

LEP(Ci,j)=HCi,j / # of ROPsCi,j

Calculate the suspect score

, ,1

( ) ( ) ( )n

i Ci j i jj

WLEP C w pat LEP C

1

1 , 0,1, 2, ,2 2 1

i r

cc i r

i

WLEP Ce abs i L

r

patC16,1

patC16,2

patC16,3C0

C4

C16

C21 C8

O3

patC16,1=3/10

patC16,2=4/10

patC16,3=3/10

LEP(C16,1)=1/3

LEP(C16,2)=4/4

LEP(C16,3)=2/3

WLEP(C16)=7/10

Outline

• Background– Motivation– Related work– Our contributions

• Proposed method– DDPG algorithm– Compound defect diagnosis process

• Experimental results

Experimental Setup

• Five ISCAS’89 benchmark circuits• Key parameters

– Each circuit has two scan chains– n=2, max(|Output_Seti|)=20

• Experimental stepsFor (cell=0;cell<L; cell++) {

Inject a timing fault to cellRun DDPG and simulation, calculate Hit_RateWhile (! misdiagnosis) { Randomly inject a SA1/SA0 fault to system logic Run DDPG and simulation, calculate Hit_Rate }

}

# _

# of hit chain diagnosis

Hit Rateof total cases

Experimental Results

CUT SA0 SA1 FTF FTR STF STR

Hit_Rate A B A B A B A B A B A B

s9234 1 1 1 1 1 1 1 1 1 1 1 1

s13207 1 1 1 1 1 1 1 1 1 1 1 1

s15850 1 0.997 1 0.993 1 1 1 1 1 1 1 1

s38417 1 1 1 1 1 1 1 1 1 1 1 1

s38584 1 1 1 1 1 1 1 1 1 1 1 1

Table 1. Hit_Rate of the proposed DDPG method

A: system logic is fault-free

B: one SA fault in system logic

Robustness Evaluation: s38584

(a) No system logic faults (b) 20 system logic faults

(c) 40 system logic faults (d) 68 system logic faults

Robustness Evaluation: All CUTs

CUT# of SA0

faults# of SA1

faults# of FTF

faults# of FTR

faults# of STF

faults# of STR

faults

s9234 9 13 17 24 27 16

s13207 13 86 26 14 17 24

s15850 20 60 17 23 33 30

s38417 58 17 19 17 26 9

s38584 23 61 41 84 55 68

Table 2. The number of faults injected into CUT when misdiagnosis happens

Diagnostic Resolutions

CUT Method SA0 SA1 FTF FTR STF STR

s9234DDPG 2.21/6 1.75/5 1.19/2 1.16/3 1.22/3 1.21/4

Li 05 15.4/33 5.7/14 5.5/13 4.8/14 3.3/8 6.9/19

s15850DDPG 2.23/6 2.30/8 1.04/2 1.03/2 1.02/2 1.07/2

Li 05 2.7/7 2.1/7 2.7/7 2.1/7 2.0/7 2.1/7

s38584DDPG 2.93/10 1.73/8 1.02/3 1.03/2 1.02/3 1.03/2

Li 05 4.1/12 4.6/15 3.6/12 5.6/13 3.8/12 3.4/10

Table 3. Diagnostic resolution (Average/Worst)

DDPG Time

CUT SA0 SA1 FTF FTR STF STRAvg

.

s9234 4.48 1.09 0.44 0.44 0.49 0.15 1.18

s13207 1.85 1.01 0.07 0.41 0.44 0.43 0.70

s15850 3.15 1.04 1.19 0.66 1.15 0.39 1.26

s38417 3.83 4.93 0.83 0.86 0.69 1.60 2.12

s38584 14.47 2.43 0.32 0.35 0.47 0.47 3.08

Table 4. Average pattern generation time (second) for a scan cell

Conclusions

• First DDPG for compound defects

• Statistical failure analysis for compound defects

• Tolerate dozens of faults in system logic without degradation of chain diagnostic resolution

Thank you!

Questions?