Rev. 0.2 5/10 Copyright © 2010 by Silicon Laboratories AN409

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OUTPUT TERMINATION OPTIONS FOR THE

Si500S AND Si500D SILICON OSCILLATORS

1. IntroductionThe Si500D Silicon Oscillator can be ordered with one of five different output buffer types: CMOS, SSTL, LVPECL,LVDS, or HCSL. Each output type has its own particular benefits and limitations. This document describes eachbuffer type, proper biasing and termination schemes, and related technical trade-offs.

2. CMOSComplementary metal-oxide semiconductor (CMOS) totem pole output buffers are used to drive capacitive loads toCMOS logic levels. The Si500 CMOS driver output impedance is a nominal 36 . An external series resistor canbe added to provide optimum impedance matching with higher impedance traces as shown in Figure 1.

Unlike most CMOS output drivers, the Si500 provides two outputs which can be ordered as complementary or in-phase. When in-phase, the two outputs may be shorted together to produce a single nominal 18 driver to drivelarge capacitive loads. The CMOS option can be ordered for all three of the supported supply levels (1.8, 2.5, and3.3 V).

Figure 1. Example of External Source Termination Resistorsto Improve Trace Impedance Matching

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3. SSTL

SSTL (Stub Series Terminated Logic) is an electrical interface commonly used with DDR (Double Data Rate)DRAM memory ICs and memory modules. The Si500 support 3.3, 2.5, and 1.8 V SSTL outputs which can besingle-ended, differential, or in-phase. The termination scheme for SSTL is shown in Figure 2.

Figure 2. SSTL Termination Schemes

50

VTT

50

VTT

VDD

0.1 uF

VTT

2 k

2 k

0.50*VDD

VDD

0.1 uF

VTT

2.43 k

2 k

0.45*VDD

Practical VTT for SSTL-3Practical VTT for SSTL-2, SSTL-18

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4. LVPECL

Low-voltage positive emitter-coupled logic (LVPECL) differential outputs are typically chosen for their superior jitterperformance. The Si500 devices offer two LVPECL options: a standard LVPECL option and a low-power LVPECLoutput option for ac coupling only. LVPECL is offered with both 3.3 V and 2.5 V supplies.

The standard LVPECL output option requires external biasing and proper termination of 50 to VDD-2 V for eachside of the differential output. Many well-known LVPECL biasing and termination schemes are supported by theSi500 devices. The most common are shown in Figures 3, 4, and 5. The primary disadvantages of this outputformat are increased power consumption (due to dc biasing) and incompatibility with 1.8 V supplies. The primaryadvantage of the LVPECL signal format is jitter performance. LVPECL provides the best jitter performancebecause of its large swing and fast edge rates.

Figure 3. Traditional Biasing and Termination for Standard LVPECL Output Option

Figure 4. Alternative Biasing and Termination for Standard LVPECL Output Option

50 50

VDD-2V

50

50

R2R2

R1 R1 R1 = 130 , R2 = 82 3.3V LVPECL

R1 = 250 , R2 = 62.5 2.5V LVPECL

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Figure 5. Alternative Biasing and Termination for Standard LVPECL Output Option(100 Line Termination May Be Internal to the Receiving IC)

The low-power LVPECL option eliminates the need for external dc biasing, which reduces overall powerconsumption without sacrificing jitter performance.

Figure 6. Termination for Low-Power LVPECL Option(100 Line Termination May be Internal to the Receiving IC)

130 130

100 0.1 µF

100 0.1 µF

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5. LVDS

Low-voltage differential signaling (LVDS) differential outputs are typically chosen for their ease of use. LVDS is acommon input and output type used with FPGAs. LVDS outputs require no external biasing or termination whenconnected to LVDS inputs and are very power-efficient. Also, the LVDS specification allows for significant dcbiasing drift from transmitter to receiver, further simplifying system-level design. LVDS outputs are connected asshown in Figure 7.

Figure 7. Typical Transmission Line Connection for LVDS (100 Line Termination May Be Internal to the Receiving IC)

6. HCSL

High-Speed Current Steering Logic (HCSL) outputs are commonly used for PCI Express applications. The Si500Dintegrates the 50 termination resistors to ground, simplifying the connection to an HCSL receiver.

Figure 8. HCSL Connection Using Internal Termination Resistors

100

Internal To HCSL Output Driver

50 50

50

50

DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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