Other Books by R. M. Marstonnvhrbiblio.nl/biblio/boek/Marston - 110 Semiconductor...Other Books by R. M. Marston 20 Solid State Projects for the Car and Garage 110 COSMOS Digital IC

Other Books by R. M. Marston

2 0 Solid State Projects for the Car and Garage 110 COSMOS Digital IC Projects for the Home Cons t ruc to r 110 Electronic Alarm Projects for the H o m e Cons t ruc tor 110 Integrated Circuit Projects for the H o m e Cons t ruc tor 110 Opera t ional Amplifier Projects for the Home Cons t ruc to r 110 Thyr is tor Projects using SCRs and Triacs 110 Waveform Genera tor Projects for the Home Cons t ruc tor

110 Semiconductor Projects for the Home Constructor

R. M. MARSTON

The Butterworth Group

United Kingdom Butterworth & Co (Publishers) Ltd London: 88 Kingsway, WC2B 6AB

Australia Butterworths Pry Ltd Sydney: 586 Pacific Highway, Chatswood, NSW 2067 Also at Melbourne, Brisbane, Adelaide and Perth

Canada Butterworth & Co (Canada) Ltd Toronto: 2265 Midland Avenue, Scarborough,

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77-85 Customhouse Quay, 1, CPO Box 472

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USA Butterworth (Publishers) Inc Boston: 10 Tower Office Park, Woburn, Mass. 01801

First published 1969 by Iliffe Books Reprinted 1971,1973,1976

Second Edition 1978 by Newnes Technical Books, a Butterworth imprint

Reprinted 1980

© R. M. Marston, 1978

All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, including photocopying and recording, without the written permission of the copyright holder, application for which should be addressed to the Publishers. Such written permission must also be obtained before any part of this publication is stored in a retrieval system of any nature.

This book is sold subject to the Standard Conditions of Sale of Net Books and may not be re-sold in the UK below the net price given by the Publishers in their current price list.

ISBN 0 408 00322 7

Typeset by Butterworth Litho Preparation Department

Printed in England by McCorquodale Newton Ltd, Newton-Le-Willows, Lanes.

PREFACE

Semiconduc to r technology has advanced so rapidly in the past decade t h a t m a n y amateurs , technic ians , and engineers have found great difficulty in keeping t r ack of the new devices t h a t have become available. Consequen t ly , m a n y outs tandingly useful devices, like t he field-effect t ransis tor , the uni junct ion t ransis tor , the silicon contro l led-rectifier, and the in tegra ted circuit , have remained unused by m a n y amateurs and professionals.

This Hisage gap ' is due mainly t o the lack of readable in format ion on the m a n y devices. Most b o o k s and articles t h a t deal w i th t h e m get bogged d o w n in a morass of useless t heo ry and incomprehens ib le ma thema t i c s . This present volume manages t o overcome this p rob lem. I t sets ou t t o in t roduce the reader t o devices b y expe r imen t , ra ther t h a n t h e o r y . Each chap te r starts b y out l ining the basic characterist ics of a device, ra ther t h a n its in t r icate t h e o r y , and then goes o n t o give a range of practical circuits in which it is used . 110 different circuits are described, and t h e opera t ion of each one is explained in simple and concise t e rms .

T h e volume is i n t ended t o appeal equally t o the amateur and p ro -fessional electronics m a n . The explanat ions of device opera t ion are m e a n t t o be readable b y the ama teu r wi th n o mathemat ica l knowledge , while at t he same t ime conveying informat ion of value t o the technician and engineer. The practical circuits should be of interest t o all readers . Those of part icular in teres t t o t he amateur include simple amplifiers, l amp and relay driving circui ts , e lectronic switches t ha t can be opera ted by l ight , b y s o u n d , or b y con tac t wi th wate r , and electronic t imer and delay circuits giving per iods ranging from a fraction of a second t o 35 m i n .

Circuits of par t icular in teres t t o t he technician and engineer include amplifiers wi th i npu t impedances as high as 500 M£2, voltage and cur ren t regulators , a cons tant -volume amplifier, pulse and o the r wave-form genera tors , analogue-to-digital conver ters , logic circui ts , f requency dividers, a d .c . choppe r , and simple power control ler circuits . All circuits are designed a round internat ional ly available semiconduc tors , so t he par t s needed in all cons t ruc t ion projects should be readily obta inable in all par ts of the wor ld .

R. M. Marston

C H A P T E R 1

30 SILICON-PLANAR TRANSISTOR PROJECTS

Recen t years have seen m a n y advances in semiconduc tor p ro d u c t i o n techniques . Amongs t the mos t i m p o r t a n t of these have been the i n t roduc t ion of simplified m e t h o d s of manufac tur ing silicon-planar mul t i - junct ion ne tworks , and the widespread adop t ion of e p o x y or plastic encapsula t ion techniques . The combina t ion of these techniques has resul ted in a new generat ion of low-cost h igh-performance transis tors , having m a n y advantages over the earlier ge rman ium types . These n e w transis tors have very low leakage cur ren ts , are capable of opera t ing a t high t empera tu res , a n d can wi ths tand considerable physical and electrical abuse w i t h o u t breaking d o w n .

With these advantages in m i n d , le t ' s take a l ook at the characterisi tcs of ju s t t w o low-cost general-purpose silicon-planar t ransis tors , a n d t h e n go o n t o consider th i r ty or so useful l i t t le circuits in which they can be used.

The t w o transis tors t ha t we'l l select for this purpose are the 2 N 2 9 2 6 n p n t y p e by G.E.C. , a n d the 2 N 3 7 0 2 p n p t y p e by Texas . Their general characterist ics and lead connec t ions are shown in Fig. 1.1 a n d Table 1.1. N o t e tha t the 2 N 2 9 2 6 t y p e is colour c o d e d according t o gain; we'l l use the medium-gain 'o range ' t ype in m o s t appl ica t ions .

Using silicon-planar transistors

The m o s t str iking differences be tween silicon and ge rmanium, a n d p n p a n d n p n transis tors are shown in Fig. 1.2. A l though n o com-p o n e n t values are shown he re , typical circuit po ten t ia l s are inc luded,

2 30 SILICON-PLANAR TRANSISTOR PROJECTS

Table 1.1 G E N E R A L C H A R A C T E R I S T I C S O F T H E

2 N 2 9 2 6 A N D 2 N 3 7 0 2 T R A N S I S T O R S

2N2926 2N3702

Transistor Type npn pnp Ic (max) 100 mA 200 mA Vceo (max) 18 V 25 V Vcb0 (max) 18 V 40 V

fT (min) = gain/bandwidth product 120 MHz 100 MHz hfe (= a.c. beta) 55-100 at 2 mA 60-300 at 50 mA hfe (= a.c. beta)

(code red) 90-180 at 2 mA (code orange) 150-300 at 2 mA (code yellow) 235-470 at 2 mA (code green)

Icbo (

max> 0.5 MA 0.1 MA

Ptot (max) 200 mW 300 mW

2N2926 2N3702

Fig. 1.1

Symbols, and lead connections (looking into the base) of the 2N2926 and 2N3702 transistors

and the mos t impor t an t po in t t o not ice is tha t the emitter-base potent ia ls of the silicon transistors are 0.65 V, while t ha t of the germanium is only 0.2 V. This difference be tween the emitter-base junc t ion potent ia ls is the mos t significant po in t t o bear in mind when designing amplifiers t ha t are in o ther ways similar. In the case of Fig. 1.2, the germanium p n p circuit can be modif ied t o opera te wi th a silicon transistor by simply altering the value of Rx t o give the required base po ten t ia l , leaving R2, ^ 3 , and R4 una l te red . I t can be made t o work wi th an n p n silicon type b y also t ransposing the supply connec t ions , as in Fig. 1.2c.

Al though convent ional germanium transistor circuits can be easily arranged t o work wi th silicon types , such an approach is ra ther poin t -

110 SEMICONDUCTOR PROJECTS 3

less, since it does n o t take full advantage of the benefi ts offered by

silicon transistors. With this po in t in m i n d , some practical circuits will

n o w be considered.

Simple common emitter amplifiers

As shown in Fig. 1.2a, germanium transistors require fairly complex biasing ne tworks ; Ru R2, R*, and C2 are used for this pu rpose . This complex i ty is needed par t ly t o allow for differences in the cur ren t gains of individual t ransis tors , b u t mainly t o compensa te for the large leakage currents t ha t are inherent w i th germanium transis tors . Silicon transistors , on the o ther h a n d , have very low leakage cur ren ts , a n d

Fig. 1.2

Similar common emitter circuits, using different types of transistor. Note the differences between ' the emitter-base potentials of germanium and silicon transistors, and the differences in supply polarity of npn and pnp types,

(a) pnp germanium circuit (b) pnp silicon circuit (c) npn silicon circuit

(a) ( b )

(c)


their bias ne tworks can thus be considerably simplified, wi th n o

deter iora t ion in per formance . Fig. 1.3 shows a simple c o m m o n emi t te r

amplifier designed a r o u n d an n p n silicon-planar t ransis tor .

Here , only a single base-bias resistor, Ru is used , and is connec t ed directly be tween base a n d col lector . This connec t ion provides a reasonable degree of negative feedback, and so compensa tes for large variations in the hfe values of individual t ransis tors , and for substant ial variations in supply line po ten t ia l .

The design is sufficiently well stabilised t o opera te f rom any supply in the range 3 - 1 5 V. Using a 9 V supply, the circuit gives a voltage gain of 4 6 dB (= 2 0 0 t imes) , an inpu t impedance of 1.5 k , and a f requency response which is wi th in 3 dB over t he range 27 H z - 1 2 0 kHz .

A similar per formance is ob ta ined from the alternative p n p version of thf amplifier, which is shown in Fig. 1.4.

These circuits can be used wi th alternative values of col lector load , if required , by simply adjusting the value of Rt t o bring t h e collector potent ia l t o roughly half the supply line voltage.

2-Stage direct coupled amplifiers

The l o w leakage currents of silicon transis tors enable direct coupl ing t o be used be tween amplifier stages in m a n y appl icat ions , a n d Fig. 1.5 shows a typical 2-stage direct coup led circuit designed a r o u n d n p n silicon t ransis tors .

& oV Fig. 1.3

Simple npn common emitter. Using a 9 V supply: Ay =46 dB

-3V TO 15V - V e

3 3 0 k Q <

C, 8/iF

5-6kQ<

C2 16/iF

OUT

•OV

Fig. 1.4

Simple pnp common emitter amplifier. Performance is similar to that of Fig. 1.3

Fig. 1.5

2-stage direct coupled amplifier. Using a 9 V supply: A V = 76 dB Zin = 3.9k£l Zout = 4.7 k£l fR = 35 Hz-35kHz ±3dB

IN-


Both transistors are connec ted as c o m m o n emit ter amplifiers, and the base-bias of Q l is derived from the decoupled emi t te r of Q2. Substant ial d.c. negative feedback is t hus ob ta ined , and the circuit 's working potent ia ls are well stabilised against variations in transistor characterist ics a n d supply line po ten t ia l . The circuit will opera te f rom any supply in the range 6-15 V.

Using a 9 V supply, the to ta l voltage gain of the circuit is 7 6 dB, the inpu t impedance is 3.9 k , the o u t p u t impedance is 4 .7 k, a n d the frequency response is wi thin 3 dB from 35 Hz to 35 kHz .

If the Q2 emi t te r decoupl ing capaci tor , C2, is removed , a substantial a m o u n t of a.c. negative feedback is i n t roduced t o t he c i rcui t ; the voltage gain then falls t o 4 6 dB , and the frequency response ex tends from 35 Hz to 120 kHz . The circuit can be made to give in te rmedia te values of gain and f requency response, if required, by replacing R3 with a 5 k f i po t , and connec t ing C2 be tween its slider and ground.

67 TO 157

OUT

Fig. 1.6

Alternative 2-stage amplifier. Performance is similar to that of Fig. 1.5

Fig. 1.6 shows an alternative version of the amplifier. I t uses one npn and one p n p transis tor , b u t gives a per formance tha t is a lmost identical t o tha t of the circuit of Fig. 1.5.

The two amplifiers shown in Figs. 1.5 and 1.6 each give an o u t p u t at Q2 collector tha t is in phase wi th , bu t m u c h greater t han , the inpu t signal at Ql base. Consequent ly , any signal feedback tha t occurs be tween the o u t p u t and the i npu t will be regenerative, so the amplifiers may t e n d t o be uns table if the supply lines are n o t proper ly decoupled , or if the inpu t connec t ions are n o t screened. This snag is overcome in the circuit of Fig. 1.7.


Here , Ql is wired as a c o m m o n emi t t e r amplifier, and has its

col lector direct ly coupled t o the base of emi t t e r follower Q2. 180° of

signal phase shift natura l ly occurs be tween the base and collector of

the Q l s tage, b u t zero phase shift occurs be tween the base and emi t te r

of 2 2 , so a to ta l of only 180° phase shift occurs b e t w e e n the inpu t

at Ql base and t h e o u t p u t at Q2 emi t te r , and any feedback tha t occurs

is degenerat ive. Ql base-bias is derived from Q2 emi t te r via R u so

negative feedback biasing is used, and t h e circui t ' s work ing potent ia l s

are well stabilised.

4 5V TO 15V+Ve

OUT

560kO

Fig. 1.7

Direct coupled amplifier with bootstrapped common emitter stage. Using a 9 V supply and an input signal from a 1 kn source:

A v =66dB Zin =330 SI zout

= 8 20 u

f# = 20 Hz-32 kHz ±3 dB

N o w , the signal appear ing at Q2 emi t te r is a lmost identical wi th

tha t at Ql col lector , bu t is at a low impedance and is effectively

isolated from it . In Fig. 1.7, this l ow impedance signal is fed, via C3, t o the j u n c t i o n of the R2-R3 split col lector load of Q l . Consequen t ly ,

a lmost identical a.c. signals appear at b o t h ends of R3, and only a

negligible signal cur ren t flows in this resistor, which thus appears as

a very high impedance t o a.c. signals; the effective a.c. value of R3 is

in fact increased t o several h u n d r e d k i lohms b y the use of this feed-

back or ' b o o t s t r a p ' t echn ique , and Ql therefore gives a very high

8 30 SILICON-PLAN A R TRANSISTOR PROJECTS

Emitter follower circuits

Emit te r follower circuits act effectively as impedance t ransformers . They give a high inpu t impedance , a l ow o u t p u t impedance , a n d near un i ty voltage gain. Fig. 1.8a shows a typical emi t te r fol lower.

Here , the i npu t impedance looking in to the base of the t ransistor is approx imate ly equal t o hfeJZ\02L&, where Z j o a (j is equal t o the com-bined parallel impedance of Re and any externa l load , Zx, t ha t is connec t ed a t the o u t p u t . This i n p u t impedance is s h u n t e d b y the base-bias resistors (Rx-R2), so the actual inpu t impedance , Z ^ n, of the comple te uni t is equal , in this case, t o the c o m b i n e d parallel impedance of Ru R2 and / z / e . Z i o a d.

The inpu t resistance, R x n, looking in to the base of the t ransis tor , is roughly equal t o hfeRe.

Fig, 1.8

(a) Typical emitter follower circuit (see text) (b) Simple emitter follower giving a Zinofl80 kn

( a ) ( b )

voltage gain, which is finally made available a t the emi t te r of Q2 at a fairly low impedance level.

This circuit will opera te f rom any supply in the range 4 .5-15 V. Using a 9 V supply , i t gives a voltage gain of a b o u t 6 6 dB , an i n p u t impedance of 3 3 0 £2, and an o u t p u t impedance of 8 2 0 £1. T h e f requency response varies somewha t wi th the source impedance of the inpu t signal; wi th a 100 12 source , the 3 dB po in t s occur a t 3 0 Hz a n d 4 5 k H z , and wi th a 1 k£2 source at 20 Hz and 3 2 k H z .

110 SEMICONDUCTOR PROJECTS 9 T o enable the emi t te r follower t o handle the largest possible signal

levels, it is usually biased so tha t its emi t te r is at a quiescent potent ia l of roughly half the supply line voltage. The s tandard way of achieving this in germanium circuits , where base leakage currents are large and may be comparable t o normal bias cur ren ts , is to wire Rx and R2 as a potent ia l divider ne twork , as in the diagram. The emit ter of a transistor inevitably takes u p a potent ia l tha t is wi thin a fraction of a volt of tha t on its base, so, if Ri = R2, and R2 is small relative t o R[n, the required bias condi t ions are natural ly m e t , and are n o t greatly al tered by normal variat ions in the leakage currents of germanium transistors . The major snag with this m e t h o d of biasing is tha t the bias resistors impose a severe restr ict ion on the m a x i m u m available inpu t impedance of the circuit .

Silicon transistors , on the o ther h a n d , have very low leakage currents , so, assuming tha t these are low relative t o the normal base-bias currents , the required bias condi t ions can be m e t by simply wiring a single resistor, Ru wi th a value equal t o R[n, be tween the base of Ql and the +ve supply l ine, as in the practical circuit of Fig. 1.8b. Ri a n d / ? i n then act effectively as a potent ia l divider base-bias ne twork , set t ing Ql base and emi t te r at roughly half of the supply line voltage, bu t cause only a small reduc t ion in the available input impedance of the circuit .

Using the c o m p o n e n t values shown, the circuit of Fig. 1.8b can be used with any supply in the range 3-15 V, and gives an inpu t im-pedance , wi th the o u t p u t un loaded , of abou t 180 k£2 at all voltages. Alternative values of Zxn can be ob ta ined by changing the values of Rl and R2. Rl should have a value of roughly 100 X R2, the values should be chosen so tha t R2 draws a quiescent cur ren t within the limits 0.5 m A - 2 0 m A .

If inpu t impedances substantial ly greater than a couple of h u n d r e d k i lohms are requi red , the circuit of Fig. 1.9 can be used. Here , Ql and Q2 are wired in the Darl ington or super-alpha m o d e , wi th the emi t ter current of Ql feeding directly in to the base of Q2, and act like a single transistor wi th a gain roughly equal t o the p r o d u c t of the t w o individual hfe values. In this m o d e , Ql opera tes at such a low current level tha t leakage currents become significant; t o minimise the effects of these , R4 is used as a stabilising resistor, and base biasing is provided by voltage divider n e t w o r k R\-R2. To minimise the shunt ing effects of Rx and R2 on Z j n, isolating resistor R$ is wired in place as shown, and is boo t s t r apped from Q2 emi t te r bia C2.

This circuit gives an inpu t impedance of abou t 3.3 M£2. The inpu t impedance can be reduced , if required , by lowering the value of R4,


down to a m i n i m u m of 18 k£l, at which po in t ZlTi = 1 Mft . Alternat ively,

the inpu t impedance can be raised t o abou t 5 M£2, by using a green

coded 2 N 2 9 2 6 transistor in the Ql posi t ion.

An alternative way of obta in ing a very high inpu t impedance a n d

near un i ty voltage gain is shown in Fig. 1.10. In this circuit , Ql and Q2

b o t h act as c o m m o n emi t te r amplifiers, bu t all of the Ql col lector signal

current flows directly in to the base of Q2, and all of the Q2

signal current flows th rough R3; t hus , the R3 signal cur ren t is roughly

equal t o the Ql base current t imes the p r o d u c t of the individual

4-5V TO 15V + V e

Fig. 1.9

Bootstrapped 2-stage emitter follower giving a Zjn of 3.3 Mn

-3V TO 15V+Ve

Fig. 1.10

Complementary feedback pair circuit, giving a Z / w of 6 Afft

110 SEMICONDUCTOR PROJECTS 11 t ransistor gains, a n d the i n p u t impedance t o t he base of Ql is roughly

equal t o R3hfeXhfe2. As far as voltage gains are conce rned , virtually

100% negative feedback is ob ta ined overall , so the circuit gives a gain

of a lmost exact ly u n i t y . Thus , t he circuit of Fig. 1.10, wh ich is k n o w n

as a c o m p l e m e n t a r y feedback pair , gives a per formance very similar t o

t ha t of a 2-stage emi t te r follower. Ri and R2 form a voltage divider base-bias n e t w o r k , which is

effectively isolated from Ql base by b o o t s t r a p p e d resistor RA. The circuit can be used wi th any supply in the range 3-15 V , and gives an inpu t impedance of a b o u t 6 M£2. This impedance can be raised t o a b o u t 10 M£2, if requi red , by using a green coded 2 N 2 9 2 6 transistor in the Ql pos i t ion .

Relay operating circuits

Transistors can be used t o modify the characterist ics of simple and inexpensive relays, e i ther t o effectively increase their cur ren t or voltage sensitivities, or t o give t h e m a built-in opera t ing t ime delay.

Fig. 1.11a shows a simple circuit in which Ql is wired as an emi t te r follower and uses a relay as its emi t te r load , t hus effectively increasing the relay 's cur ren t sensitivity b y abou t 5 0 t imes . R2 shunts base leakage cur ren ts t o g round in the absence of an inpu t bias, and should have a value 100 t imes greater t h a n the relay 's coil resistance. Rx limits the base cur ren t t o a safe value in the event of an excessive operat ing voltage being connec ted a t the inpu t . Dl p revents any back e.m.f. from damaging the circuit as the relay switches rapidly o n or off.

The actual relay used in this circuit ( and all o thers descr ibed in this sect ion) can be any type requiring an opera t ing cur ren t less t han 5 0 m A , and needing an opera t ing poten t ia l less t h a n 15 V . The circui t ' s supply rail should be at least 3 V greater t h a n the opera t ing voltage of the relay.

For correct opera t ion of Fig. 1.11a, t he inpu t voltage m u s t be con-nec ted wi th the polar i ty shown in the diagram. For some purposes , however , it m a y be required tha t t he relay be ope ra ted wi th ei ther polar i ty of i npu t , and this can be achieved b y wiring a bridge rectifier in the i n p u t , as shown in Fig. 1.1 l b . Diodes D2-DS can be any general purpose ge rmanium or silicon types . The i n p u t signal m u s t , of course , be ' f loating' relative t o the g round line if this modif icat ion is used.

If a greater increase t h a n fifty is needed in t he relay 's cur ren t sensitivity, t he circuit of Fig. 1.12a can be used. Here , R3 is given a value roughly 100 t imes greater t han R2 u p t o a m a x i m u m value of 1 M£l, and the circuit gives an increase in cur ren t sensitivity of abou t


Fig. 1.11b

(a) Circuit for increasing relay current sensitivity by 50 times. R2 = 100 times relay coil resistance, (b) Modification of Fig. 1.11a for operation by either polarity input. R2 = 100 times relay coil resistance, D2-D5 are general purpose

silicon or germanium diodes

500 t imes. Fig. 1.12b shows the modif icat ion for opera t ing wi th ei ther polari ty of inpu t voltage.

If an increase in b o t h the voltage and the current sensitivitv of the relay is required, the circuit of Fig. 1.13a can be used. Here , b o t h Ql and Q2 are wired as c o m m o n emit ter amplifiers. With no input con-nec ted , Ql is held at cut-off by R2, and Q2 is held cut-off by R3, so the relay does no t opera te and the circuit consumes only a small leakage cur ren t . When an input is connec ted to Ql base, b o t h Ql and Q2 are driven to sa tura t ion , and the relay opera tes . An input of roughly 700 m V at 4 0 JJLA is needed t o drive the relay on .

Fig. 1.13b shows the modif icat ion needed for operat ing wi th ei ther polar i ty of inpu t voltage. The bridge rectifier causes some loss in the voltage sensitivity of the circuit . If D2-D5 are germanium types , the

Di = SILICON DIODE

INPUT (EITHER

POLARITY) I

Fig. 1.11a

Di = SILICON DIODE


circuit needs an inpu t of abou t 1.1 V to opera te the relay, and if

D2-DS are silicon types , an input of nearly 2 V is needed .

Fig. 1.14 shows t w o circuits for imposing t ime delays on the opera t ion of the relay. Fig. 1.14a gives a delay be tween the m o m e n t of connect ing the supplv and the m o m e n t at which the relay actually tu rns on : Fig. 1.14b causes the relay t o switch on as soon as the supply is con-nec ted , b u t t o switch off again automat ica l ly after a p rede te rmined per iod. Timing per iods u p t o abou t one minu t e are ob ta inable .

In Fig. 1.14a, Q l and Q 2 are wired as a Darl ington emi t te r follower, wi th the base-bias ot Q l provided by the RrQ ' po ten t ia l divider ' ne twork . At the m o m e n t t ha t the supply is first connec ted , Q is discharged and Q l base is held at g round po ten t i a l , so the relay is off.

6V TO 18V + V e

Ql 2N2926(o)

Fig. 1.12a

INPUT (EITHER POLARITY)

Rl - \ A A A A —

lOkQ Qi 2N2926(o) |

> R3 >iooxR2

6V TO 18V + v e

Q2 2N2926 ( o )

RELAY Dl =

! SILICON DIODE

-0V

Fig. 1.12b

(a) Circuit for increasing relay current sensitivity by 50 times. R2 = 100 times relay coil resistance, (b) Modification of Fig. 1.12a for operation by either polarity input. R2 = 100 times relay coil resistance, D2-D5 are general purpose

silicon or germanium diodes


(N TO I8V + V e

Fig. 1.13a

6V TO 18V + V e

Fig. 1.13b

(a) Circuit for increasing relay sensitivity to 700 mV at 40 yA. (b) Modification of Fig. 1.13a for operation by either polarity of input. D2-D5 are general

purpose silicon or germanium diodes (see text)

Cx then charges u p via Ru and the voltage on Ql base and the voltage across the relay coil rises exponent ia l ly , wi th a t ime cons tan t of CxJlu until eventually the relay's operat ing voltage is a t ta ined and the relay tu rns on . T h e precise delay per iod depends on the value of C b on the relay's operat ing characterist ics, and on the supply line po ten t ia l used, b u t if t he supply is made a b o u t 3 V greater than the relay opera t ing voltage the delay is roughly equal t o 0.1 sec//xF of Q value, i.e., if Q = 100 /xF, delay = 10 sec.

110 SEMICONDUCTOR PROJECTS 15 Ql and Q2 are also wired as a Darl ington emi t te r follower in

Fig. 1.14b, b u t in this case the posi t ions of Rx and Cx are reversed. Consequent ly , when the supply is first connec ted , Cx is discharged and Ql base is shor ted t o the +ve supply rail, so the relay is driven ha rd on . Q then charges u p via Ru so the voltage across the relay coil decays exponent ia l ly wi th a t ime cons tan t of Ri.Cuuntil eventual ly the relay 's turn-off voltage is reached. The t ime delay depends a great deal on the

6V TO 18V + V e

lOOkQ

Qi 2N2926(o)

Q2 2N2926(o)

C| (SEE TEXT)

RELAY | 1 D . -* SILICON

DIODE

OV

Fig. 1.14a

6V TO 18V + V e

(SEE TEXT)

QI 2N2926 ( o )

Q2 2N2926 ( o )

lOOkQ

| RELAY | I D,= * SILICON

DIODE OV

Fig. 1.14b

(a) Circuit for giving a switch-on delay to a relay. R2 = 100 times relay coil resistance, (b) Circuit giving automatic turn-off of a relay after a predetermined

period. R2 = 100 times relay coil resistance


relay's on /of f voltage ra t io , bu t can be varied by choice of t h e Ci value,

which is t hus best found b y trial and error t o suit individual needs .

Voltage regulator circuits

Most silicon-planar t ransis tors have very sharply defined emit ter-base reverse b r e a k d o w n voltages, a n d their emit ter-base j unc t i ons t hus act as zener diodes. Figs. 1.15a a n d 1.15b show h o w the 2 N 2 9 2 6 and 2 N 3 7 0 2 t ransis tors can be used as zener d iodes .

The 2 N 2 9 2 6 ( 0 ) t ransistor gives a zener po ten t ia l of 9 -10 V , and the 2 0 0 mW m a x i m u m dissipation of t he device l imits t he m a x i m u m available cur ren t t o a b o u t 20 m A , so the circuit of Fig. 1.15a gives a

-ov -0V

( a ) ( b )

Fig. 1.15

(a) Connection of 2N2926(0) as zener diode, (b) Connection of 2N3702 as zener diode

regulated o u t p u t of abou t 9.5 V over the cur rent range 0 - 2 0 m A The value of Vm is n o t crit ical, and Rx is given by the formula in the diagram.

The 2 N 3 7 0 2 transistor gives a zener po ten t ia l of 7-8 V, a n d can handle m a x i m u m currents of abou t 3 7 m A . Fig. 1.15b shows a circuit giving a regulated o u t p u t of a b o u t 7.5 V over the range 0 - 3 5 m A .

In b o t h of these circuits , the Rx value is chosen t o l imit the zener cur ren t t o the m a x i m u m permissible value, wi th the o u t p u t un loaded .

Regula ted o u t p u t s greater t han 10 V can be ob ta ined b y wiring zener diodes in series. Fig. 1.16a shows h o w t o wire t w o 2 N 2 9 2 6 ( 0 ) zener diodes t o give an o u t p u t of abou t 19 V at 0 - 2 0 m A , and Fig. 1.16b


—! 1 I _ o V

(b)

Fig. 1.16 (a) Two 2N2926(0) zener diodes wired in series to give 19 V output (b) 2N2926(0) and 2N3702 zener diodes wired in series to give 17 V output

be tween the zener diodes a n d the o u t p u t , and Fig. 1.17a shows a practical circuit giving a regulated o u t p u t of abou t 18 V at 0 - 5 0 0 m A . Cx suppresses any ripple f rom the unregula ted l ine, and so gives a well s m o o t h e d o u t p u t . Approx ima te ly 0 .65-1 .0 V are ' los t ' in the emit ter-base j unc t i on of Q3, so the regulated o u t p u t is this a m o u n t less than the actual zener voltage.

Q3 is an M J E 5 2 0 min ia ture silicon n p n power transistor b y Motoro la ; th is t ransistor is c o m p l e m e n t a r y t o t h e M J E 3 7 0 p n p t y p e , a n d Fig. 1.17b a n d Table 1.2 show the characterist ics and connec t ions of b o t h types . Alternat ive silicon transistors can be used in the Q3 pos i t ion if preferred,

*)

shows h o w t o wire a 2 N 2 9 2 6 ( 0 ) and 2 N 3 7 0 2 in series for an o u t p u t of abou t 17 V a t 0 - 2 0 m A .

Larger o u t p u t cur ren ts can be ob ta ined by wiring an emi t te r follower

+ V e


3 0 V + V e (UNREGULATED)

+ V e

f*2 OUTPUT I k Q % I 8 V AT 0-500mA

Fig. 1.17

(a) Practical 18 V regulator, (b) Dimensions and connections of the MJE520 and MJE370 miniature complementary power transistors by Motorola

bu t mus t have hfe values of a t least 3 0 . The transistor has t o dissipate a m a x i m u m power of a b o u t 2 W, and should be m o u n t e d on an a lumin ium hea t sink wi th an area of 2 in

2.

Fig. 1.18 shows the circuit of a simple variable-voltage regulator , covering the approx imate range U-17.5 V at 0 - 1 A. R2 is wired across the zener ne twork , making a variable reference po ten t ia l of 0 - 1 9 V available to the base of Q3\ Q3 and Q4 are wired as a Darl ington emi t te r follower, so this variable po ten t ia l is m a d e available a t a high current level at Q4 emi t t e r ; abou t 1.5 V are ' los t ' in Q3 and Q4,

( b )


Table 1.2 C H A R A C T E R I S T I C S O F T H E M J E 5 2 0 A N D T H E M J E 3 7 0 M I N I A T U R E

C O M P L E M E N T A R Y P O W E R T R A N S I S T O R S B Y M O T O R O L A

MJE520 MJE370

Transistor Type npn pnp Ic (max) 3 A 3 A

Vceo (max) + 4 0 V - 4 0 V

Vcbo (

max> + 6 0 V - 6 0 V

fT at Vce 2 0 V 2 .8 MHz 2 .8 MHz hFE at Ic 0 . 7 5 A . 4 5 - 6 0 4 5 - 6 0

icbo (typ) 0 0 .1 MA 0.1 MA

Ptot (max) at 4 5 C 2 5 W 2 5 W (on heat sink with an area of 1 2 in

2)

however , so t he o u t p u t voltage is this a m o u n t less t h a n t he zener reference po ten t ia l .

In this circuit , Q4 m a y dissipate a m a x i m u m power of a b o u t 2 0 W, a n d mus t be m o u n t e d o n a hea t sink w i th an area of at least 12 in

2.

Q3 dissipates a m a x i m u m power of less t h a n 1 W, and can be m o u n t e d o n a hea t sink of 2 in

2. N o t e t h a t JR5 mus t have a power ra t ing of at

least 12 W.

N o t e t h a t , in the circuits of Figs. 1.17 and 1.18, t he unregula ted

3oV +Ve (UNREGULATED)

Fig. 1 . 1 8

Simple vatiable voltage regulator


Current regulator giving an output variable from approximately 0.65-12.0 mA

28V - V e

oV

Fig. 1.19

S E R I E S : LOAD

supply m u s t be derived f rom a t ransformer wi th fairly l ow copper losses, so tha t the full 3 0 V is available at m a x i m u m current load.

Current regulator circuits

The emi t te r a n d collector cur rents of a high gain t ransis tor are in-heren t ly a lmost identical in ampl i tude , a lmost irrespective of the collector voltage, and it follows t ha t the collector can t hus be used as a cons tan t -cur rent source by simply set t ing the emi t te r cur ren t t o t he requi red value. This t echn ique is of value in obta in ing cons tan t cur rents for charging D E A C bat ter ies , for l inearly charging capaci tors in t imer circuits , and for opera t ing zener diodes as stable voltage reference sources. Fig. 1.19 shows the circuit of a pract ical current regulator working on th is principle.

Here , Q l is wired as a zener d iode , and is opera ted a t a cur ren t of abou t 9 m A via Rx. This zener voltage is fed t o Q2 base , and so causes a regulated po ten t ia l of abou t 7 V t o appear at Q2 emi t t e r ; t he emi t te r ( and t hus the col lector) cur ren t of Q2 is thus d ic ta ted b y this potent ia l a n d by the c o m b i n e d resistance values of the emi t te r load resistors, R2 a n d # 3 , and can be varied over the app rox ima te range 0 . 6 5 - 1 2 . 0 m A via R2.

Thus , a cons tan t cur ren t , of magni tude variable via R2, is fed in to any series load c o n n e c t e d in the collector of Q2, and is i n d e p e n d e n t


of the resistive value of the load providing it is n o t so large t ha t the

transistor is sa tura ted .

In this circui t , t he m a x i m u m available cur ren t is res t r ic ted t o ab o u t 12 m A b y the l imi ted power dissipation capabilit ies of t he 2 N 3 7 0 2 transis tor . Greater cur ren ts can be ob ta ined , if required , by using a silicon power t ransistor in t he Q2 pos i t ion , and lowering the value of R3 t o l imit the m a x i m u m current t o the requi red value.

The circuit of Fig. 1.19 requires the use of a fixed 28 V supply . Fig. 1.20a shows the circuit of a cons tan t cur ren t generator tha t can

I7VT0 3 3 V + V e I7VT0 3 3 V + V e

Fig. 1.20

fa) Constant current generator operating from a variable voltage supply, (b) Modification of Fig. 1.20a to give variable constant-current output

be ope ra ted from any supply in the range 1 7 - 3 3 V, and which draws a, cons tan t cur ren t of a b o u t 2 8 m A .

Here , Ql is wired as a zener d iode , and applies a fixed po ten t i a l of abou t 9.5 V t o Q2 base ; Q2 has a fixed emi t te r load , R2, of 5 6 0 £2, so this transistor passes a cons tan t col lector cur ren t of a b o u t 17 m A .

( * ) ( b )


Sine/square converter

Fig. 1.21a shows t h e basic circuit of a Schmi t t trigger or voltage opera ted electronic switch, in which one or o the r of the transistors is on , a n d the o the r off, at all t imes . The values of Rx and R2 are chosen so tha t Q l is normal ly off, and under this condi t ion the t o p of jR4 ( t he Q2 base-bias resistor) is close t o the +ve rail voltage, so Q2 is biased ha rd on and its col lector is near g round volts . Ql can be driven ha rd on by applying a positive signal t o its base; under this condi t ion the t o p of R4 goes close t o g round po ten t ia l , and Q2 switches off, its collector going close t o full +ve rail voltage. The values of R3, R6, a n d R1 are chosen so t ha t regenerative ac t ion occurs as the transistors change s ta te . Thus , the circuit acts as an electronic switch which can be triggered f rom one s tate t o the o ther by the appl icat ion of a suitable inpu t voltage.

This t y p e of circuit can be used as a s ine/square conver ter . When a large ampl i tude sine wave signal is applied to Ql base, t he +ve par t s of the waveform cause Ql t o switch on , and the —ve par t s cause Ql

This 17 m A current is fed t o Q4, which is also wired as a zener d iode and applies a fixed po ten t ia l of abou t 7.5 V t o Q3 base ; Q3 has a fixed emi t te r load , Ru of 6 8 0 O , so this t ransistor passes a cons tan t collector cur ren t of a b o u t 11 m A , and this cur ren t is fed t o zener d iode Ql. T h u s , b o t h zener diodes are fed f rom cons tan t cur ren t sources, and their opera t ing potent ia ls are well regulated. Consequen t ly , the opera t ing cur ren t of t he ent i re circuit is f ixed at ab o u t 28 m A , and is virtually i ndependen t of variat ions in supply line po ten t i a l . R3 prevents t he t ransis tors cu t t ing off w h e n the supply is first appl ied, and so acts as a sure-start resistor.

The c o m p o n e n t values of Fig. 1.20a have been chosen so t ha t the circuit gives t h e m a x i m u m possible o u t p u t cur ren t , wi thin the working limits of the transistors used, i.e., w i th a 3 3 V supply a n d a shor ted o u t p u t load , the m a x i m u m voltage across Q3 is abou t 17 V, and the m a x i m u m power dissipations of t he transistors are as follows: Ql = 110 mW, Q2 = 2 9 0 mW, Q3 = 190 mW, and Q4 = 140 mW. Larger o u t p u t cur rents can be ob ta ined by using al ternative semiconduc tors and lower values of Rx and R2.

The circuit can be modif ied t o act as a variable cur ren t regulator by wiring a 2-gang 10 k£2 variable resistor in pos i t ion as shown in Fig. 1.20b. This modif icat ion enables the regulated cur rent t o be varied over the range 1.6-28.0 m A .


t o switch off again. Thus , a rectangular waveform appears at Ql and

Q2 col lectors, and has a mark /space ra t io of approx imate ly 1:1 , i.e., it

resembles a square wave. Fig. 1.21b shows the practical circuit of a s ine/sauare converter .

Fig. 1.21

(a) Basic Schmitt trigger, (b) Schmitt trigger used as a sine/square converter. Circuit has an input impedance of 40 k£l, and requires a sine wave input

greater than 100 m V r ms for a square wave output

( b )


Light operated switch

Fig. 1.22 shows h o w t h e Schmi t t trigger can be used as t he basis of a light ope ra ted switch. L .D.R. is a c a d m i u m sulphide pho toce l l , or light dependen t resistor, a n d has a high resistance under dark cond i t ions a n d a l ow resistance under bright condi t ions . The l.d.r. forms a po ten t ia l divider n e t w o r k wi th Ru and the po ten t i a l f rom the l.d.r.-Ri j u n c t i o n is used t o trigger the Schmi t t circuit via R2. Q3 is used t o opera te a relay, and is off when Q l is off, and is driven t o sa tura t ion w h e n Q l is on .

Thus , under br ight condi t ions , only a low voltage is fed t o Q l base via R2, so Q l , Q 3 , and the relay are off. Under dark cond i t ions , a large voltage is fed t o Q l base v i a / ?2 so Q l triggers on , driving Q 3 to sa tura t ion,

i 2 V - V e

Fig. 1.22

Light operated switch, giving automatic operation of car parking or side lights. L.D.R. is any cadmium sulphide photocell with a face diameter greater than 0.25 in

Ql is wired as a simple c o m m o n emitter pre-amplifier, a n d Q2 and Q3 are wired as a Schmi t t trigger. The circuit can be used wi th any supply in the range 6-15 V, has an i npu t impedance of a b o u t 4 0 k£l, and requires a sine wave i n p u t of a t least 100 m V r >m s t o give a square wave o u t p u t from Q3 col lector via C4. G o o d square waves are available over the f requency range of a few Her tz t o over 100 k H z ; should be adjusted t o give a 1:1 mark /space ra t io pulse o u t p u t on a ' scope ; the value of C 3 m a y be adjusted b y trial a n d error t o give t he best possible square waves a t very high frequencies, if requi red .

110 SEMICONDUCTOR PROJECTS 25 a n d driving the relay sharply on . Dl is used t o prevent any back e.m.f. f rom the relay coil damaging the circuit as t he relay changes s ta te .

The circuit is specifically designed t o au tomat ica l ly opera te car park ing or side l ights , via t h e relay con tac t s , a n d the precise trigger po in t can be adjusted via Ri. Cx is inc luded so t h a t the circuit is ope ra t ed b y m e a n , ra ther t h a n ins t an taneous , l ight levels, i.e., i t is no t effected b y sudden changes in light levels, as migh t occur w h e n driving unde r s t reet l ights, br idges, e t c . The relay can be any 9 -12 V t y p e w i th a coil resistance greater t h a n 2 7 0 £2.

The circuit is i n t e n d e d for use in cars wi th 12 V +ve g round sys tems. I t can be a d a p t e d for use in —ve g r o u n d systems b y using 2 N 2 9 2 6 ( 0 ) t ransistors in place of t he 2 N 3 7 0 2 types , and vice versa, a n d by reversing the polari t ies of Dl and Cv

Water operated switch

Fig. 1.23 shows h o w the circuit of Fig. 1.22 can be used wi th a +ve supply , a n d h o w it can be a d a p t e d as a wa te r ope ra t ed swi tch. In this case, the voltage t h a t is fed t o t he base of Q l via R2 is t aken from the emi t t e r of emi t t e r follower Q4. T h e base of Q4 is t a k e n t o g round via R9, so t h a t no rma l ly , wi th t he meta l p robes isola ted, the re is

12V + V e

Fig. 1.23

Water operated switch

26 30 SILICON PLANAR TRANSISTOR PROJECTS

near-zero voltage on Q l base, and the relay is off. If a resistance wi th

a value less t han abou t 3 3 0 k£2 is placed across the p robes , however ,

po ten t ia l divider act ion causes the emi t te r of Q4 t o go sufficiently +ve

t o trigger Ql, and the relay t hen switches o n .

Now, while it is t rue tha t distilled water has very good insulating

proper t ies , it is a fact t ha t the impuri t ies in normal t ap water , or even

in rain water in industrial areas, cause these l iquids t o have a fairly low

resistance, so , in Fig. 1.23, the relay can be ope ra ted by placing the

probes in normal water . T h e circuit has a n u m b e r of appl icat ions in

the h o m e ; i t can, for example , be used t o sound an alarm when b a t h

water reaches a p rede te rmined level, or t o automat ica l ly wind in an

o u t d o o r washing line when it rains, e t c .

Time switch

Fig. 1.24 shows h o w the circuit of Fig. 1.23 can be conver ted t o a

t ime switch, for use as a p h o t o t imer , e t c . Here , R9-R10 and Cx are wired

as a voltage divider ne twork , so t ha t , when the supply is connec ted ,

12V +Ve

Fig. 1.24

Time switch

110 SEMICONDUCTOR PROJECTS 27 Q charges exponent ia l ly wi th a t ime cons tan t tha t can be varied via Rio The rising exponent ia l voltage is appl ied t o Q 4 base, and appears at the j u n c t i o n of Rx and R n at a r educed ampl i tude , and is t h e n appl ied t o the base of Q l via R2. The values of Rt and R n are chosen so t ha t , w i th Rxo set a t m a x i m u m value, the Schmi t t circuit triggers and the relay goes on after a delay of approx imate ly 0.1 sec//xF value of Ch This delay can be increased, if required , by increasing the value of Ri or reducing the value of R n.

With Ci given a value of 100 juF, the delay can be varied f rom approx imate ly 0.5 t o 10 sec via R10, and wi th a value of 1,000 iiF i t can be varied f rom a b o u t 5 sec t o roughly 100 sec.

A.C. operated switch

A different t y p e of e lect ronic switch is shown in Fig. 1.25. Here , the relay opera tes when any a.c. i n p u t wi th an ampl i tude greater t han a b o u t 100 m V r > m > Si is appl ied t o Q l base. The inpu t impedance of t he circuit

12V +Ve

Fig. 1.25

A.C. operated switch, needing 100 mVrms to operate relay

is approx imate ly 6 k£2. The values of Rt and R7 are chosen so tha t a quiescent po ten t i a l of abou t 0.5 V is applied t o Q l base , so, wi th n o inpu t signal connec ted , Q l , Q2 and the relay are off.

When an inpu t signal wi th an ampl i tude greater t han a b o u t 3 0 0 m V peak- to-peak ( roughly 100 m V r > m > s< is applied to Q l base , the +ve par ts of the waveform drive Q l o n ; as Q l collector moves towards ground , t h e col lector signal is partially s m o o t h e d b y C2, so a —ve going

28 30 SILICON-PLANAR TRANSISTOR PROJECTS d.c. plus a x . signal is appl ied t o Q2 base , a n d t ha t t ransis tor is driven on . As Q2 is driven on , i ts col lector moves towards +ve line po ten t ia l , and the relay is driven on .

When the —ve going par t s of the i npu t waveform are appl ied t o Ql base , Ql cu t s off, b u t base cur ren t con t inues t o flow in Q2 via C2, so Q2 and the relay stay on . Thus , C2 effectively conver ts the switching ac t ion of Ql i n to a d.c. bias signal at Q2 base , and the circuit acts as an a.c. s w i t c h . / ^ p r e v e n t s excessive base cur ren t s flowing in Q2.

As well as act ing as a smoo th ing capaci tor , C 2 also impar t s a t ime delay t o the on/of f opera t ion of the circui t ; the dura t ion of this delay depends on the values of b o t h C2 and the relay coil resis tance. Long or shor t operat ing per iods can be ob t a ined b y increasing or decreasing the value of C2, t o suit individual r equ i rements . The relay can be any t y p e wi th a coil resistance greater t h a n a b o u t 1 8 0 £ 2 .

Sound operated switch

Fig. 1.25 can be modif ied t o act as a sound ope ra ted swi tch , for au to -matically opera t ing a tape recorder , e tc . , b y wiring a pre-amplifier in posi t ion as shown in Fig. 1.26. In this par t icular case t he amplifier of

ikQ 12V+Ve

(FROM MICROPHONE)

DI = SILICON

DIODE

Fig. 1.26

Sound operated switch, needing 0.1 mVr r.m.s.

to operate relay

110 SEMICONDUCTOR PROJECTS 29 Fig. 1.7 has been used for this pu rpose , b u t o ther circuits are equally sui table. Decoupl ing n e t w o r k R5-C2 is wired be tween the t w o main sections of the un i t , t o prevent instabi l i ty due t o posit ive feedback. C 3 reduces the circui t ' s gain at high frequencies, and so prevents opera t ion of t he switch b y stray signals p icked u p from the tape recorders bias oscillator.

C 6 is given a value of 50 fxF in this appl icat ion, and causes the switch t o opera te wi th in a b o u t half a second of t he inpu t signal being appl ied, b u t delays switch-off b y abou t 2.5 sec; these differences in switching t imes are mainly due t o the differences in o n and off opera t ing voltages of the normal relay.

The circuit needs an inpu t of a b o u t 0.1 m V r m s t o opera te the relay, and is suitable for use wi th hand-held low t o m e d i u m impedance mic rophones . Greater sensitivity can be ob ta ined b y using an addi t ional pre-amplifier.

Tone operated switch

The circuit of Fig. 1.26 can be modif ied t o act as a t o n e switch by incorpora t ing a f requency selective n e t w o r k in the design, ei ther at the inpu t or in a - v e feedback l o o p . Fig. 1.27 shows a pract ical t one switch of this t y p e , using a twin-T negative feedback e lement .

With the c o m p o n e n t values shown, the circuit is t u n e d t o a centre f requency, fQ, of a b o u t 2.5 k H z , has an effective ' Q ' of abou t 2 5 0 , and needs an inpu t of abou t 0.4 m V r m Si t o opera te the relay. When fed wi th a variable f requency inpu t signal wi th an ampl i tude ab o u t 5 0 % greater t h a n tha t needed t o opera te the relay a t the centre f requency, t he un i t exhibi ts a b a n d w i d t h of roughly ± 2 % of fQi and is t h u s suitable for use in mul t i -channel r e m o t e con t ro l appl icat ions , e t c .

The twin-T n e t w o r k (Rx-R2-RyCi'C2-C3) acts as a frequency-selective a t t enua to r , wi th inpu t appl ied t o C 8 and o u t p u t fed t o Q l base, and gives infinite a t t enua t ion a t ) ^ ,bu t low a t t enua t ion a t all o ther frequencies. Thus , when connec t ed in a negative feedback loop as shown, t he amplifier gives a very high gain at f0, b u t low gain at all o the r frequencies. Fo r satisfactory opera t ion (infinite a t t enua t ion a t f Q) , however , the twin-T c o m p o n e n t s mus t be precisely m a t c h e d in the following ra t ios :

Ri = R2 = 2 X JR3, and Cx = C2 = C$12. In prac t ice , the circuit gives good results if the twin-T c o m p o n e n t s are m a t c h e d t o be t t e r t h a n 5%.

The cent re frequency, ^ , is approx imate ly equal t o 1/(6.3 X Rx X CO, so fQ can be reduced b y increasing the resistor or capaci tor values. Ri and R2 values can be varied over the range 4 . 7 - 2 2 . 0 k£2; the non-


Di= SILICON

DIODE

R, R2 6-8kQ 6 8 k Q

Fig. 1.27 2.5 kHz tone operated switch, needing 0.4 mVrmSt to operate relay.

N.B. Ri, R2, R3, Ci, C2 and C3 should be 5% or better

and error . C 10 has been given a value of 0.1 juF in this appl icat ion, to make the uni t suitable for use wi th pulsed tone signals, b u t this value can be varied t o suit individual requi rements . Rs and C 7 are used t o prevent positive current feedback at fQ, wi th consequent instabi l i ty; their values may require adjus tment at o ther frequencies, if stabili ty is poor . The sensitivity of the circuit can be reduced , if requi red , by increasing the R4 value.

Multivibrator circuits

Fig. 1.28 shows the circuit of a symmetr ical 1 kHz astable mult i -vibrator , or square wave generator . O u t p u t s can be taken from either

s tandard R3 values can be ob ta ined by wiring two Rx resistors in parallel. The low frequency rejection characteristics of the circuit can be

improved, if required, by reducing the values of C4, C6, and C 9, by trial

Rio

IkO 12V +Ve

2V TO 9V + V e

OV

Fig. 1.28

Symmetrical 1 kHz multivibrator or square wave generator

2V TO 18V + V e

Qi 2N2926(o)

Fig. 1.29 Simple bistable multivibrator or memory unit

2V TO 9V + V e

Qi 2N2926(o)

-OV

Fig. 1.30 Monostable multivibrator or one-shot pulse generator, giving 2.5 sec output pulse


collector , a n d the circuit is suitable for use as a signal injector . The on and off per iods of this t ype of circuit are con t ro l led by the

Ci~R4 and C2-R3 t ime cons tan t s ; if these t ime cons tan t s are equal (Cx = C2 and R3 = R4) the circuit acts as a square wave genera tor , a n d opera tes wi th a f requency of approx imate ly 1/1.25 X Q X R3. Thus , the opera t ing f requency can be decreased by increasing the values of Cx a n d C2.

Note tha t the opera t ing f requency is virtually i ndependen t of supply rail po ten t i a l . A n y supply in the range 2 - 9 V can be used wi th this part icular circuit .

Fig. 1.29 shows a simple bistable mul t iv ibra tor or m e m o r y uni t . Here , ei ther Q l is on and Q2 is off, or vice versa. The s tate of the circuit can be changed by momen ta r i l y short ing the base of the ' o n ' t ransistor t o g round . The circuit t h e n mainta ins this n e w state unt i l t he base of the new ' o n ' t ransistor is shor ted t o g round . O u t p u t s can be t aken from ei ther col lector . A n y supply in the range 2 -18 V m a y be used.

Finally, Fig. 1.30 shows the circuit of a monos tab le mul t iv ibra tor , or one-shot pulse genera tor . Here , Q l is normal ly on and Q2 is off; when the base of Q l is briefly shor ted t o g round , the circuit changes s ta te , b u t after a delay de te rmined by the Rs-Cx t ime cons tan t re turns automat ica l ly t o the normal cond i t ion . With the c o m p o n e n t values shown, t he pulse dura t ion is approx imate ly 2.5 sec. The circuit can be triggered electronical ly, if requi red , via a negative pulse applied t o Q l base. O u t p u t s can be t aken from either col lector , a n d the circuit can be used wi th any supply in the range 2 - 9 V.

C H A P T E R 2

15 FIELD-EFFECT TRANSISTOR PROJECTS

One of the mos t i m p o r t a n t new semiconduc tor devices t o have been in t roduced in recent years is the field-effect t ransis tor , or f.e.t. This device resembles a convent ional t ransistor in a n u m b e r of ways , bu t has t he ou t s t and ing advantage of offering a very high inpu t impedance at i ts 'ga te ' .

T w o basic t ypes of field-effect t ransistor are in use , and are k n o w n as the ' junction-gate f.e.t . ' ( J U G F E T ) and the ' insulated-gate f.e.t. ' ( I G F E T ) types . T h e I G F E T type is, however , ra ther easily damaged if n o t carefully hand led , so in this vo lume only t he J U G F E T type will be considered, and will be referred to simply as an ' f .e . t . '

An f.e.t., like an ordinary t ransis tor , is a three- terminal device: the terminals are k n o w n as the ' source ' , the 'ga te ' , and the 'd ra in ' , and cor respond respectively t o the emi t t e r , base, and the col lector of a normal t ransis tor . 'N-channel ' or 'p -channel ' versions of t he f.e.t. are available, j u s t as normal transistors are available in ei ther n p n or p n p versions, a n d Fig. 2.1a shows the convent ional symbols and supply polarit ies of b o t h types of f.e.t. and of b o t h types of ord inary t ransis tor .

Like ord inary t ransis tors , f.e.t.s can be used as amplifiers in any of th ree basic ways. Fig. 2 .1b shows the three al ternat ive m o d e s of opera t ion for n p n t ransis tors , ( c o m m o n emi t te r , c o m m o n base, a n d c o m m o n col lec tor) , and for n-channel f.e.t .s, ( c o m m o n source , c o m m o n gate, and c o m m o n drain) .

34 15 FIELD-EFFECT TRANSISTOR PROJECTS

F.E.T. characteristics

The mos t impor t an t characterist ics of the f.e.t. are as fol lows:

(1 ) When an f.e.t. is connec t ed t o a supply wi th t h e polar i ty

shown in Fig. 2.1a, (drain +ve for an n-channel f.e.t., - v e for

+ V e - V e

COLLECTOR

EMITTER

/ — ^ C O L L E C T O R ^ 7 - ^ D R A I N /"Zj\D

B A s F v K J GATE \r-l) GATE \

R E M I T T E R ^ — q SOURCE ^ - ^ J S

COMMON SOURCE

(N-CHANNEL)

•OV -0V

DRAIN

) SOURCE

PNP TRANSISTOR N-CHANNEL F.E.T.

( a )

+ V e

- O V

P-CHANNEL F.E.T.

COMMON GATE

(N-CHANNEL)

( b )

Fig. 2.1

+ V e

COMMON COLLECTOR (NPN)

(EMITTER FOLLOWER)

+ V e

COMMON DRAIN

(N-CHANNEL)

(SOURCE FOLLOWER)

(a) Transistor and f.e.t. symbols, with supply polarities, fb) The three basic transistor operating modes, and the f.e.t. equivalents

COMMON EMITTER (NPN) COMMON BASE (NPN)

NPN TRANSISTOR

BASE

/10 SEMICONDUCTOR PROJECTS 35

DRAIN-TO-SOURCE VOLTAGE, V d s, ( V )

Fig. 2.1c

Typical transfer characteristics of n-channel f.e.t.

a p-channel f .e. t . ) , a drain cur ren t , flows in the device. T h e magn i tude of /</ can be con t ro l led via a gate-to-source bias vol tage, Vgs.

(2 ) Id is a t a m a x i m u m when Vgs = 0 , a n d is r educed ( t o bring the device i n t o a linear opera t ing region) b y applying a reverse bias t o t he gate . Thus , a —ve gate voltage reduces 1^ in an n-channel f.e.t., and a +ve bias has a similar effect in a p -channel device. The magni tude of Vgs needed t o reduce /</ t o zero is called the 'p inch-of f vol tage, Vp, a n d typical ly has a value be tween 2 and 10 V . T h e magn i tude of Id w h e n Vgs = 0 is deno t ed as 1^, and typically lies be tween 2 and 2 0 m A .

(3) The gate-to-source j u n c t i o n of the f.e.t. has the characterist ics of a silicon d iode . When reverse biased ( to bring t he f.e.t. i n t o a l inear opera t ing region) , gate leakage cur ren ts , I g s Si are on ly a couple of n A (1 n A = 0 .001 / iA) at r o o m t e m p e r a t u r e s ; I g ss approx imate ly doubles wi th every 10°C t empera tu re rise, so only increases t o a few /xA at 125°C. Actua l gate signal cur rents are only a fract ion of an n A , and t h e inpu t impedance t o t h e gate is typical ly a t h o u s a n d m e g o h m s a t l o w frequencies ; t he gate j u n c t i o n is effectively s h u n t e d b y a capaci tance wi th a value of a few picofarads, so i n p u t impedances fall as f requency is increased. If t h e gate-to-source j u n c t i o n is fo rward biased,

o

DR

AIN

CU

RR

EN

T,I

<j,

(mA

)


i t conduc t s like a normal silicon d iode , and if i t is excessively reverse biased it avalanches like a zener d iode ; in ei ther case, the f.e.t. suffers n o damage if the gate currents are l imited t o a few mil l iamperes.

(4 ) Fig. 2 .1c shows the typical transfer characterist ics of an n-channel f.e.t. N o t e tha t , for each value of Vgs, drain cur ren t Id rises l inearly f rom zero as the drain-to-source voltage, V^Si is increased from zero u p t o some value a t which a ' k n e e ' occurs on each curve. Thus , be low this k n e e , t he drain-to-source terminals act as a resistor wi th a value d ic ta ted by VgS9 i.e., as a voltage-variable resistor. Typical ly, the drain-to-source resistance, R^s, can be varied f rom a couple of h u n d r e d ohms (at Vgs = 0) t o thousands of megohms (at Vgs = Vp).

(5) The gain of an f.e.t. is specified as t r a n s c o n d u c t a n c e , # m, and signifies the rate of change of drain current wi th gate voltage, i.e., a gm of 5 m A / V signifies tha t a variat ion of one volt on the gate p roduces a change of 5 m A in 1^. N o t e tha t the form I/V is the inverse of the ohms formula , so measurements specified in this way are usually expressed in ' m h o s ' . Usually, gm is specified in f.e.t. data sheets ei ther in t e rms of m m h o s (mill i-mhos) or /xmhos (micro-mhos) ; t h u s , a gm of 5 m A / V = 5 m m h o = 5 ,000 / / m h o .

This comple tes the descr ipt ion of the general characterist ics of the f.e.t. At this po in t , t h e n , we can select a specific f.e.t. for exper imenta l work , and then go on t o consider a few practical circuits in which it can be used. The inexpensive 2 N 3 8 1 9 n-channel f.e.t. has been selected for this purpose , a n d Fig. 2.2 and Table 2.1 show the general character-istics and lead connec t ions of this part icular device, which is encapsula ted

Table 2.1 G E N E R A L C H A R A C T E R I S T I C S O F T H E 2 N 3 8 1 9 F . E . T .

Vps ~ + 25 V (= max drain-to-source voltage). KDG

= + 25 V (= max drain-to-gate voltage).

VGS

= - 25 V (= max gate-to-source voltage).

Vp = - 8 V m ax (= gate-to-source voltage needed to cut off/^). Idss

= 2-20 mA(= drain-to-source current with Vgs = 0).

Izss = - 2 n A m ax (= gate cut-off (leakage) current at 25°C). 1Q = 1 0 mA (= max gate current). gm = 2.0-6.5 mmho (= small signal common source forward transconductance). Qss ~ 8 pFmax (

= common source short-circuit input capacitance).

PT ~ 200 m W m ax (= power dissipation, in free air). fj* = 1 0 0 MHz (= gain-bandwidth product).

T O - 9 2 CASE 2N38I9 SYMBOL (BOTTOM V I E W ) (N-CHANNEL)

Fig. 2.2

Connections of the 2N3819 f.e.t.

(c)

Fig. 2.3

(a) f.e.t. self biasing system, (b) f.e.t. off-set gate biasing system, (c) Constant current f.e.t. biasing system

- S O U R C E DRAIN-

GATE


in an epoxy TO-92 package. The device is available from a number of manufacturers .

F.E.T. biasing

Three basic f.e.t. biasing systems are in use, each wi th its own par-ticular advantages and disadvantages. The simplest of these is the self-biasing system shown in Fig. 2.3a. Here , the gate is t ied t o g round via Rg, andRs is wired be tween the source and g round ; any cur ren t flowing in Rs causes the source t o go +ve relative t o the gate , so the gate is effectively —ve biased under this condi t ion . Suppose tha t we want t o set Id at 1 m A , and k n o w tha t a Vgs bias of - 2 . 2 V is needed to set this condi t ion ; the correct bias can be ob ta ined by wiring a 2.2 k£2 resistor in the Rs posi t ion, since 1^ flows in Rs, and a current of 1 m A through an Rs of 2.2 k£2 gives the required Vgs of —2.2 V. If t ends t o decrease for some reason, Vgs automat ical ly decreases as well and so causes 1^ t o increase and counte r the original change; t hus , the bias is self-regulating via negative feedback.

Unfor tunate ly , in practice the precise value of Vgs needed t o set a given 1^ may vary widely be tween individual f.e.t.s of the same t y p e : The only sure way of sett ing an accurate 1^ in this system is, therefore , t o either select Rs by trial and error , or t o replace it wi th a variable resistor.

A more reliable m e t h o d of biasing is the off-set gate sys tem shown in Fig. 2 .3b. Here , po ten t ia l divider Ri-R2 applies a fixed +ve bias t o the gate via Rg, so the potent ia l on the source is equal t o this +ve bias plus the +ve value of Vgs; Rs is chosen so tha t the required drain current flows wi th this source voltage. Thus , if the +ve gate voltage is large relative t o Vgs, 1^ is contro l led mainly by the values of Rs and the +ve gate bias, and is no t greatly influenced by variations of Vgs be tween individual f.e.t.s. This system therefore enables 1^ values to be set wi th reasonable accuracy and wi thou t need for individual c o m p o n e n t selection. Similar results can be alternatively ob ta ined by connect ing the gate t o ground via Rg and taking the b o t t o m end of Rs t o a large —ve voltage.

The th i rd type of biasing system is shown in Fig. 2 .3c . Here , the normal source resistor is replaced b y n p n transistor Q2. which is wired as a cons tant cur ren t source and so determines the value of The value of this cons tan t cur ren t is in tu rn de te rmined by the voltage on Q2 base (set by potent ia l divider Rx-R2) and by the value of emi t ter resistor R3; in some circui ts ,Z?2niay be replaced b y a zener diode or some


other voltage reference device. Thus , in this sys tem, 1j is i ndependen t of the f.e.t. characteris t ics , and very good stabil i ty is ob ta ined , at the expense of increased circuit complex i ty and cost .

In t h e th ree biasing systems described, Rg can have any value u p t o a b o u t 10 M H , the m a x i m u m limit being imposed by t h e po ten t i a l d rop across th is resistor caused by gate leakage cur ren t s , which m a y upset the biasing condi t ions .

Basic source follower circuits

The ou t s tand ing feature of t he field-effect t ransistor is i ts inherent ly high inpu t impedance , and full advantage can be t aken of this character-istic when the device is used in the c o m m o n drain or source follower m o d e ( the f.e.t. equivalent of t he emi t te r follower m o d e ) . Fig. 2.4a shows a simple circuit of this t y p e .

Here , a self-biasing sys tem is used, and the drain cur ren t can be varied via Rv The circuit can be used wi th any supply in the range

12V TO 20V + V e 12V TO 20V + V e

Fig. 2.4

(a) Simple source follower, giving: A v = 0.95

Z[n = 10 MSI shunted by 10 pF (b) Simple source follower, giving:

Av = 0.95

Zjn = 44 MCI shunted by 10 pF

W 0 0


1 2 - 2 0 V, and Rx should be adjusted so tha t the quiescent potent ia l across R3 is 5.6 V, giving a drain current of 1 m A . The circuit gives a voltage gain of 0.95 be tween inpu t and o u t p u t .

Due t o the potent ia l divider ac t ion of the R\-R2 t o R3 chain, a degree of boo ts t rapp ing is applied t o R4, and its effective value is increased by abou t 5 t imes. The actual i npu t impedance of the circuit is a b o u t 10 MSI shun ted by 10 p F , i.e., it is 10 MSI a t very low frequencies, falling t o 1 MSI at abou t 16 kHz , and to abou t 100 kSl at 160 kHz .

Fig. 2 .4b shows an alternative version of the simple source follower circuit . In this case, gate off-set biasing is used, so individual c o m p o n e n t adjus tment is n o t required. Voltage gain is approx imate ly 0 . 9 5 . C2 is a boo t s t r ap capaci tor , and increases the effective value of gate resistor R3 by abou t 20 t imes . C2 can be omi t t ed f rom the design, if preferred.

With C2 r emoved from the circuit , the inpu t impedance of the design is abou t 2.2 MSI shun ted by 10 p F . With C2 in place, the input impe-dance is raised t o abou t 4 4 MSI shun ted b y 10 p F . Alternat ive impedance values can be ob ta ined by changing the R3 value, u p t o a m a x i m u m of 10 MSI.

Hybrid source follower circuits

The f.e.t. gives an ou ts tanding performance w h e n used in conjunct ion wi th ordinary t ransis tors , i.e., in hyb r id circui ts , Fig. 2.5a shows a hybr id version of the source follower, giving an inpu t impedance of abou t 5 0 0 MSI shun ted by 10 p F .

In this circuit , Dl and D2 are general purpose silicon diodes , and pass a s tanding cur rent via Rs, so a fairly cons tan t forward volt d rop of abou t 0.65 V occurs across each d iode , giving a fixed potent ia l of 1.3 V on Q2 base . Q2 is wired as an emi t te r follower, wi th emi t te r load R4\ a potent ia l d r o p of abou t 0.65 V occurs be tween the base and emit ter of this t ransistor , so abou t 0 .65 V is developed across and Q2 thus passes a cons tan t collector current of roughly 1 m A . Thus , Q2 supplies a cons tan t bias current to Ql source.

N o w , Ql is wired as a source follower, and the col lector of Q2 serves as its source load a n d appears as a very high impedance . Because of the very high effective value of this source load, the f.e.t. gives a voltage gain of a b o u t 0 .99 . C2 passes a boo t s t r ap signal from Ql source to R3i and because of the high voltage gain of the circuit this boo t s t r ap signal increases the effective value of R3 by a b o u t 100 t imes, i.e., to 1,000 MSI. Thus , the actual inpu t impedance of the circuit is equal t o this value shun ted by the f.e.t.s gate impedance , and works o u t at abou t 5 0 0 MSI shun ted by. 10 p F .

110 SEMICONDUCTOR PROJECTS 41 If the high effective value of source load (and thus the high inpu t

impedance) of this circuit is t o be main ta ined , the o u t p u t mus t ei ther

be t aken t o externa l circuits via an addi t ional emit ter follower, or

t aken only t o fairly high impedance loads .

Fig. 2 .5b shows h o w a p n p emi t te r follower, Q 3 , can be added t o

I2V TO 20V + V e

(A)

"OUT

GENERAL PURPOSE SILICON DIODES

OV

I5V TO 25V + V e

(b)

Fig. 2.5

(a) Hybrid source follower, giving: Ay = 0.99

Z in = 500 Ma II10 pF

(b) Modified source follower, giving: Ay = 0.99

Z in = 500MSI II 4.7pF

4 2 15 FIELD-EFFECT TRANSISTOR PROJECTS

C3 16/iF

"—Dl—•OUT "I

16/iF

OV

Simple common source amplifier with self-biasing, giving:

A V = 21 dB

Z M = 2.2 Ma// 50 pF fR = 15Hz-250kHz±3dB

Fig. 2.6a

the above circuit , enaoling an o u t p u t t o be t aken direct ly t o a low impedance external load via C3. In addi t ion , this part icular circuit in-corpora tes modif icat ions tha t reduce the effective shunt capaci tance of the inpu t impedance , and so enables an improved high f requency performance t o be ob ta ined .

The major par t of the shunt inpu t capaci tance of the source follower is due t o the internal gate-to-drain capaci tance of the f.e.t., and this capaci tance can be regarded as a reactance wired be tween the gate and drain terminals . In Fig. 2 .5b , resistor R1 is wired in series be tween the drain and +ve supply l ine, and the drain is boo t s t r apped from Q3 emit ter via C4. N o w , the o u t p u t signal at Q3 emi t t e r , and thus the boo t s t r ap signal on Q l drain, is a lmost identical wi th the input signal on Ql gate , so this boo t s t r ap signal is in fact applied to the reactance be tween gate a n d drain, a n d greatly increases its value. Since the re-actance of the gate-to-drain capaci tor is increased in this way , it follows t h a t the effective value of its capaci tance is reduced in p r o p o r t i o n , and its shunt ing effect on the inpu t impedance of the f.e.t. is therefore minimised.

In pract ice , the inpu t impedance of the modif ied circuit of Fig. 2.5b has been measured at 5 0 0 MSI shun ted Jby 4 .7 p F . Some of this capaci-tance is, however , due t o circuit ' s t rays ' , and the value can p robab ly be further r educed wi th care in c o m p o n e n t l ayou t and wiring.

Simple c o m m o n source amplifiers

Fig. 2.6 shows t w o ways of using the 2 N 3 8 1 9 f.e.t. as a simple c o m m o n source amplifier. In Fig. 2.6a a self-biasing sys tem is used, and the

12V TO isV+ve


circuit can be used wi th any supply in the range 12-18 V R3 should be adjusted so tha t 5.6 V is developed across R2.

Fig. 2.6a shows the off-set gate biasing version of the same circuit . In this case, the supply range is l imi ted t o be tween 18 and 2 0 V ; / ^ is

18V TO 20 V + V C

Fig. 2.6b

Simple common source amplifier with offset gate biasing, giving:

A v = 21 dB Z in = 2.2Mall 50 pF fR = 15Hz-250kHz±3dB

approx imate ly 1 m A . In b o t h of these circuits , the source is decoupled t o g round via C 2 a t signal frequencies.

These t w o circuits give a similar small signal pe r fo rmance , a l though this is subject t o some variat ion be tween individual f.e.t.s. On average, t h e voltage gain of b o t h circuits works o u t a t 21 dB (= approx ima te ly 12 t imes) , a n d the f requency response is wi th in 3 dB f rom 15 Hz t o 250 kHz . I n p u t impedance is a b o u t 2.2 M£l s hun ted b y 5 0 p F . This comparat ively high value of shun t capaci tance is due t o Miller feedback f rom drain t o gate , which effectively increases the value of the f.e.t.s gate-to-drain capaci tance in p r o p o r t i o n t o t he voltage gain of t he amplifier, i.e., by 12 t imes in this part icular case.

Hybrid common source amplifier

Fig. 2.7 shows the hybr id version of the simple c o m m o n source amplifier, using n p n t ransis tor Q2 as a cons tan t cur ren t bias supply for the f.e.t; t he source of Q l is decoupled t o g round via C2.

This version of the amplifier has excellent bias s tabi l i ty, and is


*>0UT

Fig. 2.7

Hybrid common source amplifier, giving:

Ay = 21 dB

Z in = 2.2Ma II50pF

fR = 15Hz-250kHz±3dB

GENERAL PURPOSE CON DIODES

suitable for use wi th any supply in the range 1 2 - 2 0 V. I ts small signal

per formance is identical wi th tha t of the amplifier shown in Fig. 2.6a.

A compound amplifier

Each of the three c o m m o n source amplifiers described above has a fairly large value ( 5 0 p F ) of shunt inpu t capacitance, and thus has a modera te ly low value of inpu t impedance at high frequencies ( approx-imately 32 k£2 at a frequency of 100 kHz) . Fig. 2.8 shows an alter-native version of the c o m m o n source amplifier, in which the inpu t shunt capaci tance is substantial ly reduced ( t o abou t 12 p F ) , t hus giving an increased inpu t impedance at high frequencies ( a b o u t 120 kSl at 100 kHz) . This circuit uses a variety of transistor opera t ing modes ( c o m m o n source, c o m m o n base , and c o m m o n col lector) , and is therefore k n o w n as a ' c o m p o u n d amplifier ' .

The cause of the large inpu t shunt capaci tance of the convent ional c o m m o n source amplifier is the Miller effect, which increases the f.e.t.s gate-to-drain capaci tance in p ropor t ion to the voltage gain be tween gate and drain. In Fig. 2 . 8 , the f.e.t. (Ql) is wired as a no rma l c o m m o n source amplifier, wi th cons tan t current biasing provided via Q2, bu t

I2V TO 20V + V e


in this case the drain of the f.e.t. is connec ted direct ly t o the emi t te r of a th i rd t ransis tor , Q3, which is wired as a c o m m o n base amplifier. N o w , as far as the f.e.t. is concerned , the emi t te r of Q3 appears as a very low impedance drain load, which effectively couples the drain to

I8V TO 24V +Ve

OUT

Fig. 2.8

GENERAL PURPOSE SILICON DIODES

Compound amplifier, giving: Av = 21 dB

= 2.2MSI II12pF iR = 15Hz-1.5MHz±3dB

ground at signal frequencies via the forward biased emit ter-base j u n c t i o n of Q3 and via C3; consequent ly , only negligible voltage amplif icat ion occurs be tween the gate and drain of Q l , and there is very little increase in the f.e.t.s gate-to-drain capaci tance as a result of the Miller effect. Ql therefore exhibi ts a fairly low value of inpu t shunt capaci tance .

Al though only negligible voltage amplif icat ion takes place be tween the gate and drain, current amplification takes place in the normal way, and the drain signal currents are fed direct ly in to the emi t te r of the c o m m o n base amplifier, Q3, which uses collector load R2. Q3 has near-uni ty current gain be tween emi t te r and col lector , so the signal currents flowing in R2 and in the drain of Ql are virtually identical ;

46 15 FIELD-EFFECT TRANSISTOR PROJECTS consequent ly , reasonable voltage gain ( a b o u t 21 dB) occurs be tween Ql gate and Q3 col lector . T o prevent external circuits wi th fairly large values of shun t inpu t capaci tance reducing the effective value of R2 (and t hus the amplifier 's voltage gain) a t high frequencies, the o u t p u t of the circuit is t aken from Q3 col lector via g 4 , which is wired as an emi t te r follower.

The comple te amplifier, which is suitable for use wi th any supply in the range 18-24 V, has a voltage gain of abou t 21 d B , an inpu t impedance of 2.2 MSI shun ted by 12 p F , and a f requency response which is within 3 dB from abou t 15 Hz t o 1.5 MHz.

F.E.T. voltmeters Fig. 2.9 shows h o w an f.e.t. can be used as the basis of a simple 3-range electronic vo l tmete r , giving a basic sensitivity of 22 .2 MSI per

O N / O F F

Fig. 2.9

Simple 3-range f.e.t. voltmeter

volt . Max imum full scale voltage sensitivity is 0.5 V , and inpu t resistance is cons tan t at 11.1 M O on all ranges.

RrRs

a nd ^ 9 toim a po ten t ia l divider across the 12 V ba t t e ry ,

and cause 4 V to appear across R9\ the t o p end of R9 is connec ted t o the g round of the circuit , which can be regarded as a ze ro volts l ine, so the b o t t o m end of R9 is at a po ten t ia l of 4 V —ve, and the t o p of Rn is at 8 V +ve. Q l is wired as a source follower, w i th its gate t aken


t o ground via the Rx t o R4 n e twork , b u t the source of Ql is connec ted t o the 4 V —ve line via source load Rs, so the f.e.t. is effectively given off-set gate biasing, and its drain cur ren t is au tomat ica l ly set at abou t 1 m A .

RrRs and Ql-Rs act as a bridge circuit , and Rs is adjusted so tha t , in the absence of an inpu t voltage at Ql gate , the voltage on Ql source is equal t o tha t on Rs slider, so the bridge is ba lanced and zero current flows in the mete r . A n y poten t ia l applied to Ql gate t h e n causes the bridge t o go ou t of balance b y an a m o u n t p ropor t iona l to the inpu t voltage, which can then be read directly on the mete r . Ri-R3 form a simple range mult ipl ier ne twork , giving full scale deflection ranges of 0.5 V, 5 V, and 50 V. Alternat ive ne tworks can be used if preferred, b u t close tolerance c o m p o n e n t s should be used if good accuracy is required. ^ 4 acts as a safety resistor, and prevents damage to Ql gate in the event of excessive inpu t voltages being connec ted .

In u s e , / ? 8 is first adjusted so tha t the mete r reads zero in the absence of an inpu t voltage. An accurately k n o w n poten t ia l of 0.5 V is t hen connec ted t o the gate , and R6 is adjusted t o give a full scale deflection on the mete r . These adjus tments are then repeated unt i l consis tent zero and full scale deflect ion readings are ob ta ined , and the uni t is then ready for use.

In prac t ice , this uni t is ra ther p rone t o drift wi th changes in tem-pera ture and supply vol tage, so f requent re-adjustment of the zero con t ro l is requi red; drift can be considerably reduced b y using a zener stabilised 12 V supply .

A low drift version of the f.e.t. vo l tmete r is shown in Fig. 2 .10 . Here , Ql and Q2 are wired as a differential amplifier, so any drift occuring on one side of the circuit is au tomat ica l ly coun te red by a similar drift on the o the r side, and very good stabili ty is ob ta ined . The circuit works on the bridge principle; Ql-Rs fo rm one arm of the bridge, Q2-R6 the o the r .

It is impor t an t t o no te tha t Ql and Q2 are selected f.e.t.s. in this circuit , and mus t have their I^ss values m a t c h e d wi th in 10%. The circuit can be used wi th any supply in the range 12-18 V, and the set t ing u p procedure is similar t o tha t described for the Fig. 2.9 circuit .

Very low frequency astable multivibrator

Fig. 2.11 shows the circuit of a very low frequency f.e.t. astable or free-running mul t iv ibra tor . The on and off per iods of the circuit are cont ro l led b y the t ime cons tan t s Ci~R4 and C2-R3\ because of the ultra-


Fig. 2.10

Low-drift 3-range f.e.t. voltmeter. Ql and 2 must have l^ss values matched within 10%

9VT0 12V + V e

l 1 ov

Fig. 2.11

V.L.F. astable multi, with cycling rate of one in 20 sec

high inpu t impedances of the f.e.t.s, the 'R' pa r t s of these t ime cons tan ts can be made very large, so tha t very long cycling per iods can be ob ta ined using fairly low values of 'C With the c o m p o n e n t values shown, the p r o t o t y p e circuit cycled at a rate of once every 2 0 sec, i.e., at a f requency of 0 .05 Hz. A second version of the circuit , using 4 0 /xF c o m p o n e n t s in the C\ and Ci posi t ions , cycled at a rate of once every 6 min . Cx and C2 mus t be low-leakage capaci tors , such as Mylar, T a n t a l u m , e t c .


The opera t ing principle of the circuit is similar t o tha t of the normal

t ransistor astable mul t i , excep t tha t in the f.e.t. case it is necessary t o

apply a charging voltage t o Q , b y closing the ' s ta r t ' b u t t o n for a b o u t

1 sec, t o ini t iate circuit ope ra t ion . Rs ensures t ha t excessive gate

cur ren ts d o n o t flow in Q l when the ' s ta r t ' b u t t o n is ope ra ted .

The on and off per iods of the circuit can be made variable, if

required, b y replacing b o t h R3 and R4 w i t h a 10 M£l variable resistor

in series wi th a 1 M£l fixed resistor. T h e values of d and Q can be

increased or decreased t o suit individual r equ i rements .

Timer circuits

Field effect t ransistors are suitable for use in a variety of e lec t ronic

t imer circuits , and Fig. 2 .12 shows one such example . With Cx given a

value of 1 juF, the p r o t o t y p e circuit gives a t iming per iod of 4 0 sec,

and wi th a value of 100 (J.F it gives a per iod of 35 min .

In this circuit , Ql is wired as a source follower, and has its gate

t aken t o the j u n c t i o n of t ime cons tan t n e t w o r k Ri-Cx. When the supply

is first c o n n e c t e d , C i is discharged, so Q l gate is at g round po ten t i a l , and

the source is a volt or t w o higher; the base of p n p t ransis tor Q2 is

connec ted t o Q l source v i a / ?3, so Q l is driven on under th is cond i t ion ,

and a 12 V o u t p u t appears across Rs. As soon as the supply is connec t ed , C\ s tar ts t o charge via Rl9 so

the voltages o n Q l gate and source rise exponent ia l ly t owards the 12 V

i 2 V + V e

Rl IOMQ

C, X l / i F f

OV

Fig. 2.12

Simple f.e.t. timer, giving a period of 40 sec when C\= 1 nF, and 35 min when C i - 1 0 0 VLF


i 2 V + v e

Fig. 2.13

Modified f.e.t timer, giving variable timing and switched output

o u t p u t . This snag can be overcome b y wiring a Schmi t t trigger circuit be tween Q2 and the o u t p u t , as shown in Fig. 2 . 1 3 . T h e circuit of Fig. 2 .13 also shows the modif ica t ions needed t o enable variable t iming per iods t o be ob ta ined .

Constant-volume amplifier

When opera ted wi th a low drain vol tage, the drain-to-source p a t h of the n-channel f.e.t. exhibi ts the characterist ics of a simple resistor, the value of which can be varied via a negative bias applied t o the gate;

supply l ine; eventual ly , w h e n Ql source rises t o abou t 10.5 V, the forward bias of Ql falls t o zero and Q2 switches off; zero volts o u t p u t appears across Rs unde r this condi t ion .

When the supply is removed from the circuit , d discharges rapidly via R2 and the forward biased internal gate-to-drain j unc t i on of Q l , and the circuit is t hen ready to carry ou t a second t iming opera t ion as soon as the supply is re-connected .

The circuit can be made to give a variable t iming per iod by re-placing Ri w i th a 10 MSI variable resistor and 1 MSI fixed resistor in series. C\ should be a Mylar or similar low-leakage type of capaci tor .

A minor disadvantage of the circuit of Fig. 2 .12 is t ha t Q2 switches off ra ther slowly, so a sharp switching act ion is n o t ob ta ined at the


lOOkQ

Fig. 2.14

Constant-volume amplifier, giving 7.5 dB change in output for 40 dB change in input. N.B. Dl and D2 are general purpose germanium diodes

a n e t w o r k can be used as the basis of a cons tant -volume amplifier. With 3 0 0 m V r < m s> applied to the input of the un i t , an o u t p u t of 0 .72 V is available on the p r o t o t y p e , and when the inpu t is reduced to 3 m V the o u t p u t falls to 0.3 V, i.e., a 4 0 dB change in the inpu t signal level p roduces a change of only 7.5 dB at the o u t p u t . Providing tha t inputs are kep t to less than 500 m V , the circuit gives very little d is tor t ion .

In this circuit , Ql mdR4 are wired as a voltage opera ted a t t enua to r , wi th inpu t applied t o Ql drain via Cu and o u t p u t t aken from Ql source via C3; a small positive voltage is applied t o the drain via Rx and

The o u t p u t from Ql source is fed t o the Q2-Q3 c o m m o n emi t te r / emi t te r follower amplifier, and the o u t p u t of Q3 emi t te r is fed, via C5 and R9, t o the Dl-Dl-C* rect i f ier /smoothing n e t w o r k , so tha t a —ve potent ia l is developed across C4, and is p ropor t iona l t o the signal ampl i tude at Q3 emi t te r . This —ve poten t ia l is applied t o Q l gate , and

this resistance is low when zero gate bias is applied, and very large when a substantial negative gate bias is applied.

This characterist ic of the f.e.t. makes it suitable for use in variable vol tage-operated a t t enua to r ne tworks , and Fig. 2 .14 shows h o w such

12V TO 18V + V e

52 15 FIELD-EFFECT TRANSISTOR PROJECTS so contro ls the a t t enua t ion of Ql-R4. Q ensures t ha t the gate-to-source bias is n o t m o d u l a t e d by the o u t p u t of the a t t enua to r , and thus keeps dis tor t ion low.

When a very small signal is applied t o the inpu t of the circuit , the o u t p u t at Q3 emi t te r is relatively small, so only negligible —ve bias is developed; under this cond i t ion , Ql appears as a low resistance, so very litt le a t t enua t ion occurs in Ql-R4, and almost the full inpu t signal is applied t o Q2 base.

When a large inpu t signal is applied t o the circuit , t he o u t p u t at Q3 emi t te r t ends t o be large, so a large —ve bias is developed; under this cond i t ion , Ql appears as a large resistance, so considerable a t t enua t ion occurs in Ql-R4, and only a small pa r t of the inpu t signal is applied t o Q2 base. Negative feedback occurs th rough the comple te circuit , so tha t in pract ice the o u t p u t level stays fairly cons tan t over a wide range of inpu t signal levels.

The ac t ion of Dl andZ>2 ensures tha t the —ve bias bui lds u p rapidly when an inpu t is applied via C5, b u t C4 ensures tha t the —ve bias decays again slowly when the inpu t is removed or reduced. Consequen t ly , when a complex speech or music signal is applied t o the un i t , the —ve bias circuit responds t o the peaks of the signal and so adjusts the gain t o give a fairly cons tan t peak vo lume, while in t roducing only negligible dis tor t ion t o the mean signal. With the c o m p o n e n t values shown, the decay t ime is a couple of seconds , and when the un i t is wired in the a.f. stages of a radio receiver it makes it possible t o t u n e t h rough a comple te waveband w i t h o u t need to adjust the vo lume con t ro l , b o t h s trong and weak s ta t ions appearing at equal vo lume.

For no rma l listening on a single s ta t ion , the value of C 4 should be increased t o 100 juF, t o increase t he decay t ime of the —ve l ine. T h e

4-5V TO 9V - V e

Fig. 2.15 f.e.t. chopper or d.c. to a.c. converter


F.E.T. chopper

Final ly , Fig. 2 .15 shows h o w the low voltage resistor-like character is t ics of the f.e.t. can be used in a chopper appl ica t ion , t o conver t a d.c. i n p u t voltage i n t o a square wave ' c h o p p e d ' o u t p u t wi th an ampl i tude equal t o the i npu t . This square wave can , if requi red , be fed t o an a.c. milli-vo l tmete r , so t ha t very small values of d.c. i npu t voltage can be indirect ly measured .

Ri and Ql are wired as an a t t enua to r n e t w o r k , and Q l is swi tched on and off by a —ve gate bias appl ied f rom the Q2-Q3 astable mul t i -v ibra tor , which opera tes at 1 kHz . With an inpu t c o n n e c t e d t o Ru and n o gate bias appl ied (Q2 o n ) , Ql acts as a very low resis tance, so on ly a negligible voltage appears on Ql d ra in ; wi th a large - v e gate bias applied (Q2 off), Ql acts like a near-infinite resis tance, so a lmost t he full inpu t voltage appears on Q l dra in . Thus , the o u t p u t , t aken from Ql drain, appears as a square wave wi th an ampl i tude p ropo r t i ona l t o the inpu t . The o u t p u t should be t aken t o a fairly high impedance .

When t o o large a —ve bias is applied t o the gate , the gate-to-source junc t ion of Ql s tar ts t o avalanche, and a small ' sp ike ' vol tage breaks t h rough t o the dra in , so a small o u t p u t is ob ta ined even t h o u g h n o d.c. i npu t is connec ted t o the circuit . T o prevent th is , t he circuit m u s t be set u p by connec t ing a d.c. i npu t t o the circui t , and then adjusting R4 unt i l the ampl i tude of t he o u t p u t j u s t s tar ts t o decrease . When set u p in this way , avalanching does n o t occur , and the circuit can reliably be used t o c h o p voltages as low as a fract ion of a millivolt .

circuit t h e n el iminates t he ' fade ' t ha t occurs on d is tan t s ta t ions , b u t

does n o t in t roduce excessive a u t o m a t i c vo lume ad jus tment dur ing brief

pauses in no rma l speech. This character is t ic is also useful in t ape recorder and in t e rcom circuits , e t c .

C H A P T E R 3

20 UNIJUNCTION TRANSISTOR PROJECTS

Anothe r impor t an t semiconductor device tha t has been in t roduced in recent years is the uni junct ion transistor , or u . j . This is a specialised bu t very simple device. It uses the symbol shown in Fig. 3.1a, employs the form of cons t ruc t ion shown in Fig. 3 .1b , and has the equivalent circuit of Fig. 3.1c.

Looking first at Fig. 3 .1b , the device is made u p of a bar of n- type silicon material wi th a non-rectifying contac t (base 1 and base 2) at ei ther end , and a th i rd , rectifying, con tac t (emi t te r ) al loyed in to the bar par t way along its length , to form the only j unc t i on within the device (hence the name 'un i junc t ion ' ) .

Since base 1 and base 2 are non-rectifying con tac t s , a resistance appears be tween these t w o po in t s , and is tha t of the silicon bar . This inter-base resistance is given the symbol RBB> normal ly has a value be tween 4 ,000 and 1 2 , 0 0 0 0 , and measures the same in ei ther direct ion.

In use, base 2 is connec ted t o a +ve voltage, and base 1 is taken to ground, so R^B acts as a voltage divider wi th a gradient varying from m a x i m u m at base 2 t o zero at base 1. The emi t te r j u n c t i o n is connec ted at some po in t be tween base 1 and base 2 , so some fraction of the base 2 voltage appears be tween the emi t te r j unc t ion and base 1. This fraction is the mos t impor t an t pa ramete r of the u . j . , and is called the ' intrinsic stand-off ra t io ' , 77, and usually has a value be tween 0.45 and 0 .8 .

The equivalent circuit of Fig. 3.1c illustrates the above po in t s . r$i and r$2 represent the resistance of the silicon bar , and diode Dl represents the j unc t i on formed be tween the emi t te r and the bar . When an external voltage, VRB, is applied t o base 2 , a voltage of V.V^B appears across and on the ca thode of Dl. If, under these condi t ions ,


SILICON BAR

Bl

( C )

Fig. 3.1

(a) Unijunction symbol (b) Unijunction construction, (c) Unijunction equivalent circuit

very high impedance of a reverse biased silicon d iode , w i th a typical impedance of several megohms .

If, on the o ther h a n d , VE is steadily increased above T?.P#£, a po in t is reached where Dl s tarts to become forward biased, so cur ren t s tar ts to flow from emi t te r to base 1. This cur ren t consists mainly of minor i ty carriers injected in to the silicon bar , and these drift t o base 1 and cause a decrease in the effective resistance of r^f, this decrease in rî causes a decrease in t h e D l ca thode voltage, so D l becomes m o r e heavily forward biased, and the emit ter- to-base 1 cur rent increases and in t u rn causes the TRI value to fall even more . A semi-regenerative act ion takes place, and

( b )

EMITTER

EMITTER-

BASE 2

REGION OF P-TYPE MATERIAL

BASE I

BASE I

BASE 2

a +ve inpu t voltage, VE, is applied be tween the emi t te r and base 1, b u t is less than diode Dl becomes reverse biased, so no appreciable current flows from emi t te r t o base 1, since the emi t te r appears as the

56 20 UNIJUNCTION TRANSISTOR PROJECTS

( b )

Fig. 3.2 (a) Basic relaxation oscillator, fbj Temperature stabilised relaxation oscillator

Here , when the supply is first connec ted , C is discharged and the emi t te r is at g round po ten t ia l , so the emi t te r appears as a high impedance ; C t hen charges exponent ia l ly towards VBB

v*

a ^ » b u t

as s o on as the

emi t te r reaches Vp the u . j . fires and C discharges rapidly i n to the low impedance of the emi t t e r . Once C is effectively discharged, the u . j . switches off and C s tar ts t o charge u p again, and the process is repea ted . Thus , a rough saw-tooth waveform is con t inuous ly generated be tween Ql emi t te r and g round .

the emi t te r inpu t impedance falls sharply, typical ly t o a value of abou t 2 0 O .

Thus , the uni junct ion transistor acts as a voltage-triggered switch, and has a very high inpu t impedance ( t o the emi t te r ) when it is off, and a low inpu t impedance when it is on . The precise p o i n t at which triggering occurs is called the 'peak-poin t ' vol tage, Vp, and is abou t 6 0 0 m V above T ? . F ^ .

It can be seen tha t the u . j . is a ra ther specialised device. I ts mos t c o m m o n appl icat ion is as a re laxat ion oscillator, as shown in Fig. 3.2a.

110 SEMICONDUCTOR PROJECTS 57 In this circuit , final switch-off occurs on each cycle when the

capaci tor discharge cur ren t falls t o a 'val ley-point ' value, IV9 typical ly of several mil l iamperes . A m i n i m u m 'peak-point emi t t e r cu r ren t ' , Ip, is needed to switch the u . j . on initially, and typical ly is a value of several mic roamperes .

T h e f requency of opera t ion of t he circuit is given approx ima te ly b y / = I ICR, and is virtually i ndependen t of VBB- Typica l ly , a 10% change in VBB results in a f requency change of less t han 1%. The value of R can be varied from abou t 3 k£2 to 5 0 0 k£2, so an at t ract ive feature of the circuit is t ha t it can be m a d e t o cover a f requency range greater than 1 0 0 : 1 via a single variable resistance.

F requency stabili ty is good wi th changes in t empe ra tu r e , and is abou t 0 .04%/°C. The main cause of this variat ion is the change of a b o u t — 2 m V / ° C tha t occurs in the forward vol t d r o p of the Dl j u n c t i o n wi th changes in t empera tu re . Stabi l i ty can be improved by ei ther wiring a couple of silicon diodes in series wi th base 2, or by connec t ing a stabilising resistor, Rs, in the same place. The RBB of the u . j . increases b y a b o u t 0 .8%/°C, so changes in the forward volt d r o p of D l can be coun te red by the changes in po ten t i a l divider act ion of Rs and RBB w i th changes in t empera tu re . The correc t value of Rs is

0.1 R BB (I-WB Rs +

t).VBB V

where RB = ex terna l load resistor (if any ) in series wi th base 1. A n exact Rs value is n o t i m p o r t a n t in mos t appl icat ions , however .

In some circuits , RB is wired be tween base 1 and g round , as shown in Fig. 3 .2b ei ther t o con t ro l the discharge t ime of C or t o give a +ve o u t p u t pulse during the discharge per iod . A —ve pulse is also available across Rs in this per iod , if needed .

TABLE 3.1

CHARACTERISTICS OF THE 2N2646 UNIJUNCTION TRANSISTOR

Emitter Reverse Volts (max) 3 0 V VBB (max) = 3 5 V

Peak Emitter Current (max) = 2 A R.M.S. Emitter Current (max) = 5 0 mA

Power Dissipation (max) = 3 0 0 mW = 0 . 5 6 - 0 . 7 5

RBB = 4 . 7 - 9 . 1 kn Ip (max) = 5 MA Iy (max) = 4 mA

case = T 0 1 8


Now tha t the basic principles of the u . j . have been described above, we can select a practical uni t and then go on to consider 20 or so

T 0 - I 8 C A S E

( B O T T O M V I E W ) Fig. 3.3

Lead connections of the 2N2646 unijunction transistor

applicat ions in which it can be used. The 2 N 2 6 4 6 u . j . has been selected for this purpose , and Table 3.1 and Fig. 3.3 show the general character-istics and lead connec t ions of this part icular device.

Wide-range pulse genera tor

Fig. 3.4 shows the practical circuit of a wide-range pulse generator . A large ampl i tude +ve pulse is available across R4, and a —ve pulse across R3; b o t h pulses have an ampl i tude of abou t half supply line volts, are of similar form, and are at a low impedance .

With the c o m p o n e n t values shown, the pulse wid th is cons tant at about 3 0 /isec over the frequency range 25 Hz-3 kHz (adjustable via Ri). The pulse wid th and frequency range can be altered by changing

Fig. 3.4

Wide-range pulse generator giving 30 iisec output pulses at repetition frequencies of 25 Hz-3 kHz

the value of Cx. Reducing d by a decade ( t o 0.01 JUF) reduces the pulse wid th by a factor of 10 ( t o 3 IXSQC) and raises the frequency range by a decade ( 2 5 0 H z - 3 0 kHz) . Cx can have any value in the range 100 pF-1 ,000 JUF.


A saw-tooth waveform is generated at Q l emi t t e r , b u t is at a high impedance and is thus n o t readily available external ly .

Wide-range saw-tooth generator

In Fig. 3.5 the saw-tooth waveform from Q l emi t te r is fed to emi t te r

follower Q 2 , making the saw-tooth readily available t o ex terna l circuits

wi th inpu t impedances greater than abou t 10 k£2. If the o u t p u t is t o

Ri

5 0 0 k Q /

3-3kO<

C| . o i / iF '

9 V T O 12V + V e

< 4 4 OV

Fig. 3.5

Wide-range saw-tooth generator covering the frequency range 25 Hz-3 kHz

be taken to impedances lower than 10 k£2, a second emi t t e r follower

should be wired be tween Q2 emi t ter and the o u t p u t . With the c o m p o n e n t values shown, the frequency range of the

circuit is variable from abou t 25 Hz-3 kHz via Rx. T h e operat ing frequency can be varied from less than one cycle per m i n u t e t o over 100 kHz b y changing the Ci value.

Linear saw-tooth generator

The ' saw- tooth ' at the emi t te r of the basic u . j . oscillator is of expo -nential form. In some appl icat ions, however , a perfect ly linear saw-t o o t h is required, and this can be ob ta ined by charging the main t iming capaci tor from a cons tan t current source, as shown in Fig. 3 .6 .

In this circuit , Ql is wired as an emi t te r follower, wi th emi t te r load R4, and feeds its collector current in to the main t iming capaci tor , C\. The emi t te r current of Q l , and thus the collector current of Q l and


B E A M - B L A N K I NG O U T P UT

Fig. 3.6

Linear saw-tooth generator, suitable for use as an oscilloscope time-base generator. Frequency range =50-600Hz with a9V supply, or 70-600 Hz with a 12 V supply

at Q2 emi t te r , and this is made available t o externa l circuits via emi t te r follower Q3. The o u t p u t should be t aken t o external circuits wi th inpu t impedances greater t h a n 10 k£2.

This part icular circuit can be used as a simple t ime-base generator for an oscil loscope. In this appl icat ion, the o u t p u t f rom Q3 emi t t e r should be t aken to the externa l t ime-base socket of the oscil loscope, and the +ve flyback pulses from R6 can be taken via a high voltage blocking capaci tor and used for beam blanking. The generator can be synchronised t o an external signal by feeding the ex te rna l signal t o base 2 of Q2, via C2. This signal, which should have a peak ampl i tude of be tween 2 0 0 m V and 1 V , effectively modula tes the supply voltage, and thus the triggering po in t , o f Q2, t hus causing Q2 t o fire in synchrony wi th the externa l signal.

C2 should be chosen to have a lower impedance than Rs at the sync signal f requency, and should have a working voltage greater than the external voltage from which the signal is applied.

the charging cur rent of C\, is de te rmined solely b y the set t ing of R2i so the Ci charging cur rent is cons tan t and this capaci tor charges in a linear fashion. Consequent ly , a linear saw-tooth waveform is genera ted

C2 ( S EE T E X T)

_ | | — S Y NC I N P UT

9 V T0 12V +Ve ( S T A B I L I S E D)

A W

/10 SEMICONDUCTOR PROJECTS 61 With the c o m p o n e n t s shown, the operat ing frequency can be varied

over the range 5 0 H z - 6 0 0 Hz using a 9 V supply , or 7 0 H z - 6 0 0 Hz

using a 12 V supply. Alternat ive frequencies can be ob ta ined by

changing the Cx value. A t very low frequencies, Cx should be a

reversible type of capaci tor .

Analogue/digi tal conver ter , resistive

The circuit of Fig. 3.7 converts changes in light level, t empera tu re , or any o ther quan t i ty tha t can be represented by a resistance, in to changes in f requency. The resistive e lement (l .d.r. , thermis tor , e tc .) is wired in parallel wi th Ru and so cont ro ls the charging t ime cons tan t

9V TO 12V + V e

OV

Fig. 3 .7

Analogue/digital converter (resistive). With element open circuit, frequency = 30 Hz; with element short circuit, frequency = 3.7 kHz

of Ci , and thus the f requency of opera t ion . A range of 30 Hz-3 .7 kHz is available, the lower f requency being ob ta ined wi th the e lement open circuit .

The o u t p u t is t aken from across R4, and consists of a series of pulses. When fed to an ea rphone , these can be clearly heard , even at the lowest f requency.

The uni t is of par t icular value in r emote reading of t empera tu re , e tc . , the o u t p u t pulses being used to modu la t e a radio or similar l ink. A t the

L.D.R., / THERMISTOR, I

OR OTHER

V

RESISTIVE ELEMENT


receiver end of the link, the digital informat ion can be conver ted back to analogue via a simple frequency mete r type of circuit .

Analogue/digi tal conver ters , voltage

The circuits in Figs. 3 .8-3 .10 have similar applicat ions to the resistance control led circuit already men t ioned , bu t have their operat ing frequencies control led by voltage, or any quan t i ty tha t can be represented by a voltage, i.e., via photo-vol t iac cells, the rmocouples , e tc .

Fig. 3.8 shows a basic ' shunt cont ro l led ' conver ter . Q l shunts the main t iming capaci tor , Cl9 and so shunts off some of its charging current and effects the operat ing frequency. If zero voltage is fed to

9V TO 12V + V e

Fig. 3.8

Analogue /digital converter (voltage), shunt type. With zero input voltage, f = 3.7 kHz, with maximum input voltage, f = 800 Hz

Ql base, Ql is cu t off, and the circuit opera tes at m a x i m u m frequency ( abou t 3.7 kHz) . When a +ve voltage is fed t o Ql base, the transistor is driven on , and the operat ing frequency falls.

A snag wi th this circuit is t ha t , as Q l is driven on , Q l collector voltage falls, and when it falls t o less than Vp, the circuit ceases t o opera te . The operat ing range is thus ra ther restr icted, to a b o u t 8 0 0 Hz m i n i m u m in this case.

The value of RA is chosen, by trial and error , to suit the cont ro l voltage in use, and usually has a value of a few hundred k i lohms at potent ia ls u p to abou t 10 V , and a few megohms at 100 V.

Fig. 3.9 shows a basic 'series cont ro l led ' converter . Here , the C\ charging current is control led almost entirely by Q l . When Q l is driven ha rd on (sa tura ted) b y a voltage applied to R4, the charging current is


l imited by Ru and the circuit opera tes at abou t 3.7 kHz . When zero

voltage is applied t o R4, Ql is cu t off, and Q charges via Rs, giving an

operat ing f requency of abou t 3 0 Hz . Between these two ex t r emes , the

Fig. 3.9

Analogue/digital converter (voltage), series type. With zero input voltage, f= 30 Hz. with maximum input voltage, i= 3.7 kHz

9V TO I2V + V e

Fig. 3.10

Improved version of Fig. 3.9

64 20 UN/JUNCTION TRANSISTOR PROJECTS

frequency can be smooth ly cont ro l led b y the voltage applied t o # 4 , and thus be the collector cur ren t of Q l . The value of R4 is found by trial and error , t o suit individual requi rements .

In the circuits of Figs. 3.8 and 3 .9 , Ql is cut off unt i l a forward voltage of abou t 6 5 0 m V is applied t o its base, so the opera t ing frequency is no t effected b y voltages less t han this . This snag can be overcome b y applying a s tanding bias to Ql base, as shown in Fig. 3 .10. This modif icat ion enables inpu t voltages right d o w n t o zero , or even reverse voltages, t o be used.

Relay t ime-delay circuits

The circuits in Fig. 3.11 enable t ime delays ranging from ab o u t 0.5 sec t o abou t 8 min t o be applied t o convent ional relays, i.e., there is a delay from the m o m e n t at which the supply is connec ted t o the

550kQ

+ V e (20V MAX.)

*r3 RLA

2

Di = GENERAL PURPOSE

SILICON DIODE

OV

Fig. 3.11a

Basic relay delay unit, giving operating delay of 0.5-50 sec if C\= 100 yF, and 3 sec-8 min if Q = 1,000 nF

m o m e n t at which the relay switches on . In Fig. 3.11a, one set of normal ly closed relay contac t s are wired in series wi th the +ve supply line. When the supply is first connec ted , it is fed t o the u . j . circuit via these con tac t s . After a delay de te rmined by the sett ing of Rx and the value of Ci, the u . j . fires and drives RLA o n . As RLA switches on , the supply t o the u . j . circuit is b roken b y the relay con tac t s and the +ve line is connec ted t o RLA via R4i holding the relay on . RLA mus t be a fast-acting low-voltage relay wi th a coil resistanceôf -tesTQian 150 SI. The supply line p o t e n t i a l _ m u s t - b e - a t r l e a s t 4 t imes the relay operat ing


R, 5 0 0 k Q /

22kQ<

Cl 100/iF

OR I .OOOMF

* 3 D2 • >470Q ( S I L I C O N ) '

Q I 2N2646

12V TO 18V + V e

R I O O Q

( S E E TEXT)

Dl ["XT J«LA_ 2N2926(o)

( a , ? ( & ,r^> (SIL ICON) VL̂ f C2

' lOOjuF

R L A

-OV

Fig. 3.11b Alternative relay delay unit, giving same delays as Fig. 3.11a

D2 ( S I L I C O N )

R L B I

9V TO 20V + V e

7 — O R L B

Fig. 3.11c Current economy version of Fig. 3.11a

voltage, and the value of R 4 mus t be chosen to keep the ' o n ' cur ren t within limits when the relay is fed from the +ve supply line.

A snag wi th the circuit of Fig. 3.1 l a is tha t the relay type must be carefully selected. This snag is overcome in the circuit of Fig. 3 .11b.

66 20 UNIJUNCTION TRANSISTOR PROJECTS Here , the relay is connec ted t o the collector of Q 2 , and is normal ly off. When the u . j . fires, a +ve pulse is fed f r o m / ? 4 t o the base of Q2 v iaZM, driving Q2 and RLA on , and rapidly charging C2. A t the e n d of the +ve pulse, the u . j . switches off and Dl is reverse biased, so C2 discharges in to the base of Q2, holding the relay on for abou t 100 msec . Thus , C2 is used as a pulse expander , and el iminates the need for fast-acting relays.

As soon as RLA s tarts t o close, the g round line t o the u . j . is b r o k e n via the relay con tac t s , bu t is still connec ted to Q2. Once RLA is fully closed, the supply is connec t ed directly across RLA, hold ing it on , a n d cut t ing Q2 ou t of circuit . RLA can be any t ype wi th a coil resistance greater t han 100 £2, and wi th a working voltage in the range 6-18 V.

In the t w o relay circuits considered so far, the relays lock on and consume cur ren t indefinitely, once they have been triggered initially. Fig. 3.11c shows an alternative version of Fig. 3.1 l a , in which an addi-t ional relay. RLB, is used, Here , t he +ve supply is connec t ed via t h e normal ly closed contac t s of RLA and the normal ly open contac t s of RLB. The RLB con tac t s are shun ted b y push b u t t o n switch .Si, and as soon as this is opera ted t he supply is connec ted t o the u . j . and to RLB; RLB instant ly switches on and its con tac t s close, keeping t h e +ve supply connec ted once .Si is released. After a pre-set t ime delay, the u . j . fires, driving RLA on and t hus breaking the +ve supply t o t h e u . j . and t o RLBy which switches off and t hus comple te ly breaks the supply t o the circuit . The o u t p u t of the un i t can be t aken f rom t h e spare RLB contac ts .

Staircase divider/generator

When fed wi th a series of cons tan t -wid th inpu t pulses, the circuit in Fig. 3 .12 gives a linear staircase o u t p u t waveform tha t has a repe t i t ion frequency equal to some sub-division of the inpu t f requency. Alter-natively, if the inpu t f requency is n o t cons tan t , the circuit ' coun t s ' the number of inpu t pulses, and gives an o u t p u t pulse only after a pre-determined n u m b e r have been coun ted . Thus , the circuit can be used as a pulse counte r , f requency divider, or step-voltage generator for use in transistor curve tracers, e tc .

In the absence of an i npu t pulse , Q l is cu t off and Q2 base is shor ted t o the +ve line via R3, so Q2 is cu t off also, and no charge cur rent flows in to C2. When a cons tan t -wid th +ve inpu t pulse is fed t o t he circuit via Ci , Ql and Q2 are driven on and C2 s tar ts t o charge via the collector cur ren t of Q2, which is wired in t he emi t te r follower m o d e and acts as a cons tan t current generator , wi th its col lector current


cont ro l led via R6. C2 charges linearly as long as Q2 is on , and since Q2

is on only for the fixed dura t ion of the inpu t pulse , the C2 voltage

increases b y only a fixed a m o u n t each t ime a pulse is appl ied. In the

absence of the pulse , there is n o discharge p a t h for C2, so the charge

voltage s tays on this capaci tor . T h e following inpu t pulse again increases

the C2 charge voltage b y a fixed a m o u n t , unt i l , after a p re -de te rmined

n u m b e r of pulses, the C2 voltage reaches the trigger po ten t i a l of Q 3 ,

and the u . j . fires, discharging C2 and re-starting the count ing cycle.

i2V+ve ( S T A B I L I S E D)

Fig. 3.12

Staircase divider/generator

If the inpu t pulses are applied at a cons tan t repet i t ion f requency, the signal across C2 is a linear staircase waveform, and an o u t p u t pulse is available across Rs every t ime the u . j . fires. If the i npu t f requency is no t cons t an t , t he staircase is non-l inear, b u t the R8 pulse again appears after a pre-de termined n u m b e r of i npu t pulses have been applied. Stable coun t or division rat ios from 1 u p to abou t 2 0 can be ob ta ined .

I t is i m p o r t a n t t o no t e tha t this circuit mus t be fed w i th cons tan t -wid th inpu t pulses if stable opera t ion is t o be ob ta ined , and t ha t the wid th of the pulses mus t be small relative t o the pulse repe t i t ion per iod. The value of C2 is de te rmined b y these cons idera t ions , and


Diode-pump coun te r

The circuit in Fig. 3 .13 also acts as a frequency divider or coun te r , b u t gives a non-linear staircase o u t p u t . I t has the advantage, however , tha t count ing is a lmost independen t of the shape of the inpu t waveform.

With no inpu t applied, Ql is cu t off and C 3 charges via R3i C2, and Dl; C2 and C 3 acts as a po ten t ia l divider, and a fixed fraction of the supply voltage appears across C3. When an input pulse is applied, Ql is driven to sa tura t ion and C2 is discharged via Ql and D2; C 3 is pre-vented from discharging by D l . When the pulse is removed again, C2

DIVISION RATIO,

9V TO 12V + V e

Fig. 3.13

Diode pump counter. N.B. Dl and D2 are general purpose germanium diodes

again charges via Dl and C3, and places ano ther fraction of the supply voltage on C3. Thus , at the end of each pulse, the C 3 voltage increases b y a fixed s tep , unt i l eventually the u . j . fires, discharges C3, and the coun t cycle starts over again. Pulse shape has virtually n o effect on circuit opera t ion .

The division r a t i o , / o u t/ / i n, is roughly equal to CjlC^+C^ The ra t io is, however , effected b y a number of variable factors , including operat ing frequency, so the values of these t w o c o m p o n e n t s are best found by trial and error . Once c o m p o n e n t values have been selected, the circuit

is best found by trial and error . Once a C2 value has been selected, the division rat io can be varied over a range of abou t 10 :1 via R6.


will give stable division over qui te a wide range of inpu t frequency

variat ion. Stable division rat ios u p to 10 :1 can be easily ob ta ined .

Synchronised frequency divider

The circuit in Fig. 3 .14 is useful in generat ing s tandard t iming wave-

forms or f requency s tandards . Positive pulses from a 100 kHz crystal

oscillator are fed, via Cu t o base 2 of Ql, and Rx is adjusted so tha t

the u . j . locks firmly to an operat ing frequency of 10 kHz , the 100 kHz

9V TO 12V+ve ( S T A B I L I S E D )

R 4 < / ? lOOkQ lOOkQ y £

470 Q < « 6 <

470 0 <

+ V e INPUT

FROM

100kHz CRYSTAL

OSCILLATOR

Ci i.ooopF

;22kO

c2 . i,ooopF'

22kQ<

Qi 2N2646

c3 l,000pF

ooi/ iF

Q2 2N2646

1kHz -0V

10kHz Fig. 3.14

Synchronised frequency divider, giving standard frequencies (and times) of 100 kHz (10 ixsec), 10 kHz (100 usee), and 1 kHz (1 msec)

signals acting as sync pulses. The 10 kHz signal from Ql emi t ter is fed t o Q2 via C3, and R4 is adjusted so tha t Q2 locks to an opera t ing frequency of 1 kHz . Thus , the circuit makes available s tandard fre-quencies (and t imes) of 100 kHz ( 1 0 jusec), 10 kHz ( 1 0 0 Msec), and 1 kHz (1 msec) . Stabil i ty is excellent if a zener stabilised supply line is used.

Division rat ios o the r than 10 can be ob ta ined b y adjusting Rx and R4. O u t p u t s can be taken , via a high impedance emi t te r follower buffer stage, from the emi t te r of each u . j . and from the crystal oscillator.

Wide-range square wave generators

The u . j . can be used as the basis of a whole range of different wave-form generators . Figs. 3.15a and b show h o w it can be used to generate square waves.

(a) Wide-range square wave generator (npn) C i , C2, and C3 are selected to suit frequency range required, (b) pnp version of the wide-range square wave generator

(*)

(b)

Fig. 3.15


In Fig. 3 .15a , Q2 and Q3 form an n p n bistable mul t iv ibra tor or

divide-by-two circuit . At the end of each u . j . cycle, the +ve pulse from

R4 is fed t o the emi t te rs of Q2 and Q3 and cause the mul t iv ibra tor t o

change s ta te . T w o cycles of the u . j . result in a single comple te cycle

of the mul t iv ibra tor , so the mul t iv ibra tor o u t p u t , taken from either

col lector , is a perfect square wave at half of the u . j . f requency. The

t w o collector signals are in ant i-phase.

Fig. 3 .15b shows the p n p version of the same circuit . In this case,

the circuit uses the —ve pulses from R3 t o trigger the bistable mul t i -

vibrator , bu t the two circuits are otherwise similar.

I t ' s impor t an t t o no t e t ha t in b o t h of these circuits C2 and C 3 are

of equal value, and have a value of approx imate ly Q / 1 0 0 , i.e., if

d = 0.1 JUF, C2 and C 3 = 0 .001 juF (= 1,000 p F ) . C2 and C 3 should,

however , have a m a x i m u m value of abou t 100 p F .

Bo th Fig. 3.15a and b will generate square waves over a 100:1

frequency range, using a single set of c o m p o n e n t values.

Variable f requency pulse genera tor

The circuit in Fig. 3 .16 generates a cons tan t -wid th pulse t h a t can

be varied in repet i t ion frequency over a 100:1 range. It m a y , for

9V TO 12V +ve

500kQ

2-2kO 1\-c 4

oV C i - C 2 = C4

Fig. 3.16

Variable frequency pulse generator


example , generate a pulse with a cons tant wid th of 500/xsec, at repeti-tion frequencies ranging from 10 Hz to 1 kHz . T h e actual pulse wid th can be adjusted, on any part icular range, over a 10:1 range, i.e., from 5 0 - 5 0 0 Msec.

The circuit is qui te simple. Q2 and Q3 are wired as a monos tab le or one-shot mul t ivibrator , wi th pulse wid th control led by Rg-Rw and C4, and the mul t iv ibrator is triggered by the +ve pulses fed from R4 t o Q3 base via C2 and Dl. Thus , repet i t ion frequency is contro l led by the u . j . and pulse wid th by the mul t iv ibrator .

Different sets of C\-C2-C4 values are needed for each range of opera t ion , bu t all three capaci tors are usually of equal value. The main poin t here is tha t the m a x i m u m period of the pulse mus t be less than the min imum period of the u . j . cycle, otherwise the pulse will no t be ended by the t ime a new trigger pulse arrives, and stable opera t ion will no t be obta ined.

Pulse o u t p u t s can be taken from ei ther col lector , the t w o o u t p u t s being in anti-phase.

Variable on/off- t ime pulse genera tor

The circuit in Fig. 3 .17 generates a series of pulses in which the on and off t imes are independent ly control led and can each be varied over a 100 :1 range.

The circuit is similar to tha t of Fig. 3.15a, Q2 and Q3 forming a bistable mult ivibrator tha t is triggered b y +ve pulses from R6. In the Fig. 3.17 circuit , however , t w o different C\ charging circuits (R\-R2 and R3-R4) are available, and the mul t iv ibrator opera tes d iode gates tha t select the charging circuit t o be used at any part icular m o m e n t .

Assume tha t , at the m o m e n t the supply is connec ted , Q2 is on and Q3 is off. Q2 collector is near ground volts , so D4 is forward biased and D3 is thus back-biased, so no charge current flows to d via R3-R4. Q3 collector is at near full +ve rail po ten t ia l , so D2 is back-biased; Dl is thus forward biased and Q charges via Rx-R2 on ly . At the end of this t iming cycle, the u . j . fires and triggers the mul t iv ibra tor , so Q2 switches off and Q3 switches on . D2 is n o w forward biased and D4 is back-biased, so Rx-R2 are cut out of circuit and C\ charges via R3-R4 only . At the end of this new cycle, the circuit again changes state , and the sequence starts over. Thus , the two switching per iods of the bistable, and thus the on and off t imes of the o u t p u t pulses, are individually control led.

C2 and C 3 are of equal value and = C i /100 , down to a m i n i m u m of


D2

-N-9V TO l2V+ê

C 2 = c 3 Ci I00

Fig. 3.17

Variable on/off-time pulse generator. With C\= 0.1 nF, individual on and off times are variable from 500 fisec-50 msec

100 p F . With Ci = 0.1 JUF, the on and off t imes can be individually

control led over the range 5 0 0 jtxsec to 50 msec.

Variable f requency/M-S ra t io genera tor

The circuit in Fig. 3 .18 generates a series of pulses in which b o t h the mark-space rat io and the f requency can be independen t ly varied over a wide range. If, for example , the M-S rat io is set at 9 : 1 , the opera t ing frequency can be varied from (say) 10 Hz to 1 kHz wi thou t any resulting change in M-S ra t io . Similarly, if the f requency is set at (say) 100 Hz , the M-S rat io can be varied over the range 1 :100 t o 100:1 wi thou t any resulting change in operat ing f requency. Both frequency and M-S rat io can be s imultaneously varied, w i t h o u t in te rac t ion . This t ype of generator is of ten used at the t ransmi t te r end of analogue dual-propor t ional radio cont ro l systems, such as 'Galloping Ghos t ' .

In Fig. 3 .18 , Q2 and Q3 form a Super-Alpha pair emi t t e r follower, and enable a saw-tooth o u t p u t t o be taken at low impedance from the


9V TO 12V + V e ( S T A B I L I S E D )

OV

Fig. 3.18

Variable frequency/M-S ratio generator. Q is selected for frequency range required

R6-RrR8 chain w i thou t effecting the operat ing frequency of Q l . This saw-tooth is then fed, via R9, t o the Schmi t t trigger formed by Q4 and Q5, and b y adjusting Rn the Schmi t t can be made to fire at different po in ts on the saw-tooth , and so generate different M-S rat io pulse signals at Q5 col lector . R6 and Rs enable the m a x i m u m and m i n i m u m M-S rat ios to be pre-set. F requency ranges can be selected via Ci, as in all u . j . circuits, and , in any given range, the frequency can be varied via Ri. Thus , Rn acts as the M-S rat io con t ro l , and Ri as the frequency con t ro l .

One-shot lamp/re lay driver

Fig. 3.19 shows the circuit of a one-shot lamp or relay driver. Here , the lamp or relay is normal ly off, b u t comes on as soon as push b u t t o n Si is opera ted , and then stays o n for a pre-set per iod t ha t can be adjusted from abou t 4 sec to 8 min . At the end of this per iod, the lamp or relay switches off and the circuit re-sets, ready for the nex t opera t ion of Sx.

Q2 and Q3 form a bistable mul t iv ibra tor , in which Q2 is normal ly

9V TO 12V +Ve

OV

Fig. 3.19 One-shot lamp/relay driver, giving 'on' times variable from 4 sec-8 min

D2

Variable on/off-time lamp flasher, giving

(on' and 'off times individually

variable from 4 sec-8 min (=16 min maximum total)

Fig. 3.20


Variable on/off- t ime lamp flasher

Finally, another sequential u . j . lamp or relay driving circuit is shown in Fig. 3 .20. Here , the on and off t imes of the lamp or relay can be individually varied over the approx imate range 4 sec to 8 min , giving a m a x i m u m possible cycle per iod of 16 min , and opera t ion is repeti t ive.

This circuit is simply a re-hash of Fig. 3 .17 , wi th the addi t ion of the o u t p u t transistor stage given in Fig. 3 .19 . The m a x i m u m o u t p u t current is again l imited to 1 A. The on t ime of the lamp or relay is control led by R3, and the off t ime is control led by R\.

on and Q3 is off. Thus , Q2 col lector is normal ly near g round volts,

so D2 is forward biased and Dl is back biased, and D l thus prevents

C\ f rom charging via R\-R2> Under this condi t ion , Q3 collector is at

near full +ve rail voltage, so no forward bias is applied t o Q4, and the

lamp (or relay) is off; (Rn-D3-RX2 form a poten t ia l divider, and ensure

tha t the small voltage at Q3 collector does no t turn Q4 on ) .

When start b u t t o n .Si is momenta r i ly opera ted , Q2 base is shor ted

to ground and the bistable changes s ta te . Q2 goes off, removing the

forward bias from D 2 , and Cx t hus starts charging via / ? r/ ? 2- D l , and

at the same t ime Q3 goes on and drives Q4 t o saturat ion via D3-Ri2, so the lamp switches on . Q t hen charges up via RrR2-Dl, and after a

pre-determined per iod the u . j . fires, and the +ve pulse from R4 is fed

t o Q2 base via C2 and D4\ this pulse turns Q2 back on , so the circuit

re-sets in its original condi t ion , wi th D2 forward biased and the lamp

off. The circuit mainta ins this s tate .unti l .Si is again opera ted .

Any lamp or relay wi th a peak operat ing current less than 1 A or so

can be used in this circuit . It should be remembered , however , tha t

lamps draw peak switch-on currents abou t 3 t imes greater than their

normal running currents . Alternative silicon transistors can be used in

the Q4 pos i t ion , if preferred.

C H A P T E R 4

15 SILICON CONTROLLED-RECTIFIER PROJECTS

The three types of semiconduc tor device tha t we have looked at so far have been developed primari ly for low power appl icat ions . New types of device have also been developed for use in high power switching circuits , however , and one of the mos t impor t an t of these is the Silicon Control led-Rectif ier , or SCR, which is also k n o w n as a Thyr i s tor .

The SCR uses the symbol shown in Fig. 4 .1a . No t e t h a t this symbol resembles tha t of a normal rectifier, b u t has an ext ra te rminal , k n o w n as the 'ga te ' . The SCR should , in fact, be regarded as a modif ied silicon rectifier, giving the following basic characteris t ics:

(1 ) Normal ly , wi th no bias appl ied t o the gate , the SCR is ' b locked ' , and acts , be tween the anode and the c a t h o d e , like an open circuit switch; it passes negligible current in e i ther d i rec t ion .

(2) When a suitable.+ve bias is fed t o the gate , the SCR acts like

a normal silicon rectifier, and conduc t s (be tween anode and ca thode ) in the forward di rec t ion, b u t b locks in the reverse

d i rec t ion .

(3 ) Once the SCR has tu rned on and is conduc t ing in the forward di rect ion, the gate loses con t ro l , and the SCR s tays on even though the gate bias m a y be removed. Thus , only a brief +ve gate pulse is needed t o t u r n o n the SCR.

(4 ) Once the SCR has t u rned on , it can only be t u r n e d off again by reducing its internal currents to zero . In a.c. circuits , turn-off t hus occurs automat ica l ly on the —ve half of each cycle. The SCR can not be t u rned off via the ga te .

78 15 SILICON CONTROLLED-RECTIFIER PROJECTS

In use, an external load is wired in series wi th the SCR, which is then opera ted as a switch. This m o d e of opera t ion enables the device to switch high power loads wi th high efficiency. Suppose , for example , tha t the SCR is wired t o a load in to which it is required to switch 3 A from a 4 0 0 V supply. With the SCR blocked-off only small leakage currents flow, so negligible power is dissipated in the circuit , b u t when the SCR is switched on it passes the full 3 A th rough itself and the load; only abou t 2 V are developed across the SCR w h e n it is on , however , so only 6 W are developed in the SCR, while nearly 1,200 W are developed in the external load.

A major advantage of the SCR is tha t it offers a high power gain be tween the gate and external load. Typical ly , a m a x i m u m gate current of 20 m A at 2 V is needed to trigger a 3 A SCR, so, in the above example , the overall power gain is 3 0 , 0 0 0 .

SCRs can be used to replace convent ional relays. T h e y have no moving par ts t o wear ou t or arc , are silent in opera t ion , can opera te at high speeds, and are no t adversely affected by severe mechanical vibrat ion or by high 'G ' forces.

SCR theo ry

The SCR is a four-layer n p n p device. Fig. 4 .1b shows a simplified diagram of its s t ruc ture , while Fig. 4 .1c shows an al ternative represen-ta t ion . F r o m this second diagram it can be seen tha t the SCR can be roughly s imulated by an n p n and p n p transistor connec ted as shown in Fig. 4 . I d , and tha t SCR opera t ion can thus be expla ined in tran-sistor te rms. Rx and R2 represent the semiconduc tor resistance be tween gate and c a t h o d e ; circuit act ion is explained as follows:

When the supply is first connec ted , and wi th zero bias on the gate, Ql base is shor ted t o the ca thode via Ri and R2, so Ql is cu t off and passes no collector current . Q2 base current is derived from Ql col lector , so Q2 is also cut off under this condi t ion , and zero cur ren t flows be tween anode and ca thode .

When, on the o ther h a n d , a +ve bias is applied t o the gate , Ql is driven on . The resulting collector current of Ql feeds direct ly in to the base of Q2, and drives tha t transistor on also. The result ing collector current of Q2 feeds back in to the base of Ql, t hus comple t ing a positive feedback loop . Regenerative act ion takes place, and b o t h tran-sistors are driven to sa tura t ion, and a heavy current flows be tween anode and ca thode . Once regenerat ion starts , it con t inues indepen-dent ly of the applied gate voltage, and once b o t h transistors are sa tura ted they can only be tu rned off again by momenta r i ly reducing

A N O DE (+Ve)

0

G A TE — O

C A T H O DE ( - V e)

A N O DE

G A TE

C A T H O DE

(b)

Fig. 4.1

(a) Symbol for silicon controlled-rectifier, or thyristor. (b) Simplified diagram of SCR semiconductor structure, (c) Alternative representation of SCR semi-conductor structure, (d) Simple transistor equivalent of SCR, derived from

Fig. 4.1c. (e) Connections of SCR using stud type of construction

( c ) (d)

A N O DE ANODE (+Ve)

Q2 ( p n p )

Qi ( n p n )

C A T H O DE

CATHODE (~Ve)

, C A T H O DE X ( L O NG T E R M I N A L)

G A TE ( S H O RT T E R M I N A L)

A N O DE ( S T U D)

(*)


the circuit cur rents t o zero , i.e., by short ing the anode to ca thode or b y breaking the supply connec t ions . T h e y can not be t u rned off b y short ing the gate t o ca thode , since Rx prevents Ql base short ing t o ca thode , and Ql collector current con t inues t o be fed directly in to Ql base.

SCR parameters

Seven basic parameters are used in defining SCR characterist ics, as follows:

Reverse voltage, max (Vr). As in the case of a convent ional rectifier, this is the m a x i m u m peak voltage tha t can be safely applied t o the device in the reverse direct ion w i thou t incurring a risk of destructive b reakdown . Note tha t this parameter is expressed in t e rms o f peak voltage, whereas mos t a.c. supply voltages are expressed in r .m.s . rating. The peak of an a.c. voltage is roughly 1.4 t imes its r .m.s. value, so, if the SCR is t o be opera ted from an a.c. supply, it should have a Vr rating at least 1.4 t imes tha t of the r .m.s. supply^ voltage. Forward voltage, max (Vf). This is the peak forward voltage tha t the SCR can safely handle when the device is b locked , and is usually of the same value as Vr. In a.c. circuits, Vf is established in the same way a s F r. Forward current, max (If). This is the m a x i m u m forward current tha t the device can safely carry be tween anode and ca thode , and m a y be expressed in t e rms of ei ther r .m.s . or average value. The m i n i m u m If rating needed for a specific appl icat ion can be simply calculated, as follows:

supply voltage m i n i m u m If rating = .

resistance of load

or, if the power rat ing of the load is k n o w n :

power of load m i n i m u m If rat ing = .

supply voltage

Thus , if an SCR is required t o cont ro l a m a x i m u m load of 1 kW from a 2 3 0 V a.c. supply, the minimum If rat ing = 1 ,000/230 = 4 .35 A r > r r u s. When making these calculat ions it should be borne in


m i n d tha t electric fires and lamps m a y , at the m o m e n t of switch-on, dissipate three t imes their no rmal running power , while electric drills m a y dissipate several t imes their no rmal running power w h e n stalled or heavily loaded .

Gate voltage, max to trigger (Vg). This is the m a x i m u m forward gate bias voltage needed t o trigger the SCR, and typical ly has a value of 1-2 V. Gate current, max to trigger (Ig). The m a x i m u m gate cur ren t , Ig, required t o trigger the SCR typical ly has a value be tween 1 and 3 0 m A . The gate- to-cathode j u n c t i o n acts like a no rmal silicon d iode , and presents a very low impedance when forward biased, so in pract ical circuits the gate cur ren t should be l imited to some safe value above Ig via a series resistor, which should have a m a x i m u m value selected on the basis of:

gate voltage m a x i m u m resistance = .

k

The m a x i m u m permissible gate cur ren t of the SCR is usually l imited t o a b o u t a t e n t h of If, so the m i n i m u m value of the gate resistor can be calculated f rom:

10 X gate voltage m i n i m u m resistance .

'f

The final value of gate resistor should rest be tween these two ex t remes .

Holding current, max (Inm). I t was m e n t i o n e d earlier tha t , t o tu rn off an SCR, its cur ren ts mus t be reduced to zero . In pract ice , however , it is usually possible t o t u rn off the device by simply reducing the currents t o a fairly low value, typically be tween 1 and 50 m A . Conse-quen t ly , the SCR m a y n o t ho ld on correct ly if opera ted wi th t o o low an anode cur ren t , and a m i n i m u m hold ing cur ren t , In, is therefore specified in manufac tu re r s data sheets . I nm is the m a x i m u m value of In occuring in a p roduc t i on spread of SCRs, and its pract ical effects are t o l imit the m a x i m u m resistive values of anode load t h a t can be reliably used.

Peak on-voltage drop at If (Vfm). This is the m a x i m u m forward voltage d rop of the SCR when opera t ing a t m a x i m u m cur ren t rat ing, and typical ly has a value of a b o u t 2 V.


Basic d.c. on/off circuits

r i g . 4 .2 shows a basic SCR d.c. on/off circuit , driving a 12 V, 500 m A lamp load. Any type of load drawing a m a x i m u m current less than 3 A can, in fact, be used here , b u t the SCR may need to be m o u n t e d on a heat sink at currents above 1 A or so. If an inductive load is used, it

Fig. 4.2

r 1 - _ 1 6U>2

<

> 1 k Q

( b )

(a) Basic SCR d.c. on /off circuit

(b) Alternative on/off circuit

In both circuits, SCR7 is any SCR with a Vr of 50 p.i.v. and an If of 3 A, or

greater

must be shunted by a reverse connec ted d iode , wi th a cur ren t rating equal to tha t of the load, as shown d o t t e d in the diagram, to prevent high back e.m.f.s damaging the circuit .

The SCR and lamp are t u rned on by briefly connect ing a +ve gate voltage via push-bu t ton Sv The circuit is self-latching, and the gate

S,

This completes the descript ion of the general characterist ics of the SCR, and we can now go on to look at 15 practical circuits of interest to the exper imenter . All of these circuits are in tended for low-voltage work , and have been designed to work wi th any SCR w i th an If of 3 A r. m. s. and a Vf of 50 V, so any SCR meet ing or exceeding these requi rements can be used. Most SCRs use a s tud type of cons t ruc t ion , and Fig. 4 .1e shows the usual connec t ions .


bias only has t o be applied for a couple of microseconds t o ensure full turn-on. S\ can be omi t t ed if preferred, and the turn-on gate pulse can be applied via a t ransistor pulse genera tor . The SCR is t u rned off by momenta r i ly breaking the supply connec t ions via 5 2; the SCR takes a few tens of microseconds t o tu rn off fully.

An alternative m e t h o d of turning off the SCR is shown in Fig. 4 .2b . Here , the SCR anode is shor ted t o the ca thode when S2 is momen ta r i l y opera ted , so the SCR cur rents are briefly reduced to zero and switch-off again occurs .

A variation of this switch-off t heme is shown in Fig. 4 . 3 . Here , wi th the SCR on , Cx charges via R3. When fully charged, the SCR -anode end of Cx is 2 V above ground potent ia l , and the R3 end is at full +ve rail

voltage, giving a capaci tor charge of 10 V in this part icular case. Now, when S2 is opera ted , the +ve end of C\ is c lamped to g round , and the capaci tor charge therefore forces the anode of the SCR t o m o m e n -tarily swing to abou t 10 V —ve, the reby reverse biasing the SCR and thus causing it t o cut off. The capaci tor charge leaks away rapidly under this condi t ion , b u t only has to ho ld the SCR anode negative for a few h u n d r e d t h s of a mill isecond to ensure comple te switch off. Note tha t , if S2 is held down after the charge has leaked away, the capaci tor then starts t o charge in the reverse direct ion via LPU so Cx mus t be a reversible type . The value of C\ is no t critical.

Fig. 4 .4 shows a modif icat ion of Fig. 4 . 3 , using an addi t ional SCR to enable switch-off t o be ob ta ined via a low-current gate pulse . SCRl

S, (ON)

12V +Ve

II ( R E V E R S I B L E)

oV

Fig. 4.3

Capacitor-discharge turn-off circuit


i2V+Ve

Rl 220O

Fig. 4.4

Dual- SCR on/off circuit (bistable)

and SCRl work as a flip-flop or bistable a r rangement , in which SCRl is

on when SCRl is off, and vice versa.

Suppose tha t SCRl is off and SCRl is on . Cx charges via LPX, and

the SCRl -anode end of the capaci tor goes to +ve rail po ten t i a l . When

a +ve gate pulse is applied t o SCRl, SCRl and the l amp go o n ; the

SCRl -anode end of Cx is pul led towards g round po ten t ia l , so SCRl

anode is driven momenta r i ly - v e and SCRl tu rns off. Cx t h e n charges

in the reverse di rect ion, via R3, and the R3-end of Cx eventual ly reaches

the +ve supply rail po ten t ia l . Thus , when a +ve gate pulse is applied to

SCRl, SCRl switches on and pulls the R3 end of Cx t o near g round

poten t ia l and so drives SCRl anode - v e , and the reby causes SCRl t o

switch off. The cycle then repeats ad infinitum. In this circuit , SCRl

only has t o carry a current of Fsuppry/R3-

Automa t i c turn-off circuit

Fig. 4.5 shows a deve lopment of Fig. 4 .4 , in which , once the lamp has

been tu rned on via Si, turn-off occurs automat ica l ly after a pre-set

per iod. The turn-off delay is de te rmined by a u . j . t imer circuit , and

can be varied from a b o u t 8 - 8 0 sec v i a / ?7. Normal ly , SCRl and the lamp are off, and SCRl is on and its


12V +Ve

-oV

Fig. 4.5

Automatic turn-off circuit, giving switch-off delay of 8-80 sec

anode is at near ground po ten t ia l . The u . j . circuit is therefore inoperat ive. When a +ve trigger pulse is applied to SCR 1, SCR 1 and the l amp go on and SCR2 goes off. As SCR2 switches off, its anode rises t owards the +ve rail voltage, and the u . j . circuit t hen starts a t iming cycle . At the end of a per iod de te rmined by the set t ing of R7, the u . j . fires and triggers SCR2 on via a +ve pulse from Rs, and SCR2 triggers .SCR 1 off via C\. The circuit is t hus re-set and ready for the nex t ope ra t ion of Sx.

Note tha t , when the supply is first connec t ed , b o t h SCRs are off, so there is a delay in which the u . j . goes th rough one comple te cycle before the circuit takes u p the above bistable s ta te .

Single-but ton on/off circuit

Fig. 4 .6 shows h o w the SCR bistable can be conver ted for single b u t t o n opera t ion , so tha t one push of the switch turns the lamp on and the following push tu rns it off again. In this case, SCR2 has a large anode load, so its on cur ren t is lower than its m i n i m u m hold-on r equ i r emen t ; / SCR2 is thus unable t o la tch on .

Assume tha t b o t h SCRs are off; b o t h anodes are near +ve rail voltage so zero charge is on C\. When .Si is ope ra ted , SCRl and LP\ are driven on via a brief +ve pulse from C3, and .SCR 2 is momen ta r i l y

Si . (ON)


12V 500mA

( R E V E R S I B L E )

•2

R. I2k0

SCRl (50P.I.V., 3 A )

o-i/iF

* II—

o-i/jF HI—

R2

SCR2 ( 5 0 P . I . V . , 3 A )

I k Q

-OV

Fig. 4 . 6

Single-button on/off circuit

the o ther hand , is briefly driven on , and thus applies a reverse voltage t o SCRl via Ci, so SCRl and LPi tu rn off. A t t he end of this pulse, SCRl again tu rns off th rough lack of hold-on cur ren t , and the circuit is ready for the nex t opera t ion of S\.

The circuit changes state each t ime a +ve pulse is applied via .Si. No te therefore , tha t opera t ion may become erratic if a noisy push -bu t ton is used. The possibility of erratic opera t ion can be overcome by applying the trigger pulses via a one-shot transistor mul t iv ibrator .

Repet i t ive switching circuits

The circuit of Fig. 4 .6 can be made to operate as a free-running or repetitive switch by feeding it wi th the trigger pulses from a u . j . pulse generator . Fig. 4 .7 shows a practical version of a lamp flasher using this principle. This circuit gives equal on and off t imes of the l amp , and the repet i t ion rate can be varied be tween abou t 25 and 150 flashes/min via R5

A different type of flasher, giving independent ly variable on and off t imes, is shown in Fig. 4 . 8 ; the on and off t imes can be varied from

driven on via a pulse from C2. At the end of this brief pulse, SCRl

turns off again th rough lack of holding cur ren t , b u t SCR 1 stays on . Ci then charges via R u and SCRl anode goes to +ve rail po ten t ia l . The nex t t ime .Si is opera ted , +ve pulses are again fed t o b o t h SCRs, b u t that on SCRl gate has no effect, since SCRl is already on . SCRl, on

12V+Ve

12V +Ve

Fig. 4.7

Repetitive switching circuit, giving 25-150 flashes I min

12V+Ve

Fig. 4.8

Repetitive switching circuit, giving independently variable on/off times of 0.2-1.2 sec. D1-D6 are general purpose silicon diodes


Basic a.c. on /of f circuits

Fig. 4 .9 shows a basic a.c. on /of f circuit using a 12.6 V supply from a t ransformer. With .Si open , the SCR is off, so n o cur ren t flows in the l amp . When .Si is closed, the .SCR gate is forward biased o n +ve half cycles, so the SCR conduc t s and the l amp comes on . Dl prevents reverse bias being applied t o t he gate . The SCR t u rns off au tomat ica l ly on the —ve halves of each cycle , so the un i t is n o t self-latching, and the l amp goes off again when .Sx is opened . N o t e t ha t the .SCR only conduc t s on +ve half cycles, and so acts as a half-wave rectifier, and the l amp thus burns at only half bril l iance.

Fig. 4 . 10 shows a full-wave on/off circuit . In this case, the a.c. supply is conver ted t o rough d.c. via t he Dl-DA bridge rectifier, and this d.c. is t hen applied t o t he .SCR. With .Si o p e n , the .SCR is off, so n o current flows th rough the bridge via LPX. When .Si is closed, the .SCR is biased on , so cur ren t flows th rough LPX via the bridge and SCR. The SCR voltage falls t o zero once on every half cycle , so the circuit is n o t

approx . 0 .2 t o 1.2 sec. No te t ha t this is a t rue bistable circuit , t he anode loads of b o t h SCRs being low enough for self-latching.

When the supply is first connec ted , b o t h SCRs are off, and the u . j . t imer is free-running via t h e R9-RX(fD4 and RirRu-D6 n e t w o r k s ; Dl and D2 are reverse biased via R5 and R6, however , and prevent the trigger pulses reaching the SCR gates, so the u . j . has n o pract ical effect at this stage. T o start t he circuit working , Sx mus t be momen ta r i l y opera ted .

When .Si is opera ted , a trigger pulse is fed t o SCR 1 via R4, and SCR 1 and LPX la tch on . .SCR 1 anode thus goes t o near-ground po ten t i a l , and the reverse bias of D2 is r emoved ; at the same t ime ,Z)3 is forward biased and DA is reverse biased so the R9-Ri0 n e t w o r k is effectively cu t o u t of the u . j . t imer circui t , and the u . j . charges yiaRn-Ri2 and D6. At the end of this t iming cycle , the u . j . fires and tu rns o n .SCR2 via D2 and C3; as S C R 2 tu rns o n , it t u rns .SCRl and LPX off via Cx. This p u t s a reverse bias on D2 b u t removes the reverse bias of D l ; at the same t ime , D5 is forward biased and D6 is reverse biased, so R n and R12 are effectively cu t o u t of t he u . j . t imer circuit and D3 is reverse biased and D4 is forward biased, so the u . j . n o w charges via R9 and R10. A t the end of this t iming per iod , the u . j . again fires and triggers .SCRl and LPX on via Dl and C2. As .SCRl goes on , it triggers .SCR2 off via Ci, and the circuit biasing is again changed so t h a t the u . j , charges via R n and R12. The process t h e n repeats ad infinitum.


l 2 - 6 V d . c

( F R OM

T R A N S F O R M E R)

Fig. 4.9

Basic a. c. on/off circuit (Half-wave)

LP, I2V

5 0 0 m A

l 2 -6Vd.c .

Fig. 4.10

Full-wave on/off circuit, controlling an a.c. load. D1-D4 are 50 p.i.v., 3 A silicon rectifiers

self-latching. No te t ha t , in this circuit , LP\ is on the a.c. side of the bridge, while the SCR is on the d.c. side, so the design is in fact used t o cont ro l an a.c. load.

The circuit of Fig. 4 .11 is similar to tha t of Fig. 4 . 10 , b u t in this case the l amp load is wired in series wi th the SCR a n o d e , so this design is used to con t ro l a d.c. load. The circuit is n o t self-latching.

3A FUSE

Fig. 4.11

Alternative full-wave on/off circuit, controlling a d.c. load. D1-D4 are 50 p.lv., 3 A silicon rectifiers

3A FUSE

Fig. 4.12

Light-operated switch (non-latching) D7-D4 are 50 p.i.v., 3 A silicon rectifiers, D5 is a general purpose silicon diode, and LDR is any cadmium sulphide

photocell with a face diameter greater than 0.25 in


Fig. 4 .12 shows h o w Fig. 4 .11 can be conver ted for use as a light-opera ted switch. Here , the SCR and l amp are fed wi th rough d.c. from the bridge rectifier, and this is t hen s m o o t h e d b y C\ b u t prevented from reaching the SCR by D 5 . The s m o o t h e d d.c. is t h e n stabilised at 9 V at 2 0 m A via Rx and Z D 1 , and is used t o power t he Ql t ransistor c i rcui t ry . Q l is wired as an emi t te r follower, wi th base-bias provided via po ten t ia l divider RA and LDR. Under bright cond i t ions , the LDR resistance is low, so the voltage on Ql emi t te r is n o t sufficient t o trigger the SCR, and LP\ is off. Under dark condi t ions , the LDR resistance is high, so the voltage on Q l emi t te r is sufficient t o trigger t he SCR, and LPX comes on . Since the SCR is fed wi th rough d.c. the circuit is n o t self-latching, and the l amp tu rns off when the gate bias is removed.

Fig. 4 .13 shows h o w Fig. 4 .12 can be modif ied for self-latching opera t ion . Here , when the SCR is on , it passes the rough current of

3A FUSE

Fig. 4.13

Modification of Fig. 4.12 giving self-latching operation D1-D4 are 50 p.iv., 3 A silicon rectifiers

the l amp plus a low b u t smoo thed ' s t andby ' current from R5. The s t andby cur ren t , however , is greater than the SCRs m i n i m u m holding cur ren t , so, once the SCR has been driven on , the gate loses con t ro l , and the lamp stays on even t h o u g h the gate bias is removed . The SCR

Light-operated SCR switches


can only be tu rned off by removing the gate bias and disconnect ing the holding current by opera t ing ' reset ' b u t t o n Sv

The circuits of Figs. 4 .12 and 4 .13 can be modif ied for opera t ion by sound, hea t , e tc . , by simply replacing Ql w i th al ternative de tec tor circui try.

Variable-power circuits

Fig. 4 .14a shows h o w the SCR can be used, in conjunct ion wi th a u . j . pulse generator , as a variable power uni t feeding a d.c. load. The circuit

3A F U SE

O)

( b )

M I N I M UM P O W ER

H A LF P O W ER

M A X I M UM P O W ER

VOLTAGE A C R O SS

ZDl

V O L T A GE B E T W E EN

S C R l G A T E

A ND C A T H O DE

VOLTAGE A C R O SS

SCRl

VOLTAGE A C R O SS

LOAD [LP, ]

Fig. 4.14

(a) Variable-power unit, feeding a d.c. load. D1-D4 are 50 p.i.v., 3 A silicon rectifiers, (b) Wave-forms of Fig. 4.13a under alternative operating conditions


waveforms are shown in Fig. 4 .14b . Here , the voltage across Z D 1 , and thus across the u . j . circuit , is rough d.c. cl ipped at 9 V , so the power t o the generator is automat ical ly connec ted and disconnected in sym-pa thy wi th the power line f requency. At the start of each new half cycle, the u . j . circuit s tarts a t iming cycle, and , after a delay de te rmined

LP, 12V

500mA

( b )

VOLTAGE A C R O SS

ZDl

VOLTAGE B E T W E EN

SCR I GATE

A ND C A T H O DE

VOLTAGE A C R O SS

SCRl

VOLTAGE A C R O SS

LOAD (LP,)

M I N I M UM P O W ER

H A LF P O W ER

M A X I M UM POWER

-OV

Fig. 4 15

(a) Variable-power unit, feeding an a.c. load. D1-D4 are 50 p.iv., 50 silicon rectifiers, (b) Wave-forms of Fig. 4.1a, under alternative operating conditions

(a)


by Rs, generates a +ve pulse and fires SCRl. Thus , the u . j . gives delayed and variable firing of the SCR.

When the uni t is set for m i n i m u m o u t p u t power (in LPi), the u . j . gives m a x i m u m delay, so the SCR fires towards the very end of each half cycle, so only a small par t of the to ta l available power is fed t o the load. At half m a x i m u m power , the u . j . fires the SCR half way th rough each half cycle, so half of the m a x i m u m available power is fed t o the load. A t m a x i m u m power , the u . j . triggers the SCR t owards the start of each half cycle, so almost the full available power is developed in the load. The d.c. power t o the load is thus fully variable via Rs, and, since the SCR is used as a switch, the system is highly efficient as a variable power source.

Finally, Fig. 4 .15a shows h o w a similar circuit can be used t o con t ro l an a.c. power load. This circuit is identical wi th tha t of Fig. 4 .14a , except tha t the load is placed on the a.c. side of the bridge rectifier. A slightly different set of circuit waveforms are generated in this case, however , as shown in Fig. 4 . 1 5 b .

In this case, as soon as the u . j . triggers the SCRt a lmost the full supply voltage is developed across the load, so the voltages across SCRl and ZDl fall t o near-ground po ten t ia l . This is of no impor t ance , however , since the SCR has already fired, and thus stays locked-on unti l its anode falls t o full g round potent ia l at the end of each half cycle. The power t o the load can thus be smooth ly varied from near-zero t o m a x i m u m v i a / ?5, as in the case of the d.c. circuit .

C H A P T E R 5

30 COSMOS DIGITAL I.C. PROJECTS

The actual semiconduc to r ' hea r t ' of a t ransis tor or f.e.t. is physically very small . So small, in fact , t h a t i t can be clearly seen only wi th the aid of a mic roscope . The physical size of a comple te t ransis tor or f.e.t., however , is d ic ta ted by the practical need of a h u m a n opera to r t o comfor table handle t he device, and t o m e e t this need the ' hea r t ' is usually shrouded in a relatively massive case, and is connec ted t o equally massive external leads . Thus , a l though the final t ransis tor is qui te small b y m o s t s tandards , t he relative size of the ' hea r t ' t o the case compares , by analogy, t o tha t of an orange t o a househo ld garbage can . There is in fact enough r o o m in the average sized t ransis tor case t o h o l d scores of semiconduc to r 'hear t s ' .

The same is t rue of resistors: mos t of the volume of a convent ional resistor is t aken u p by a ' b o d y ' or former , on the outs ide of which is a th in film of carbon or oxide which forms the t rue resistance. The volume of resistance mater ia l is very small relative t o t ha t of the b o d y .

I t follows from the above t h a t , if t he need t o hand le individual t ransistors and resistors can be e l iminated , i t should be possible t o p roduce a comple te circui t , wi th m a n y ' t ransis tors ' and ' resistors ' , in a single case t he size of a convent ional t ransis tor . Only a few externa l connec t ions , such as power supply and i n p u t and o u t p u t leads , m a y need t o be m a d e t o such a circui t . T h u s , the idea seems feasible, and in the past decade or so the technology has indeed been developed t o p u t the idea i n t o prac t ice , and i t is n o w possible t o integrate m a n y t ransis tors , f.e.t.s, d iodes , zener d iodes , and resistors and small capaci tors i n to a single circuit package. The devices e m b o d y i n g the idea are k n o w n as in tegra ted circui ts , or i.c.s.

96 30 COSMOS DIGITAL I.C. PROJECTS

Most pract ical in tegra ted circuits can be clearly fitted i n t o one or o ther of t w o classes. They are ei ther ' l inear ' types , which are in tended t o amplify analogue signals, or they are 'digital ' t ypes , which are in t ended t o process l o g i c ' signals and ac t pure ly in the non-linear or switching m o d e . A n u m b e r of alternative logic technologies are used in digital in tegra ted circui ts , and one of the mos t interest ing of these is the so-called COSMOS technology , which is briefly described be low.

Unders tanding COSMOS

When discussing digital or logic c i rcui t ry , i n p u t and o u t p u t signals are generally considered t o have only t w o possible s ta tes : They are ei ther a t t h e ' low ' ( ze ro vol ts) or 'logic 0 ' level, or t h e y are a t t he 'h igh ' (full supply voltage) or 'logic 1 ' level.

The mos t basic logic e lement used in digital circuitry is the simple pulse inverter or N O T ga te . Fig. 5.1 shows a simple resistor-transistor-logic ( R T L ) inverter circui t . When a low or 'logic 0 ' i npu t is applied t o t h e circuit Qx is cu t off, so the o u t p u t of the circuit is high or at the 'logic 1' level. When a high or 'logic 1 ' i n p u t is applied t o the circuit Qi is driven to sa tu ra t ion , so the o u t p u t goes t o near-zero volts ( the 'logic 0 ' level). T h u s , the circuit acts as a simple b u t useful pulse or digital inver ter . T w o major deficiencies of the circuit are t h a t i t draws a fairly high cur ren t (several m A ) from the power supply when its o u t p u t is in the 'logic 0 ' s t a t e , and i t has an i n p u t impedance of only a thousand ohms or so .

Fig. 5.2a shows the basic COSMOS version of the digital inverter or N O T gate. Here , a complemen ta ry pair of metal-oxide silicon field-effect t ransistors (one p-channel t ype and one n-channel t ype ) are wired in series be tween the power supply l ines, b u t have their gate terminals t ied toge ther and used as a single c o m m o n signal-input po in t .

Fig. 5.1

Simple R TL inverter or NOT circuit


5 V t o 15V . v e

Fig. 5.2a

Basic COSMOS digital inverter or NOT gate

5 V t o 1 5 V . v e

:u )on

5 V t o 1 5 V * v e

10 000MA

O V O V

(b) (C) Fig. 5.2b and c

Equivalent circuit of COSMOS NOT gate with (b) logic 0 input, and (c) logic 1 input

Basic characterist ics of t he t w o f.e.t.s used in the circuit are t h a t t h e y have very high i n p u t impedances ( typical ly a few mill ion megohms) and tha t their drain-to-source pa ths act as variable resistances t h a t are cont ro l led by their source-to-gate voltages. Typical ly , the drain- to-source p a t h presents a resistance in the order of t housands of megohms when the source-to-gate voltage is z e r o , and presents a resistance of only a few h u n d r e d ohms when the source-to-gate voltage is in the high or l og i c 1' s ta te .

n - C H A N N E L

p - C H A N N E L


Fig. 5.2b and 5.2c respectively show the effective equivalent circuit of the COSMOS inverter when 'logic 0 ' and 'logic 1' inputs are appl ied. Thus , when the inpu t is at 'logic 0 ' the lower f.e.t. is virtually open circuit and the uppe r f.e.t. presents a resistance of only 40012, so the o u t p u t is in the 'logic 1' s ta te . When the i n p u t is at 'logic 1' the upper f.e.t. is virtually open circuit and the lower f.e.t. presents a resistance of only 40012, so the o u t p u t is in the 'logic 0 ' s t a te . N o t e tha t in each case one or o ther of the f.e.t.s is virtually open circuit , so the inverter draws negligible cur ren t from the supply , b u t tha t in each case the o u t p u t of the circuit is t ied t o ei ther the zero or the positive supply rail by a resistor of only 40012, so the circuit has a low effective o u t p u t impedance and good cur ren t drive capabili t ies. This basic COSMOS digital circuit thus has m a n y advantages over its R T L equivalent .

No te tha t the te rm COSMOS or COS/MOS is derived from the tit le C o m p l e m e n t a r y .Symmetry Metal Oxide .Silicon, which describes the semiconduc tor technology used in this part icular logic family.

T h e C D 4 0 0 1 quad 2-input N O R gate

The basic COSMOS technology described above can be used in m a n y applicat ions in addi t ion t o the simple digital inverter already m e n t i o n e d , and a vast range of COSMOS digital i.c.s are n o w available. One of the mos t useful and least expensive of these is the C D 4 0 0 1 , and conta ins four independen t 2-input N O R gates. Fig. 5.3 shows the logic diagram and pin connec t ions of this i.e., and Fig. 5.4 shows the basic circuit t ha t makes u p each of the four gates t ha t is con ta ined in the i.e. The ac t ion of each gate is such t ha t its o u t p u t goes t o the low or 'logic 0 ' s tate if e i ther inpu t is high or in the 'logic 1 ' s t a t e , and goes high only when b o t h inpu ts are in the low or 'logic 0 ' s ta te . Each gate can be m a d e t o act as a simple inverter by ty ing its t w o i n p u t terminals together .

In prac t ice , each one of the eight i n p u t terminals of this i .e. is provided wi th a built-in 'ant i -s tat ic ' p ro tec t ion circui t , compris ing three diodes and one resistor, so the comple te i.e. houses the equivalent of 16 f.e.t.s, 8 resistors and 24 diodes . The i.e. is except ional ly versatile, and can readily be made t o funct ion as any one of a variety of gate or logic circui ts , or as an astable or monos tab le mul t iv ibrator , e t c . Thi r ty useful applicat ions of the CD4001 are shown in following sect ions of this chapter .

The CD4001 i .e. can be opera ted from any d.c . power supply in the range 3V to 18V. When handl ing the device, care should be t aken t o ensure tha t large static voltages are n o t applied t o its i n p u t terminals .


V o D ( . v e )

( T O P V I E W)

Fig. 5.3

Logic diagram and pin connections of the CD4001 quad 2-input NOR gate

I N P U T A*

V ( . v t )

P

I N P U T Bi

• O U T

Fig. 5.4

Circuit of each of the four 2-input gates of the CD4001

In par t icular , soldering i rons mus t be proper ly ea r thed or g rounded when soldering t o t h e i .e. te rminals . When using t h e i .e. , n o t e t h a t all unused i n p u t pins mus t be t ied t o g round or t o the positive supply rail. The pins m u s t unde r n o c i rcumstances be al lowed t o ' f loat ' . F inal ly , no t e when test ing practical C D 4 0 0 1 circuits t ha t the i .e. draws only n a n o a m p s of quiescent cur ren t from its power supplies, and these currents are t o o small t o be measured wi th a no rma l mu l t ime te r .


C D 4 0 0 1 pulse inverter and gate circuits

Each of the four gates of the CD4001 i.e. can be used as a simple pulse inverter or invert ing pulse amplifier by merely shor t ing its t w o i n p u t terminals toge ther , as shown in Fig. 5.5a, which shows jus t one of the four gates so connec ted . No te t ha t any n u m b e r of the four gates of the CD4001 can s imul taneously be used in this w a y , and t h a t all the inpu ts of the unused gates of the i .e. mus t be t ied t o g round .

The CD4001 can be m a d e t o act as a non-invert ing pulse amplifier or buffer by wiring t w o of its gates as pulse inverters and wiring the t w o inverters in series, as shown in Fig. 5 .5b . No te t ha t t w o of these non-invert ing amplifiers can be made from each CD4001 package .

Fig. 5.5a Fig. 5.5b

Simple pulse amplifier/inverter Non-inverting pulse amplifier

The CD4001 i.e. can be used in a variety of pulse gate appl icat ions. Pulse gates can be simply described as pulse amplifiers t h a t can be 'enabled ' and 'disabled ' , or t u rned on and off, via electronic c o m m a n d signals. One of the simplest circuits of this t y p e is the pulse disabling gate, and Fig. 5.6 shows h o w one of the four gates of the CD4001 can be m a d e t o act as a gate of this t y p e .

S I G N A L I N P U T ( A )

juuuuuuuuul

i _ G A T E I N P U T

( B)

5 V t o 1 5 V * v e

I C i = C D 4 0 0 1

UU1 I W O U T

T O P I N S 5 , 6 .

8 , 9 .12 A N D 13

O V

I N P U T O U T

A B

O U T

0 0 1

1 0 0

0 1 0

1 1 0

Fig. 5.6

Simple pulse disabling gate with truth table


O V

Fig. 5.7

Non-inverting pulse disabling gate with truth table

The above circuit can be modif ied t o act as a non-invert ing pulse disabling gate , if requi red , by in terposing a pulse inverter stage be tween the i npu t signal and the i npu t of the gate , as shown in Fig. 5 .7 . No te t ha t t w o of these circuits can be m a d e from each C D 4 0 0 1 i.e.

The pulse disabling gate of Fig. 5.7 can be conver ted i n t o a pulse enabling gate , which passes signals only when the gate i n p u t is high or at logic level 1, by in terposing a pulse inverter stage be tween the gating i n p u t signal and the gate i n p u t pin of the disabling gate , and Fig. 5.8 shows h o w the CD4001 can be so used. Only one such gate can be bui l t from each i .e.

Final ly, the pulse disabling gate of Fig. 5.7 can be conver ted t o an electronically or manual ly triggered S T A R T / S T O P gate , which starts passing signals at a S T A R T c o m m a n d and s tops passing t h e m on a separate STOP c o m m a n d , by feeding the c o m m a n d signals t o t he gate via a simple bistable mul t iv ibra tor e l ement . Fig. 5.9 shows the electronically triggered version of such a circui t , and Fig. 5 .10 shows the manual ly triggered version.

T h e t w o circuits opera te in t h e same basic w a y , and use the t w o left-hand C D 4 0 0 1 gates as a bistable mul t iv ibra tor , and use t he two

Here , an i n p u t signal is applied t o pin 1 of t he i.e., and a gating or c o m m a n d signal is applied t o pin 2 . Tlie o u t p u t of the circuit is t aken from pin 3 . Normal ly , wi th a zero or logic 0 gating i n p u t appl ied, the circuit acts as a simple pulse inverter and p roduces an o u t p u t signal at pin 3 . When , however , a logic 1 gate i n p u t is applied t o pin 2 , the circuit 's o u t p u t is driven i n t o the logic 0 s t a te , and the i n p u t signal n o longer appears at the o u t p u t . The gate is thus 'disabled' . The four possible s tates of t he circuit are shown in the t r u t h table of Fig. 5 .6 . No te t ha t four i ndependen t pulse disabling gates can be bui l t from each CD4001 i.e.

5 V t o 15V * v e


r ight-hand gates as actual gating e lements . Normal ly , the o u t p u t of the bistable is high or at logic 1, so the gating circuit 's o u t p u t is g rounded , and none of the i npu t signal reaches the o u t p u t te rminal . When the S T A R T c o m m a n d is given the bistable changes s ta te , and

S I G N AL I N P U T ( A )

O -nnnnnnnnruui

I C, = C D 4 0 0 1

3 P̂ TO P I NS

I 12 A N D 13

O V

Fig. 5.8

Pulse enabling gate with truth table

I N P U T O U T

A B O U T

0 0 0

1 0 0

0 1 0

1 1 1

5 V t o 1 5 V . v e

S T A RT S T OP

r JuuuuL:

O V

Fig. 5.9

Electronically triggered STAR T/STOP gate

5 V t o 1 5 V . v e

Fig. 5.10

Manually triggered START/STOP gate


CD4001 logic circuits

The CD4001 COSMOS i.e. can be used t o per form all five of the basic functions of digital logic. The mos t basic of all logic e lements is t he N O T circuit , which uses the symbol shown in Fig. 5.1 l a . This circuit is

(a) h — T 0 P I NS 5 . 6 .

8 . 9 . 1 2 A N D 1 3

Fig. 5.11

(a) NOT logic symbol; (b) NOT logic circuit

simply a pulse inverter , and gives a logic 1 o u t p u t from a logic 0 i n p u t , and vice versa. Fig. 5.1 l b shows h o w one of the gates of a CD4001 can be connec ted as a N O T logic e l ement : four such e lements can be buil t from each CD4001 package .

I N P U T A<

I N P U T

(a)

O U T

O U T P U T I S H I G H I F A L L I N P U T S

A RE L O W O U T P U T I S L O W I F

E I T H ER I N P U T I S H I G H I N P U T A

I N P U T B<

(b)

5 V t o 1 5 V . v e

I C , = C D 4 0 0 1

O U T

T O P I NS 5 , 6 ,

8 ,9 ,12 A N D 13

Fig. 5.12

(a) NOR logic symbol; (b) NOR logic circuit

Fig. 5.12a shows the symbol t ha t is used t o represent a N O R logic e lement , and Fig. 5 .12b shows the connec t ions for making one of these e lements from one gate of a C D 4 0 0 1 i.e. F o u r such e lements can be made from each CD4001 package. The circuit act ion is such t ha t i ts o u t p u t goes t o logic 1 only when b o t h inpu t s are at logic 0 . The o u t p u t goes t o logic 0 if e i ther i npu t is at logic 1.

locks in to this n e w state even when the c o m m a n d signal is sub-sequent ly removed . As the bistable changes s ta te its o u t p u t goes t o logic level 0 , the gate opens and passes the i n p u t signals t o its o u t p u t . These signals con t inue t o flow unt i l a STOP c o m m a n d is given, a t which po in t the bistable flips back to its original log ic 1' cond i t i on , the gate closes and s tops the i n p u t signal from reaching the o u t p u t .


O U T P U T I S L O W I F A L L I N P U T S

A RE L O W : O U T P U T I S H I G H I F

E I T H ER I N P U T I S H I G H .

I N P U T A

I N P U T B O U T 5 V t o 15V . ve

\l TO P I NS 8 ,

9,12 A N O 13

Fig. 5.13

(a) OR logic symbol; (b) OR logic circuit

buil t from each i.e. The circuit ac t ion is such t ha t i ts o u t p u t goes t o logic 0 only when b o t h inpu ts are at logic 0 ; t he o u t p u t goes t o logic 1 if e i ther i n p u t is at logic 1.

Fig. 5.14a shows the symbol t ha t is used t o represent a N A N D logic e lement , and Fig. 5 .14b shows the connec t ions for making one of

I N P U T A

I N P U T B

O U T P U T I S L O W I F A L L I N P U T S

A RE H I G H . O U T P U T I S H I G H I F

A N Y I N P U T I S L O W

O U T

(a)

I N P U T A

I N P U T B

5 V t o 1 5 V . v e

ICrCDAOOl

(b)

Fig. 5.14

(a) NAND logic symbol; (b) NAND logic circuit

these e lements using all four of the gates of a C D 4 0 0 1 i.e. The act ion of this circuit is such t ha t its o u t p u t goes t o logic 0 only when b o t h inpu ts are at logic 1. The o u t p u t goes t o logic 1 if e i ther i n p u t is at logic 0 .

Final ly , Fig. 5.15a shows the symbol t ha t is used t o represent an A N D logic e lement , and Fig. 5 .15b shows the connec t ions for making one of these e lements using three of the gates of a C D 4 0 0 1 i.e. The

(a)

Fig. 5.13a shows the symbol tha t is used t o represent an O R logic e lement , and Fig. 5 .13b shows h o w one of these e lements can be bui l t from a pair of gates from a CD4001 i .e. T w o such e lements can be


O U T P U T I S H I G H I F A L L I N P U T S

A RE H I G H : O U T P U T I S L O W I F

A N Y I N P U T I S L O W

I N P U T A

• O U T I N P U T B

(a)

(b)

I N P U T A

I N P U T B

5 V t o 15V . v e

I C, = C D 4 0 0 1

8 U O U T

K T O P I NS 12 A N D 13

O V

Fig. 5.15

(a) AND logic circuit; (b) AND logic circuit

act ion of this circuit is such tha t its o u t p u t goes t o logic 1 only when bo th inpu t s are at logic 1. The o u t p u t goes t o logic 0 if e i ther i npu t is at logic 0 .

C D 4 0 0 1 mul t iv ibra tor projects

The C D 4 0 0 1 i .e. can be made t o per form as any of the three basic types of mul t iv ibra tor circuit . Fig. 5 .16a shows t w o ways of using the i.e. as a simple bistable mul t iv ibra tor or m e m o r y circuit . Fig. 5.16a is an electronically triggered version of the circuit , and Fig. 5 .16b is a manual ly triggered version.

Each circuit is m a d e u p from t w o cross-coupled gates of t he i.e., and the circuit ac t ion is such t ha t t he o u t p u t of t he bistable sets and locks t o t h e high or logic 1 level w h e n a logic 1 c o m m a n d signal is briefly applied t o pin 2 of t he i .e. , or sets and locks t o the low or logic 0 level when a logic 1 c o m m a n d signal is briefly applied t o pin 5 of the i .e. No te tha t t he circuit switches i n t o the required s tate wi th in nanoseconds of the appl icat ion of the i n p u t c o m m a n d signal, and remains locked in to t h a t s tate even when the c o m m a n d signal is sub-sequent ly r emoved . The form and dura t ion of the c o m m a n d signal is of l i t t le impor t ance t o the circuit ac t ion , so long as its peak ampl i tude exceeds approx imate ly 6 0 % of t he circuit supply voltage.

In the Fig. 5.16a circuit the c o m m a n d signals consists of external pulses (or o the r waveforms) t ha t are fed t o the i npu t terminals of the bis table . In the Fig. 5 .16b circuit the c o m m a n d signals are derived


J L

Ri

I M 12

5 V t o 15V * v e

R 2 I M 12

I— TO P I NS

8 , 9 , 1 2 A N D 13

O V

Fig. 5.16a

Electronically triggered bistable multi or memory unit

5 V to 15V * v e

1 C , = C D 4 0 0 1

Fig. 5.16b

Manually triggered bistable multivibrator

Figs. 5.17 and 5.18 show t w o ways of using the i.e. as a monos tab le or one-shot mul t iv ibra tor . Fig. 5.17 is an electronically triggered version of the circuit , and Fig. 5.18 is a manual ly triggered version. Each circuit is designed a round t w o of the gates of a CD4001 i.e. The circuit act ion is such t ha t its o u t p u t is normal ly low or at logic level 0 , b u t switches to logic level 1 for a pre-set per iod as a rising trigger waveform is applied t o pin 2 of the i.e. The o u t p u t pulse per iod is

from the positive supply rail via push-bu t ton switches Sx or 5 2. In each case, the circuit o u t p u t effectively ' r emembers ' which of the t w o inpu t terminals last received a c o m m a n d pulse .

T R I G G ER I N P U T

/10 SEMICONDUCTOR PROJECTS 107 5V t o 15V • v e

>1 5 M U

A

r

2

>IMU

IC, = CD4001

_ J V O UT I ^ I

TO P I NS 8 , 9 , 1 2 A N D 13

OV

Fig. 5.17

itos/c monostable multivibrator or pulse stretcher is electronically triggered

£ 100k il

5 V t o 1 5 V . v e

> 1 . 5 M f i

-H I s / x / F I—

J — 1 _ :

O UT

ICi = CD4001

TO P I NS 8 , 9 , 1 2 A N D 13

OV

Fig. 5.18

'Noiseless'push-button or manually triggered monostable

de te rmined by the values of Ri and C i , and approx imates 1 second

per /xF of C\ value wi th the Rx value s h o w n . Periods can be varied

from less than one microsecond t o several minu tes by selection of

the Ri a n d C x values.

It should be n o t e d t ha t the o u t p u t pulse of the circuit is in i t ia ted

at the m o m e n t t ha t t he inpu t trigger signal rises t h rough a ' th resho ld '

level of roughly half-supply vol ts , and tha t once the o u t p u t pulse has

been in i t ia ted i ts dura t ion is qui te i ndependen t of the signal on p in 2

108 30 COSMOS DIG ITAL I. C. PROJECTS

12 A N D 13

O V

Fig. 5.19

Basic 1kHz astable multivibrator or square wave generator

Fig. 5.19 shows h o w t w o of the gates of a CD4001 i .e. can be wired toge ther t o make a basic 1kHz astable mul t iv ibra tor or square wave genera tor . The circuit ac t ion here is such t ha t capaci tor Cx a l ternately charges and discharges via t iming resistor Rx, p roduc ing a regenerative switching act ion at the end of each t iming cycle and the reby generat ing square waveforms at o u t p u t s A and B. The A and B o u t p u t s are in ant i -phase.

A useful feature of the basic astable circuit of Fig. 5.19 is t ha t it uses only t w o t ime-cons tan t c o m p o n e n t s (Rx and C i ) , and the values of b o t h of these c o m p o n e n t s can be varied over wide ranges t o give required opera t ing frequencies. The value of Rx can be varied from a few thousand ohms t o thousands of m e g o h m s , and Ci (which mus t be a non-polarised capac i tor ) can be varied from a few p F t o h u n d r e d s of JUF. The operat ing frequency is inversely p ropor t iona l t o the Rx and Cx values, and can be varied from less t han one cycle per h o u r t o several megaher tz .

of the i.e. The shape and dura t ion of the trigger signal is of l i t t le impor tance t o the circuit ac t ion , so long as its ampl i tude exceeds approx imate ly 6 0 % of the supply vol tage, and the trigger pulse or signal can even have a longer per iod than the o u t p u t pulse signal if requi red .

In the electronically triggered Fig. 5.17 circuit the trigger signals are derived from an external source . In the manual ly triggered Fig. 5.18 circuit the trigger signals are derived from the positive supply rails via push -bu t ton switch Si.

5 V t o 1 5 V - v e


The opera t ing frequency of the basic circuit can be m a d e variable, if requi red , by wiring a variable resistor in series wi th l imit ing resistor R l9 as shown in t he circuit of Fig. 5 .20 . With t he c o m p o n e n t values shown , t he circuit covers t he approx ima te f requency range 6 0 0 H z t o

— ^ T 0 P I NS 8 . 9

12 A N D 13

O V

Fig. 5.20

Variable frequency (500Hz-6kHz) astable multivibrator

H I G H ( O F F )

G A T E • —

I N P U T

L OW ( O N )

OV

Fig. 5.21

Gated J kHz astable multivibrator

The basic astable circuit described above usually produces a square wave tha t is slightly non-symmetr ica l ( the symmet ry is dependen t on the characterist ics of the individual CD4001 i.e. used) , and the opera t ing


frequency of the circuit varies slightly wi th the supply voltage (a 4 0 %

variat ion in supply voltage typical ly causes a 5% variat ion in f requency) .

Apar t from these minor defects , t he circuit gives a very useful per-

formance , and is except ional ly versatile. The astable can be gated on

and off via an external l o g i c ' signal, for example , by using the con-

nec t ions shown in Fig. 5 . 2 1 . T h e astable is cu t off when the gate i n p u t

signal is h igh , and is operative when the gate i npu t signal is l ow .

5 V t o 1 5 V . v e

L * T O P I N S

12 A N D 13

O V

Fig. 5.22

Buffered output J kHz astable multivibrator

Fig. 5.22 shows h o w one of the spare gates of the CD4001 i.e. can be added t o the basic astable circuit t o act as a buffer stage which b o t h improves the shape of the o u t p u t square waveform and prevents the opera t ing frequency from being influenced by external loading.

Final ly , Figs. 5.23 and 5.24 show h o w steering diodes can be added t o the basic circuit t o enable the symmet ry of the o u t p u t waveform t o be varied t o mee t part icular requi rements . In the Fig. 5.23 circuit t iming capaci tor C\ charges via D\ and the low half of the resistance chain in one half-cycle, and discharges via D2 and the t o p half of the resistance chain in the o the r half-cycle. The mark/space ra t io can be varied over the range 1/11 t o 11/1 via R2, and the circuit operates at a frequency of roughly 6 0 0 H z ; the frequency varies slightly as the mark/space ra t io is varied.

The Fig. 5.24 circuit has independen t ly variable ON and O F F t imes . Here , Cx charges via Dx-Ri-R3, and discharges via D2-R2-R^. The per iod of each half-cycle is variable over the range Spts t o 800/xs using the c o m p o n e n t s shown . Periods of u p t o one h o u r can be ob ta ined by increasing the c o m p o n e n t values.

R , i 6 8 0 W l |


5 V t o 1 5 V . v e

0 * f - * 6 0 0 H z

M /S R A T IO = l / H t o I l / l

I C , = C D 4 0 0 1

* D, A N D D2= L O W - L E A K A GE S I L I C ON D I O D ES

Fig. 5.23

Variable mark/space ratio astable multivibrator

5 V t o 1 5 V * v e

10kfl

iMa

D;

P E R I OD O F E A CH H A L F - C Y C LE I S V A R I A B LE F R OM 8 / J S T O 8 0 0 / J S

_ C,

" l O O O p F

I C , = C D £ 0 0 1

• T O P I NS 8 . 9 .

12 A N D 13

OV * D , A N D D 2 = L O W - L E A K A GE S I L I C ON D I O D ES

Fig. 5.24

Astable multivibrator with independently variable on and off times


D . C . lamp-cont ro l circuits

The CD4001 COSMOS i.e. can be used in a variety of d.c. l amp flasher and l amp d immer appl icat ions . Fig. 5.25 t o 5.27 show three simple examples of such lamp-cont ro l circui ts . These circuits are i n t ended t o drive 12V lamps at cur rents u p t o 2 A.

! 2 V * v e

I C, = C D 4 0 0 1

Fig. 5.25

Simple d.c. lamp flasher (rate -1.5 seconds per flash, ^ 40 flashes per minute)

Fig. 5.25 shows the circuit of a simple l amp flasher. Here , one half of t he CD4001 i.e. is wired as a low-frequency astable mul t iv ibra tor or square genera tor , which symmetr ical ly drives the l amp on and off via transistors <2i and Q2. With t he c o m p o n e n t values shown the l amp flashes at a ra te of roughly 1.5 seconds per flash, or 4 0 flashes per m i n u t e . The flashing rate can be varied, if requi red , by replacing Rt with a fixed and a variable resistor in series.

Fig. 5.26 shows h o w the above circuit can be modif ied t o give a p rog rammed du ty cycle so t h a t , for example , the l amp tu rns on for a single per iod of only 0.75s in each 8.25 second cycle , thus giving a 1:10 d u t y cycle and giving considerable cur ren t e conomy as an emergency l amp flasher. The ON t ime of the l amp is cont ro l led by Rx and Z>i, and is fixed at abou t 0 .75s , b u t the O F F t ime is con-trol led by R2 and D2, and can be varied over a wide range. When R2 is given a value of 1M12 the l amp has an O F F t ime of 0 .75s , and when R2 has a value of 10M12 the O F F t ime is abou t 7.5s. The R2 value can be varied from a few thousand ohms t o thousands of m e g o h m s , as requi red , t o give any desired O F F t ime .


1 2 V . v e

* = G E N E R A L - P U R P O SE S I L I C ON D I O D ES

T^rr O V

Fig. 5.26

Programmed duty cycle (P-D-C) lamp flasher

G A N G ED

I C ^ C D A O O I

= G E N E R A L - P U R P O SE S I L I C ON D I O D ES

~r^T7 O V

Fig. 5.27

D.C. lamp dimmer, —ve ground

Fig. 5.27 shows the circuit of the d .c . l amp d immer . Here , one half of the C D 4 0 0 1 is wired as an astable mul t iv ibra tor t h a t opera tes a t a fixed frequency of abou t 100Hz , b u t has a du ty cycle or m a r k / space ra t io t h a t is fully variable from approx imate ly 1:20 t o 2 0 : 1 via

The o u t p u t waveform of the astable is used t o drive the l amp via

t ransistors Qx and Q2. Consequen t ly , the mean power t o t he l amp can

114 30 COSMOS DIG ITAL I. C PROJECTS

T o n e a n d alarm-generator circuits

The CD4001 i.e. can be used in a variety of t one and alarm-generator appl icat ions . Figs. 5.28 t o 5.35 show several practical circuits of these types .

5 V to 15V • v e

Fig. 5.28

Code-practice oscillator

Fig. 5.28 shows the circuit of a simple b u t useful code-pract ice oscillator. Here , t w o of the gates of the i .e. are wired as a gated astable mul t iv ibra tor , wi th its i npu t derived from the morse key and its o u t p u t t aken t o a pair of high-impedance h e a d p h o n e s via R4 and one of the spare gates of the i .e. The tone of the circuit can be varied from 300Hz t o 3kHz via Rx, and the ' phone volume is variable via The circuit draws a s t andby cur ren t of abou t 0.003JUA when the morse key is open , thus obviating the need for a separate O N / O F F swi tch . The circuit can be used wi th any 'phones having an impedance greater than a few h u n d r e d o h m s .

Fig. 5.29 shows h o w the i.e. can be used as the basis of a low-power fixed-frequency ( m o n o t o n e ) alarm-call generator . Here , t w o of the gates of the i.e. are wired as an 800Hz gated astable mul t iv ibra tor ,

be varied from approximate ly 5% t o 9 5 % of m a x i m u m v i a / ? 3. Since

the period of the basic 100Hz waveform (10ms) is shor t relative t o

the thermal t ime cons tan t of the l a m p , the in tensi ty of the lamp can

be varied from virtually zero t o m a x i m u m wi th n o sign of flicker. No te

t h a t O N / O F F switch Sx is ganged t o R3, so t ha t the circuit can be

switched fully off by turning the R3 'bri l l iance ' con t ro l fully anti-

clockwise.

115 5 V to 15V • v e

O V

Fig. 5.29

Low-power 800Hz alarm generator

I C, = C D A 0 0 1

O V

Fig. 5.30

Medium-power (0.25 W to 11.25 W) alarm generator

15V . v e

Fig. 5.31

High-power (18W) alarm generator


5 V t o 1 5 V . ve

Fig. 5.32

Pulsed-tone alarm generator

Fig. 5.32 shows the circuit of a low-power pulsed-tone alarm generator . Here , gates A and B are wired as a fixed-frequency astable mul t iv ibra tor tha t operates at a frequency of abou t 6Hz and is gated on via S l9 and gates C and D are wired as an 800Hz astable mult i -vibrator t ha t is gated on and off by the o u t p u t of the A-B astable. The o u t p u t of the 800Hz astable feeds t o the speaker via Qi and Rx. Thus , when Sx is closed the tone in t he speaker comprises an 800Hz no t e tha t is pulsed on and off at a ra te of 6Hz .

Fig. 5.33 shows h o w the above circuit can be modif ied for use as a pulsed-output water-act ivated alarm by simply increasing the value of the gate-A i n p u t resistor t o 10M12 and replacing switch St wi th a pair of meta l p robes . The circuit act ion is such tha t the alarm turns on when a resistance less than abou t 5M12 is placed across the p robes , as occurs when the p robes come in to con tac t wi th water .

Final ly , Figs. 5.34 and 5.35 show the circuits of low-power one-shot and self-latching alarm generators respectively. In each case

wi th its o u t p u t fed t o a speaker via l imit ing resistor Rx and boos te r t ransistor Qx. The speaker and Rx should have a to ta l resistance of a b o u t 100 o h m s . With switch Sx open the generator is inopera t ive , and the circuit consumes a s t andby cur rent of only IJUA or so . With Si c losed, the generator is operat ive , and drives the speaker. O u t p u t power depends on the supply voltage and speaker Rx values used , bu t approximates 160mW when a 10012 speaker (Rx = zero) is used wi th a 9 V supply .

Figs. 5 .30 and 5.31 show h o w the o u t p u t power of the above circuit can be boos t ed u p t o m a x i m u m s of 11.25W and 18W respect-ively by using alternative t ransistor o u t p u t stages.

117

5 V T O 15 V » v e

Fig. 5.33

Pulsed-output water-activated alarm

5 V t o 1 5 V * v e

Fig. 5.34

One-shot alarm generator

5 V t o l 5 V . v e

OV

Fig. 5.35

Self-latching alarm generator

118 30 COSMOS DIG ITAL I. C. PROJECTS

gates C and D of t he circuits are wired as 800Hz gated astable mul t i -vibrators which each feeds a speaker via t ransis tor Qt9 and each astable is gated on and off via the mult ivibrators formed by gates A and B.

In the Fig. 5.34 circuit gates A and B are wired as a gated m o n o -stable or one-shot mul t iv ibra tor which is triggered by momenta r i ly closing switch Sx. Consequen t ly , the circuit ac t ion is such tha t the alarm is normal ly off, b u t tu rns on as soon as S i momenta r i ly closes, and then tu rns off again automat ica l ly after a pre-set pe r iod . The per iod is roughly equal t o 0.5 seconds per juF of Cx value. Cx mus t have a leakage resistance less t han one m e g o h m .

In the Fig. 5.35 circuit gates A and B are wired as a manual ly triggered bistable mul t iv ibra tor , which can be changed from one s tate t o the o the r by briefly closing switch Sx or 5 2. Consequen t ly , t h e circuit act ion is such t h a t the alarm is normal ly off, b u t tu rns on and self-latches as soon as Sx is momenta r i ly closed. The alarm then stays on indefini tely, or unt i l S2 is briefly ope ra t ed , at which po in t the alarm resets i n to the O F F s ta te . In the O F F state the circuit consumes a quiescent cu r ren t of only one mic roamp or so . The circuit is t hus ideally sui ted t o use in burglar alarm and similar appl icat ions .

INDEX

A.C. operated switch, 27 -28 Alarm circuits, 114 Alarm generator, 114-118

one-shot, 116 self-latching, 116 water-activated, 116

Amplifiers, common emitter, 3 - 4 , 7, 10,12

common source, hybrid, 4 3 - 4 4 simple, 4 2 - 4 3

compound, 4 4 - 4 6 constant-volume, 5 0 - 5 3 2-stage direct coupled, 4 - 8

Analogue/digital converter, resistive, 6 1 - 6 2

voltage, 6 2 - 6 4 AND logic circuit, 105 Astable multivibrator, 30, 53,108

very low frequency, 4 7 - 4 9 Attenuation, 52 Attenuator, frequency-selective, 29

voltage-operated, 51 Attenuator network, 53 Avalanching, 53

Back-bias, 72, 76 Base-bias, 7 Base-bias resistor, 4, 8, 22 Beam blanking, 60 Bias resistors, 9 Biasing systems, field-effect

transistors, 38 -39

Bistable multivibrator, 32, 71, 72, 74, 84 ,101 ,105 ,108

Blocking capacitor, 60 Bootstrap capacitor, 40 Bootstrap technique, 7 , 9 , 4 0 , 4 2 Bridge rectifier, 11,12, 88 ,91 , 94

Cadmium sulphide photocell, 24 Car parking lights, automatic operation

of, 25 CD4001,98

circuit, 99 multivibrator projects, 105

Chopper, field-effect transistor, 53 Common emitter amplifier, 3 - 4 , 7,

10,12 Common emitter pre-amplifier, 24 Common source amplifier, hybrid,

4 3 - 4 4 simple, 4 2 - 4 3

Complementary feedback pair, 11 Compound amplifier, 44—46 Computer logic, 103 Constant current generator, 21, 66 Constant-volume amplifier, 5 0 - 5 3 Constant-width pulse, 7 1 - 7 2 Copper losses, 20 COSMOS digital i.e., 95

projects, 95-118 Counter, diode-pump, 68—69 Current regulator circuits, 2 0 - 2 2 Cut-off, 12

119

120 INDEX

Darlington emitter follower, 13,18 Darlington mode, 9 D.C. lamp-control circuits, 112 D.C. 2-stage amplifier, 4 - 8 Decay time, 52 Delays. See Time delays Digital inverter, 97 Dimmer, lamp, 112 Diode-pump counter, 6 8 - 6 9 Diodes, 11 Distortion, 52 Division ratio, 6 8 - 6 9 Drain, 33 ,45 ,53 Drain current, 36, 39 Drain-to-source resistance, 36 Drain-to-source voltage, 36 Drift, 47

Electronic switch, 22, 27 Emitter-base junction potentials, 2 Emitter decoupling capacitor, 6 Emitter follower, 7 , 1 1 , 1 7 , 4 1

circuits, 8 -11 Darlington, 13,18 super-alpha pair, 73

'Fade', 53 Field-effect transistor, 33 -53

advantages, 33 basic types, 33 biasing systems, 38 -39 characteristics, 34 -38 chopper, 53 constant-volume amplifier, 5 0 - 5 3 equivalents of basic operating

modes, 34 insulated-gate, 33 junction-gate, 33 n-channel, 33 p-channel, 33 timer circuits, 4 9 - 5 0 v.l.f. astable multivibrator, 4 7 - 4 9 voltmeters, 4 6 - 4 7 see also Source follower

Flasher, lamp, 112 Flip-flop, 84 Forward bias, 36,55, 72, 76, 88 Frequency control, 74 Frequency divider, 66, 68

synchronised, 69 Frequency-selective attenuator, 29 Frequency-selective network, 29

'Galloping Ghost', 73 Gate, 33 Gate-to-drain capacitance, 4 2 - 4 5 Gate-to-source bias voltage, 35 Generator,

pulsed tone, 116 square wave, 108 tone, 114

Germanium transistors, 1 - 3 , 9

Half-wave rectifier, 88 Heat sink, 18,19

IGFET. See Field-effect transistor, insulated-gate

Impedance transformers, 8 Integrated circuit projects, 95-118 Intrinsic stand-off ratio, 54

JUGFET. See Field-effect transistor, junction-gate

Lamp-control circuits, 112 Lamp dimmer, 112 Lamp flasher, 86,112

variable on/off-time, 76 Lamp/relay driver, one-shot, 74 -76 Leakage currents, 3 , 4 , 9 , 1 1 , 1 2 Light-dependent resistor, 24 Light-operated switch, 2 4 - 2 5 , 91 Logic levels, 96 Low frequency rejection

characteristics, 30

Memory unit, 32 Miller effect, 44, 45 Miller feedback, 43 Monostable multivibrator, 32, 72,106 M-S ratio control, 74

see also Variable frequency/ M-S ratio generator

Multi-channel remote control, 29 Multivibrator, 3 0 - 3 2

astable, 30, 53,108 very low frequency, 47—49

bistable, 32, 71, 72, 74, 84 ,101 , 105,118

free-running, 47 monostable, 32, 72,106, 118

INDEX 121

NAND logic circuits, 104 Negative feedback, 4 , 6 , 1 1 , 29,

38 ,52 Negative feedback biasing, 7 'Noiseless' push-button, 107 NOR logic circuits, 103 NOT circuit, 96 NOT gate, 97 NOT logic circuits, 103 npn transistors, 1, 2, 6, 33, 38

Off-set gate biasing, 43 ,47 One-shot lamp/relay driver, 74 -76 OR logic circuits, 104 Oscillator, 56 Oscilloscope, time-base generator

for, 60

Peak-point emitter current, 57 Peak-point, voltage, 56 Phase shift, 7 Photocell, cadmium sulphide, 24 Photo timer, 26 Pinch-off voltage, 35 pnp transistors, 1, 2, 6 ,17 Polarity, 11 ,12 ,25 Positive feedback, 29, 30,112 Potential divider, 26, 38 ,46 ,68 ,

76,91 Potential divider network, 9 ,13 , 24 Power dissipation, 18,19, 21, 22 Power transistor, 17, 21 Pre-amplifier, common emitter, 24 Pulse circuits, 100-118 Pulse, constant-width, 7 1 - 7 2 Pulse counter, 66 Pulse disabling gate, 100 Pulse enabling gate, 102 Pulse expander, 66 Pulse generator, 32, 83

unijunction, 86 -88 , 92 variable-frequency , 7 1 - 7 2 variable on/off-time, 72 -73 wide-range, 5 8 - 5 9

Pulse inverter circuits, 100 Pulse stretcher, 107 Push-button, noiseless, 107

Relaxation oscillator, 56 temperature stabilised, 56

Relay, automatic turn-off after pre-determined period, 15

switch-on delay, 15

Relay coil resistance, 28 Relay contacts, 25 Relay driver, 74 -76 Relay operating circuits, 11-16 Relay time-delay circuits, 6 4 - 6 6 Remote control, multi-channel, 29 Repetitive switching circuits, 8 6 - 8 8 Reverse bias, 35, 36, 55, 88 RTL inverter, 96

Saw-tooth generator, linear, 59 -61 wide-range, 59

Saw-tooth waveform, 56, 59 Schmitt trigger, 22, 24, 27, 74 Schmitt trigger circuit, 50 Screening, 6 Self-biasing system, 39,42 Self-latching circuit, 82, 91 Series controlled converter, 62 Shunt controlled converter, 62 Shunting effects, 9 Side lights, automatic operation of, 25 Signal feedback, 6 Signal injector, 32 Silicon controlled-rectifiers, a.c.

on/off circuits, 88 -89 advantages, 7 8 - 7 9 automatic turn-off circuit, 84 basic characteristics, 77 basic parameters, 7 9 - 8 2 bistable circuit, 84, 88 capacitor-discharge turn-off

circuit, 83 circuit action, 78 d.c. on/off circuits, 82 -84 gate, 77 light-operated switch, 91 maximum forward current, 80 maximum forward voltage, 80 maximum gate current to trigger, 81 maximum gate voltage to trigger, 81 maximum holding current, 81 maximum permissible gate current,

81 maximum reverse voltage, 80 peak on-voltage drop at If, 81 power gain, 78 -79 projects, 77 -94 repetitive switching circuits, 8 6 - 8 8 single-button on/off circuit, 85 structure, 79 symbol, 77

122 INDEX

Silicon controlled-rectifiers {contd.) theory, 79 variable-power circuits, 9 2 - 9 4

Silicon diode, 35, 36 ,40 Silicon-planar transistors, 1-32

types, 1 use of, 1 -3

Silicon transistors, 1 -4 , 9 ,17, 21, 76 Sine/square converter, 22 -24 Smoothing capacitor, 28 Sound-operated switch, 28 -29 Source, 33 Source follower, 49 Source follower circuits, basic, 3 9 - 4 0

hybrid, 40 Square wave, 24,53 Square wave generator, 30, 32,108

wide-range, 69 -71 Staircase divider/generator, 6 6 - 6 8 Start/stop gate, 102 Step-voltage generator, 66 Super-alpha mode, 9 Super-alpha pair emitter follower, 73 Switch, a.c. operated, 27 -28

electronic, 22, 27 light-operated, 24 -25 , 91 sound operated, 2 8 - 2 9 time, 26 tone operated, 2 9 - 3 0 voltage-triggered, 56 water operated, 25 -26

Switching circuits, repetitive, 86 -88 Synchronised frequency divider, 69

Tape recorder, 28 -29 Temperature stabilised relaxation

oscillator, 56 Thyristor. See Silicon controlled-

rectifier Time-base generator for oscilloscope,

60 Time constants, 3 2 , 4 7 - 4 9 , 1 0 8 Time delays, 11 ,13 ,15 , 2 8 , 6 4 - 6 6 Time switch, 26 Timer, circuits, 4 9 - 5 0

unijunction circuit, 84 -85 Tone generator circuits, 114 Tone operated switch, 2 9 - 3 0 Transconductance, 36 Transformers, impedance, 8 Transistor curve tracers, 66 Transistor operating modes, and

f.e.t. equivalents, 34

Transistors MJE370,17 MJE520,17 2N708, 97 2N2646, 58 2N2926,1 ,10 ,16 2N2926(o), 25 2N3702 ,1 ,16 ,21 ,25 2N3819,36,42

Trigger, Schmitt, 74 Trigger circuit, Schmitt, 50 Twin-T components, 29 ' 2-stage direct coupled amplifiers, 4 - 8

Unijunction, applications, 5 8 - 7 6 basic principles, 5 4 - 5 8 characteristics, 58 construction, 54 equivalent circuit, 54 intrinsic stand-off ratio, 54 projects, 54 -76 pulse generator, 86 -88 , 92 symbol, 54 timer circuit, 84-85

Variable current regulator, 22 Variable frequency/M-S ratio

generator, 73 Variable on/off-time lamp flasher, 76 Variable-power circuits, 9 2 - 9 4 Variable reference potential, 18 Variable resistor, 22 Variable-voltage regulator, 18 Voltage divider, 54 Voltage divider base-bias network, 11 Voltage divider network, 9, 26 Voltage-operated attenuator, 51 Voltage reference device, 39 Voltage regulator, 18 Voltage regulator circuits, 16 -20 Voltage trigger, 110 Voltage-triggered switch, 56 Voltage-variable resistor, 36 Voltmeter, 3-range f.e.t., 4 6 - 4 7

Water-activated alarm, 116 Water-operated switch, 25 -26

Zener diode, 16,17, 2 0 - 2 2 , 38 Zener potential, 16 Zener reference potential, 19

Documents

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