Optimized Layout Design of Priority Encoder using 65nm Technology

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 78

Optimized Layout Design of Priority Encoderusing 65nm Technology

AmriteshOjhaDepartment of ECE, National Institute of Technical Teachers’ Training &Research Chandigarh, India-

[email protected]

Abstract: This paper provides comparative performanceanalysis of power and area of 4 bit priority encoder using65nm technology.Two priority encoder approaches arepresented, one with full automatic and the other withsemicustom. The main objective is to compare full automaticand semicustomdesigned layout on the basis of twoparameters which is power and area. The automatic designcircuit simulation has been done on logic editor and layoutcreated from Verilog file which is simulated. Thesemicustom layout is created manually and simulated.Creation of layout in both types of method is done at 65nmCMOS technology.The simulation results show that priorityencoder using semicustom design has improved powerefficiency and area by 29.61µWand 253.8µm2 respectively.

Keywords: Priority Encoder, Low Power, Area,65nmtechnology, CMOS

1. INTRODUCTIONNowadays, priority encoder has been widely utilizedin

high-performance critical applications whichpersistentlyimpose special design constraints in terms ofhigh-frequency, low power consumption, and minimal area[1].In the growth of the integrated circuit towards largeintegration density with high operating frequency theconcern issues are power, delay and smaller silicon areawith higher speed [2].Priority encoders are used in anumber of computer systems as wellas other applications.When several processes, modules, or units requesta singlehardware (or software) resource, a decision has to bemadeto allow a single request to use such a resource. Thepriorityencoder implements a fixed selection functionwhere the resource isgranted to the request with thehighest priority [3].The development of digital integratedcircuits ischallenged by higher power consumption [4].Asthe computer systemsbecome more compact the areaofthe PE becomes a key parameter in the design ofthesystem. And at the same time, the overwhelmingdemand forportable electronics encourages thedevelopment of apower optimized PE structure[5].Thispaper discusses comparison between 4 bit priorityencoder design between fully automatic layout usingstatic CMOS logic and semi-custom layout using staticCMOS logic at 65nm technology.Industrial 65nmprocesses have been introduced by Toshiba in 2002,Fujitsu, NEC and STMicroelectronics in 2003 and byIntel in 2004. With transistor channels ranging from 30nmto 50nm in size (30 to 50 billionth of a meter),comparable to smallest microorganisms this technology istruly nanotechnology [6].Here Microwind3 is used todraw the layout of the CMOS circuit [7].In digitalelectronic an encoder is the logic device that converts 2Ninput signals to N-bit coded outputs. The output of a

priority encoder is the binary representation of the ordinalnumber starting from zero of the most significant inputbit. If two or more inputs are given at the same time, theinput having the highest priority will take precedence.

2. PRIORITY ENCODER DESIGNThis 4 bit priority encoder circuit is designed to controlinterrupt requests by acting on highest priority requestwith output produced by the desired bit.The truth table ofpriority encoder is given in Table1. The Xs are don’t careconditions that designate the fact that the binary valuesrepresent either 0 or 1.Input D3 has highest priority, soregardless of the value of other inputs, when the input is1, the output Y1, Y2 is 11.D2 has the priority level. Theoutput is 10 if D2 =1 and D3 = 0, irrespective of the valuesof the other two lower priority inputs, the outputs for D3

is generated only if higher priority inputs are 0, and so ondown the priority level. A valid output indicator V is setto 1 only when one or more of the inputs are equal to 1. Ifall the inputs are equal to 0, V is equal to 0, and the othertwo outputs (Y1 and Y0) of the circuit are not used [8].

Table.1 Truth table of 4 bit priority encoder

‘

Fig.1.Shows the logic diagram of 4 bit priority encoderwhich consists two 2 input OR gates, one 4 inputs OR

gate, one 2 input AND gate and one inverter

Fig.1. Logiclevel priorityencoderNow replacing the basic logic gates used in above logiclevel diagram by their staticCMOS logic using DSCH

Inputs OutputsD0 D1 D2 D3 Y1 Y0 V01XXX

001XX

0001X

01001

X0011

X0101

01111


79 NITTTR, Chandigarh EDIT-2015

represented in fig. 2. The DSCH program is a logic editorand simulator. DSCH is used to validate the architectureof logic circuit before microelectronics design is started[9].Fig. 2 shows the CMOS implemented 4 bit priorityencoder on DSCH3.CMOS semiconductors have bothPMOS and NMOS transistors and only one of them is onat any instant of time.

Fig. 2.CMOS equivalent on DSCH3

Fig.3.shows the output simulation of CMOS equivalent of4 bit priority encoder on DSCH.

Fig.3. Simulation result of equivalent CMOS logic

The DSCH program is a logic editor and simulation. Itprovides user-friendly and fast simulation [10].

3. PRIORITY ENCODER LAYOUT SIMULATIONThis section consist two design layout simulation mainlyfull automatic layout and semicustom layout. Fullautomatic layout has been developed on Microwind3.1.HereVerilog file generated on DSCH3 got compiled andgive an idea about all PMOS and NMOS connectionswithground and supply voltage. It gives an idea aboutinterconnections between two different metallayerspolysilicon layer and metal layers got connected.Italso gives an idea about lambda rule to design our desiredlogic circuit. Fig. 4. Shows the fully automatic layoutgenerated on Microwind3.1 of 4 bitpriority encoder whenwe use staticCMOS logic gates. So this is the gate levelimplementation of our desired logic level circuit.

Fig.4.Full automatic layout using staticCMOS logicThe simulation result is shown in fig. 5.

Fig. 5. Simulation result of full automatic layoutFig.6. Shows the semicustom design layout usingstaticCMOS logic using Microwind3.1 on 65nmtechnology.

Fig. 6. Semi-Custom layout using static CMOS logic

Fig. 7.Shows the simulation result of semi-custom layout.

Fig.7.Simulation result of semi-custom layout



4. RESULT ANALYSISComparative analysis between automatic design layoutand semi-custom design layout of 4 bit priority encoder isshown in table.2.Comparison is based on the factorresponsible for factors affecting performance of priorityencoder are power dissipation and effective area used.Comparison shows that semi-custom design based 4bitpriority encoder is better than automatic design layout.This improvement in power and area is recorded on 65nmtechnology in both design techniques.

Table.2 comparative performance analysis

Fig. 8.and fig. 9. Represents the comparison on Columnchart for power and area respectively.

Fig.8. Power Graph

Fig.9.Area Graph

5. CONCLUSIONFrom the above analysis it can be concluded thatsemicustom is more useful technique to reduce theeffective area on a chip and power dissipationthanautomatic.So semi-custom design analysis of 4 bitpriority encoder finds the better simulation results forboth parameters i.e. power consumptions and area. Fullcustom design for priority encoder for more number ofbits is another considerable design which is the futureaspect of this paper. Thus as shown in table.2 powerconsumption is reduced by 86.35% and area is reduced by83.40%.

REFERENCES[1] Saleh Abdel-hafeez and ShadiHarb, “A VLSI High-PerformancePriority Encoder UsingStandard CMOS Library”, IEEE Transactions onCircuits and Systems—II: Express Briefs, Vol. 53, No. 8, pp. 597-601,2006[2] Swati Sharma, Rajesh Mehra:“Area & Power Efficient Design ofXNOR-XOR Logic Using 65nm Technology”, International Journal ofEngineering and Technical Research, pp.57-60,2014[3] José G. Delgado-Frias, and JabulaniNyathi, “A High-PerformanceEncoder with PriorityLookahead”, IEEE Transactions onCircuits and Systems—I: Fundamental Theory and Applications, Vol.47, No. 9, pp.1390-1393, 2000.[4] PushpaSaini, Rajesh Mehra:“A Novel Technique for Glitch andLeakage PowerReduction in CMOS VLSI Circuits”, InternationalJournal of Advanced Computer Science and Applications, Vol. 3, No.10,pp.161-168 2013[5] Cheong KUN, ShaoleiQuan, and Andrew Mason, “A Power-Optimized 64-Bit Priority EncoderUtilizing Parallel Priority Look-Ahead”, International Journal of Ad hoc, Sensor & UbiquitousComputing (IJASUC), Vol.1, no.3, pp.85-91, 2010[6]Etienne SICARD,SyedMahfuzulAziz:“Introducing 65nm technologyin Microwind3”, Microwind application Notes,pp. 3, 2006[7] VandanaChoudhary,Rajesh Mehra:“2- Bit Comparator UsingDifferent Logic Style of Full Adder”, International Journal of SoftComputing and Engineering (IJSCE), Volume-3, Issue-2,pp. 277-279,2013[8] M. Morris Mano, Michael D. Ciletti:“Digital Design”, PearsonEducation Inc., pp. 167-168, Fourth Edition, 2008[9] Etienne SICARD:User’s Manual: Microwind and DSCH”, Version3,pp. 7, 2006[10] I. Hassoune, D. Flandre, I. O’Connor and J.D.Legat:ULPFA: ANewEfficient Design of A Power Aware Full Adder”, IEEE Transactions onCircuits and Systems I-5438,pp.2066-2074, 2008

0

50

FullAutomatic

SemiCustom

35.9410.38

Power

0

500

1 2

293.940.1

Area

Parameters Fullautomaticlayoutdesign

Semi-customlayoutdesign

Power(µW)

35.94 6.32

Area(µm2)

293.9 40.1






Fig.8. Power Graph

Fig.9.Area Graph



SemiCustom

10.38

40.1



Power(µW)

35.94 6.32

Area(µm2)

293.9 40.1






Fig.8. Power Graph

Fig.9.Area Graph





Power(µW)

35.94 6.32

Area(µm2)

293.9 40.1

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Optimized Layout Design of Priority Encoder using 65nm Technology