Opportunities of Wafer Level Embedded Technologies · PDF fileOpportunities of Wafer Level Embedded Technologies for MEMS ... UV-laser drilling through RCC to open ... Integrated glass

© Fraunhofer IZM

Tanja Braun, SIIT

SEMI MEMS Tech Seminar (Sept 26, 2013 - Cornaredo, Italy)

Opportunities of Wafer Level Embedded Technologies for MEMS

Devices T. Braun (1), K.-F. Becker (1), R. Kahle (2), V. Bader (1), S. Voges (2), T. Thomas (2),

R. Aschenbrenner (1), K.-D. Lang (2)

(1) Fraunhofer Institute for Reliability and Microintegration Gustav-Meyer-Allee 25, 13355 Berlin, Germany

e-mail: [email protected] phone: +49-30/464 03 244 fax.: +49-30/464 03 254

(2) Technical University Berlin, Microperipheric Center

© Fraunhofer IZM

Tanja Braun, SIIT


Outline

Introduction – FOWLP

Application Examples

MST SmartSense Multi-Sensor Package

Sensor Integration into Microfluidics

© Fraunhofer IZM

Tanja Braun, SIIT


Fan-out Wafer Level Packaging (FOWLP)

Die assembly on carrier

with release tape

Carrier overmolding

Carrier release

RDL (e.g. thinfilm, RCC, ink-

jetting), balling, singulation

“Molded Reconfigured Wafer” , Infineon

“Redistributed

Chip Package”,

Freescale

„Fan-Out Wafer-Level Packaging “,

Renesas Electronics Corporation

„Wafer-Level Fan-Out

Packaging, WFOP“,

J-Devices

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Tanja Braun, SIIT


From Wafer to Panel Level Packaging

24“x18“ 6“

PCB Technologies

Thin Film Technologies

• Based on standard PCB manufacturing equipment

• Intrinsic warpage compensation by lamination

• 3D and double sided routing are standard features for PCBs – Line/space down to 20/20 µm

• Full format/large area is standard

12“ 8“

• Based on standard thin film technology equipment

• Tightest tolerances for fine pitch line/space (5/5 µm)

• Sensitive to substrate warpage • Currently limited to 12” – 300 mm

© Fraunhofer IZM

Tanja Braun, SIIT


Chip Embedding - IZM Embedding & Substrate Line

from Wafer Scale to Panel Scale 610 x 456 mm²

Datacon evo/

Siplace CA3

Mahr OMS 600 WL: Towa 120t

PL: NN – Q2 2014

Lauffer/

Bürkle

Siemens

Microbeam

Ramgraber auto-

matic plating line

Schmoll MX1 Orbotech

Paragon 9000

Schmid

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Tanja Braun, SIIT


FOWLP with PCB based RDL and Through Mold Vias (TMV) Process Flow

Precision die placement on intermediate carrier

Large area compression molding

Lamination of RCC both wafer sides

Cleaning, Pd activation und Cu plating µVias and TMVs

Laser direct imaging (LDI) and Cu layer etching Molded wafer release from carrier

UV-laser drilling through RCC to open die pad and through molded wafer for TMVs

Soldermask, UBM, package singulation by sawing

3D module assembly

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Tanja Braun, SIIT


Motivation SiP Wafer Level Fan-Out Embedding

µC

MS-ASIC

Roadmap source: Yole

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Tanja Braun, SIIT


Application Example MST SmartSense - Intelligent 3D MEMS Compass

http://www.emft.fraunhofer.de/index.html

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Tanja Braun, SIIT


MST SmartSense - Intelligent 3D MEMS Compass

Chip on Board technology Transfer molded LGA housing

Heterogeneous Integration BGA Multi-Sensor Package Evaluation of Material

Combinations Reliability Investigations

µC

MS-ASIC

Technology Demonstrator Commercial Product Advanced Technology

sensor

ASIC

LGA pad

TMV

PoP approach using embedding as a basis

Thin film & PCB based RDL Product well within specs!

© Fraunhofer IZM

Tanja Braun, SIIT


FOWLP Multi-Sensor Stack

substrate PCB based RDL MEMS acceleration

sensor

ASIC

ASIC

MEMS pressure

sensor

Through Mold Via (TMV) molding

compound

thin film RDL

Manufacturing of functional demonstrators

FOWLP Multi-Sensor Stack consisting of

Pressure Sensor/ASIC package with thin film RDL and RDL opening above sensor membrane

Acceleration sensor/ASIC package with PCB based RDL and Through Mold Vias (TMV) for package stacking

© Fraunhofer IZM

Tanja Braun, SIIT


FOWLP – Pressure Sensor-ASIC Package

pressure sensor packages after wafer level molding and redistribution

Thin film redistribution Open RDL layer above pressure sensor membrane Comparable sensor performance over the entire wafer

M. Bründel, U. Scholz, F. Haag, E. Graf, T. Braun, K.-F. Becker; Substrateless sensor

packaging using wafer level fan-out technology; Proc. of EPTC 2012; Singapore.

© Fraunhofer IZM

Tanja Braun, SIIT


Through Mold Via - Reliability

Investigations of 5 different epoxy molding compounds

with max. filler sizes from 24 µm to 75 µm

4 different via diameters/pitches (200 µm/400 µm, 150 µm 350 µm, 100 µm/300 µm, 50 µm/250 µm)

TMV test

vehicle

EMC with max. 24 µm filler size 50 µm via and 250 µm pitch

EMC with max. 75 µm filler size 50 µm via and 250 µm pitch

All samples passed:

MSL 1

5000 temperature cycles -55 °C/125 °C

5000 h humidity storage 85 °C/85 % r.h.

without any electrical failures

Laser drilled Through Mold Vias: 100 up to 150 vias/s

Direct metallization by Cu plating

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Tanja Braun, SIIT


Sensor Package - Through Mold Via (TMV)

Cross section – Through mold via

X-Ray image – acceleration sensor-ASIC package

with through mold vias (red arrows)

• Precisely laser drilled and homogeneously metalized through mold vias • Well aligned and void-free Cu filled µVia with 110 µm pitch and structured

conductor lines with 55 µm lines and spaces

ASIC

Sensor

EMC

RCC

Cross section – Through mold via interconnection between

ASIC and sensor with PCB based RDL technology

© Fraunhofer IZM

Tanja Braun, SIIT


FOWLP Multi-Sensor Stack

Functional tests show sensor performance in specs

sensor

ASIC

LGA pad

TMV

Acceleration sensor/ASIC package with PCB based RDL

and Through Mold Vias (TMV) for package stacking

assembled sensor

stack on test board

pressure sensor/ASIC package with thin film RDL

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Tanja Braun, SIIT


Application Example Sensor Integration into Microfluidics • ENIAC Cajal4EU

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Tanja Braun, SIIT


Sensor Integration into Microfluidics

Concept and CAD-Design

Fabrication

Characterization

System design / simulation

Fluidics

World to chip interface

Polymer / PDMS structuring &

Bonding

Surface modification

Integration of Microelectronics /MEMS / MOEMS…

Fusion of components to

functional demonstrator

Fluidic characterization Functional experiments System validation

Ev

al. °C

30

.2

35

.4

40

.5

45

.7

50

.9

56

.1

61

.2

71

.6

LO

I0

PO

I1

PO

I0

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Tanja Braun, SIIT


Example: Sensors and Actuators for Automated Cell-free Protein Production

Process automation: Phase interface and bubble detectors

Micro actuators / pumps / valves

Control and regulation: Electrochemical pH-sensing

Optical Mg-sensing by color change reaction

Temperature spot control with micro peltiers

Glucose measurement for energy regeneration

system

Yield measurement: Fluorescence measurement with µPMT

RNA purity control by UV-absorbance

measurement

Bubble detector

Integrated glass fiber Integrated pH-Sensor (Fh ISIT)

Micro glucose sensor (Fh ISIT) www.micropelt.com

Integrated RGB- Sensor with LED

µPMT (Hamamatsu)

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Tanja Braun, SIIT


Cajal4U: Integration of CMOS Biosensor into a Polymeric Lab-on-a-Chip Systems

T. Brettschneider, C. Dorrer, H. Suy, T. Braun, E. Jung, R. Hoofman,

M. Bründel, R. Zengerle and F. Lärmer, “Integration of CMOS biosensor into a polymeric

lab-on-a-chip systems”, International Conference on Microfluidics and Nanofluidics, 2013,

Venice, Italy.

CMOS sensor die

reconfigured wafer with RDL

singulated FOWLP

module

FOWLP module in

microfluidics

reconfigured wafer

Feasibility of packaging approach for

silicon-into-polymer suitable for mass

fabrication successfully shown

Protection of sensing area during

packaging allows application to wide

range of biosensors

Tightness high enough for most

microfluidic applications

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Tanja Braun, SIIT


Cajal4U: Integration of CMOS Biosensor

X-ray image of

connected TSV die

X-ray CT image of FOWLP

Cross section of connected TSV die Photography of FOWLP

Separation of “wet” microfluidics from

“dry” electrical connection

Use of TSV dies for 3D routing

Backside TSV die connection by blind

µvias through molding compound

© Fraunhofer IZM

Tanja Braun, SIIT


Conclusion

A technology has been successfully developed for stacking wafer level

embedded packages by Through Mold Vias (TMV)

Technology based on large area compression molding and

PCB based redistribution technology with potential to full PCB format

(610 x 457 mm²) or

Standard thin film redistribution technology

Laser drilled TMV technology has very high reliability potential – samples

passed MSL1, 5000 TC -55 °C/125°C and 5000 h 85°C/85 % r.h. without

failure

Technology was successfully demonstrated for

a functional ASIC- MEMS acceleration sensor package on which an

ASIC – MEMS pressure sensor package is assembled

Sensor integration into microfluidics

© Fraunhofer IZM

Tanja Braun, SIIT


Outlook - Fan-out Panel Level Packaging (FOPLP)

Continuous manufacturing line for FOPLP up to 24“ x 18“ / 610 x 457 mm²

© Fraunhofer IZM

Tanja Braun, SIIT


Thank you for your attention

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Opportunities of Wafer Level Embedded Technologies · PDF fileOpportunities of Wafer Level Embedded Technologies for MEMS ... UV-laser drilling through RCC to open ... Integrated glass