Op to Electronic and Microelectronic

8/8/2019 Op to Electronic and Microelectronic

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Name : Chong Kai Wei (6650)

College : KBU INTERNATIONAL COLLEGE

Course : Engineering in Electrical and Electronics Engineering

Subject : Optoelectronic and Microelectronic Engineering

Name of Lecturer : Mr Chio

Title : The mask layout design of a BCD to 7 Segment Decoder


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Table of Contents

1. INTRODUCTION................................ ................................ ............................. 1 1.1. Aims ................................ ................................ ................................ ....................11.2. Objectives ................................ ................................ ................................ ...........11.3. Resources and Budget ................................ ................................ ........................ 12. LITTERATEUR REVIEW ................................ ................................ ...............22.1. Physical Design ................................ ................................ ................................ ...22.2. Physical Design Flow ................................ ................................ .......................... 33. SYSTEM DESIGN AND DEVELOPMENT ................................ .................... 43.1. True table of 7-segment decoder ................................ ................................ ........43.2. Kmap of 7-Segement Decoder ................................ ................................ ........... 53.3. Schematic of 7-segment decoder ................................ ................................ ........73.4. Layout of 7-segment decoder ................................ ................................ ............. 84. TESTING AND RESULTS ................................ ................................ ............... 94.1. Design Rules Checks (DRC) ................................ ................................ ............. 114.2. Layout Versus Schematic (LVS) ................................ ................................ ......125. CONCLUSION ................................ ................................ ................................ 14


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1. INTRODUCTION

We have design a BCD to 7-segment decoder using mentor graphics software. A BCD to

7-segment decoder consists of 4 bits binary input and 7 outputs connect to 7-segment

display. Next, we have mask layout and perform DRC and LVS on the BCD to 7-

segment decoder. Due to this, a truth table can be drawn to define this.

1.1. AIMS

y To design a BCD to segment Decoder.

y To layout and perform physical verification on the BCD to 7 Segment Decoder.

1.2. OBJECTIVES

y Design the decoder based-on the truth table.

y Use standard cells in DA to capture the decoder circuit.

y Simulate the circuit using Eldo.

y Use the block cells created to route the mask layout of the decoder.

y

Ensure the layout is DRC clean.y Ensure the layout is LVS clean.

1.3. RESOURCES AND BUDGET

The entire project was purely was software based, which was implementing, simulating

and programming by using Mentor Graphic software. The project development was done

in the college EDA lab. The EDA software required are Design Architect (DA-IC),

ELDO, Ezwave, IC Station and Calibre. Therefore there are no any budgets in this

project.


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2. LITTERATEURREVIEW

2.1. PHYSICAL DESIGN

A.Design Architect

Design Architect is a multi-level design environmental entry tool. It is a design

program which knows about the electrical components, wire, buses and electrical

rules. This tool is use to perform schematic capture for design entry. More

importantly, this tool helps create the schematic which can be used as reference

when performing LVS

B. IC Station

IC Station is a layout design tool to perform the layout and verification process.

IC Station provides capability for full-custom editing and semi-custom editing. IC

Graph tool is the main entry point into the IC Station environment and this tool is

used to handicraft layout for silicon mask. While IC Rules and IC Trace tools is

used to verify the correctness of the design as opposed to the technology

constraints and the schematic description of the project.


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2.2. PHYSICAL DESIGN FLOW

1. First, we should design a BCD to 7segment decoder, after need to draw the cells

in the schematic circuit such as (Inverter, AND and OR)

2. The design rules and process technology used in this layout design is TSMC

0.35um. These must be loaded first before the drawing of the layout with the IC

Station software can be done. When drawing in IC Station, Design Rules Check

(DRC) the layout to make sure its free from design rules error.

3. The final task after DRC is the Layout Versus Schematic (LVS). LVS, which is in

the Design Architecture software, will check the correspondence between layout

and schematic.


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3. SYSTEM DESIGNAND DEVELOPMENT

3.1. TRUE TABLE OF 7-SEGMENT DECODER

The design of the BCD to 7-segment decoder is done based on the truth table of 7-

segment decoder.

Decimal D C B A a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 1 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 1 1 1 1 1 0 1 1

Table 3-1: True table of 7-segment decoder


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3.2. KMAPOF 7-SEGEMENT DECODER

The design of K maps based on the truth table. From the K maps, the Boolean equations

of all 7 parts of the 7 segment decoder are obtained. they represents the input (D, C, B, A)

and output(a, b, c, d, e, f, g)


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3.3. SCHEMATIC OF 7-SEGMENT DECODER

From these Boolean equations, the schematic of the 7-segment decoder is able to be

designed. The schematic of the 7 segment decoder is designed entirely using

INVERTER, OR, AND gates.

Figure 3-1: schematic of 7-segment decoder


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3.4. LAYOUT OF 7-SEGMENT DECODER

The mask layout based on the schematic of the 7-segment decoder design.

Figure 3-2: layout of 7-segment decoder


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4. TESTINGAND RESULTS

Figure 4-1 shows the schematic of symbol testing. The schematic is converted into a

symbol. In this symbol generated will be given pulse inputs to enable the output of the

symbol to be testing by using EZwave viewer

Figure 4-1: schematic of symbol testing


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Next step is running the ELDO function to check the BCD to 7 segment decoder

schematic. Result can be viewed in EZwave, it function is used to check the output

produced by the schematic. After should be checks the result or waveform to determine

whether the design is correct.

Figure 4-2: simulation result of output


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4.1. DESIGN RULES CHECKS (DRC)

Design rules are a set of guidelines which specify the minimum of width and spacing

allowed in a layout drawing. The rules are derived from the limitation of the technology

processing and other physical considerations. The design rules used in this project is

MOSIS scalable CMOS (SCMOS) rules. They show the minimum requirement for the

width and spacing allowed in the TSMC 0.35 technologies.

Figure 4-2: DRC of 7-segment decoder


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4.2. LAYOUT VERSUS SCHEMATIC (LVS)

A successful design rules check (DRC) only ensures that the layout passes through the

rules designed faultless fabrication. To ensure that the layout is the desired circuit, a tool

is required to compare the schematic and layout, the tool used is called LVS. LVS works

by generating a spice netlist from the layout and comparing it with the spice netlist of the

schematic. LVS will notify the designer whether the layout is match with the schematic.

In most of the layout error will be listed as follows

Property error:

A property is in the wrong size compared to the schematic.

Shorts

Two or more wires are not supposed to be connected together.

Component mismatches

Component of a incorrect type has been used.

Missing components

An unexpected component has been left out.


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Figure 4-2: LVS of 7-segment decoder (1)

Figure 4-2: LVS of 7-segment decoder (2)


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5. CONCLUSION

As a conclusion, the BCD to 7 segment decoder is able to be designed and the layout of

the decoder is able to be built.The BCD to 7 segment decoder has been done by gate-

level and transistor-level. The layout produced also has been done check and perform

physical verification by using various Electronic Design Automation (EDA) verification

softwares such as the DRC and LVS check.

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Op to Electronic and Microelectronic