On the Selection of Efficient Arithmetic Additive Test Pattern Generators

S. Manich, L. García, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J. Figueras

Universitat Politècnica de Catalunya, UPC

Outline• Introduction• Motivation• State of the art• Objective• Proposed technique• Experimental results• Conclusions

System on Chip (external test access is difficult)

Moore’s Law for Test: Fab vs. Test Capital

• SIA Roadmap Data 2001

Using BIST for DFT

BIST

e.g. LFSR’s

Reusing internal datapathsIncrement

Adder

Accumulator

Test Vectors

DATAPATH

• First proposed by Rajski and Tyszer.

• Similar LFSR behavior. Proved by Chiusano, Prinetto and Wunderlich

Test Pattern Generator

Signature Analyzer

Comparison of test sequencesL

FS

RA

dTP

G119 test vectors

Comparison between LFSR and AdTPG

• c3540, fault coverage of stuck-at. No reseeding

0102030405060708090

100

0 500 1000 1500 2000 2500

Test vector

Fau

lt c

over

age

AdTPGLFSR

Drawbacks of the AdTPG

Memory size doubles

Seed 1

MEMORY

Seed 1Increment 1

MEMORY

LFSR AdTPG

l1 l1

Memory size doubles

Seed 1Seed 2

MEMORY

Seed 1Increment 1

Seed 2Increment 2

MEMORY

LFSR AdTPG

l1 l1l2

l2

Memory size doubles

Seed 1Seed 2Seed 3

MEMORY

Seed 1Increment 1

Seed 2Increment 2

MEMORY

Seed 3Increment 3

LFSR AdTPG

l1 l1l2l3 l2

l3

Memory size doubles

Seed 1Seed 2Seed 3Seed 4

MEMORY

Seed 1Increment 1

Seed 2Increment 2

MEMORY

Seed 3Increment 3

Seed 4Increment 4

LFSR AdTPG

l1 l1l2l3l4

l2

l3

l4

SItriplet

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Seed

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Increment

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Generation period less than 2n

000...0

001...1

011...1

101...1

111...1

Unswitched input signals during testL

FS

RA

dTP

G119 test vectors

Unswitched input signals during testL

FS

RA

dTP

G119 test vectors

Shadow from 11...11 substring

Shadow from 00...01 substring

Proposed methodologyLUCSAM

Using same value for seed and increment

Increment

Adder

Accumulator

Test Vectors

DATAPATH

Seed 1Seed 2Seed 3Seed 4

MEMORY

l1l2l3l4

SStriplet

k-triplet set

Always generate odd increments

Seed

Increment

LSB

1

1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Period of the test sequence is 2n

000...0

001...1

011...1

101...1

111...1

Avoid shadow zones in test sequence

• Limit the size of substrings 11...11 or 00...01

• Rule of thumb: “Any input switchs at least one time”

Increment

00.......0111.......1100.......0111.......11

T (test length)

A (maximum subgroup size)

2log ( )A T

Proposed methodology

Procedure preparation of k-triplet set for circuit C and a fault set Define target FC* and initial lenght L Run ATPG(C,) to generate initial test set S (initial set of seeds) for target FC*

While FC < FC* do For all seeds in S do Run HiFault(AdTPG(seed,seed’,L),C,) and calculate FC end do Select seed giving maximum FC increase Reduce set , set S and calculate length l Append in k-triplet set the SS triplet (seed,l) end doend procedure

Proposed methodology

Fault Set

Circuit

ATPG

Test Set

Proposed methodology

Fault Set

Test SetA

dTP

G Test sequence

Faultsimulator

Seed1(l1)

Proposed methodology

Fault Set

Test SetA

dTP

G Test sequence

Faultsimulator

Seed1(l1) Seed2(l2)Seed1

Proposed methodology

Fault Set

Test SetA

dTP

G Test sequence

Faultsimulator

Seed1(l1) Seed2(l2) Seed3(l3)Seed1

Seed2

Proposed methodology

Fault Set

Test SetA

dTP

G Test sequence

Faultsimulator

Seed1(l1) Seed2(l2) Seed3(l3) Seed4(l4)Seed1

Seed2

Seed3

Proposed methodology

Fault Set

Test SetA

dTP

G

Faultsimulator

k-triplet set

Seed1(l1) Seed2(l2) Seed3(l3) Seed4(l4)Seed1

Seed2

Seed3

Seed4

Experimental results. Fault coverage

94

95

96

97

98

99

100

94 96 98 100

LU

CS

AM

Previous published data

15 circuits

5 circuits

s953

s838

s5348

s420

s1196

1

10

100

1000

10000

100000

1 10 100 1000 10000 100000

Experimental results. Bits stored in memoryL

UC

SA

M

Previous published data

20 circuits

0 circuits

0

1000

2000

3000

4000

5000

6000

0 2000 4000 6000

Experimental results. Total test lengthL

UC

SA

M

Previous published data

17 circuits

3 circuits

c5315s820

c2670

0

20

40

60

80

100

0 500 1000 1500

Fault coverage evolution of c2670

Test vector

Fau

lt C

over

age

95.31%

Seed1 Seed2 Seed3 Seed4

Checking size of 11...1 or 00...0 subgroups

1

10

100

1000

10000

100000

0 20 40 60 80 100

Size of subgrup

# su

bstr

ings

Less than 1.31%

Random vectors

ATPG vectors

No risk of shadows using ATPG

Conclusions

• Verified that AdTPGs is a valid TPG.

• Memory size is reduced if Seed and Increment use same value. No lose of performances.

• LSB of increment masked to 1 to allow generation of all 2n values.

• Unswitching of input signals may be prevented by cautious detection of large 11...11 and 00...01 subgrups.

• LUCSAM: proposed algorithm selecting the best seeds from initial ATPG test vectors.

• Results show good behavior of the methodology. Average values are FC = 98.77 %, Memory = 783 bits and test length = 2398 vectors.

Future work

• Some capabilities are observed from the AdTPG.

• Test session preparation from RTL analysis.

• Better suited for input activity (power) reduction.

• Limitations are also observed.

• More difficult generation of test vectors for scan-path.

• Datapath register smaller than some circuit inputs.

Results for ISCAS’85

FC SS M N

Circuit of SATs TripletsBits stored in

memoryVectors

generated

c432 99,23 1 43 119 c499 98,97 1 50 292 c880 100,00 2 130 966 c1355 99,66 1 52 1.078 c1908 99,78 1 45 3.025 c2670 95,31 26 6.130 3.340 c3540 98,63 1 62 2.845 c5315 99,80 1 190 3.074 c6288 99,61 1 38 53 c7552 96,67 5 1.090 9.192

LUCSAM

Results for ISCAS’89

FC SS M N

Circuit of SATs TripletsBits stored in

memoryVectors

generated

s641 100,00 3 173 1.301 s713 98,21 1 65 1.659 s820 100,00 4 104 2.560 s838 96,68 11 737 1.709 s953 94,92 3 147 3.624

s1196 99,91 5 167 2.164 s1238 97,60 4 139 1.727 s1488 100,00 1 25 1.644 s1494 99,85 1 25 1.341 s5378 98,83 7 1.511 4.289

LUCSAM