On High Injection Mechanisms in Semiconductor Devices under … · ON HIGH INJECTION MECHANISMS IN SEMICONDUCTOR DEVICES UNDER ESD CONDITIONS PROEFSCHRIFT ter verkrijging van de graad

ON HIGH INJECTION MECHANISMS IN SEMICONDUCTOR DEVICES

UNDER ESD CONDITIONS

Gianluca Boselli

TITLE: On High Injection Mechanisms in Semiconductor Devices under ESD Conditions AUTHOR: Boselli, Gianluca ISBN: 90-365-1554-8 COVER PHOTO: Courtesy of Dante Tassi from PhotoValtidone ‘90. KEYWORDS: Electrostatic Discharge (ESD), High Injection Effects, Diffused Resistors, Substrate Diodes, ggnMOSt’s, LDMOSt’s. � 2001 by Gianluca Boselli, Enschede, The Netherlands.

ON HIGH INJECTION MECHANISMS

IN SEMICONDUCTOR DEVICES UNDER ESD CONDITIONS

PROEFSCHRIFT

ter verkrijging van

de graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,

Prof. dr. F. A. van Vught,

volgens besluit van het College voor Promoties

in het openbaar te verdedigen

op vrijdag 6 april 2001 te 16.45 uur.

door

Gianluca Boselli

Geboren op 12 februari 1967 te Busseto (Parma), Italië

Dit proefschrift is goedgekeurd door de promotor:

Prof. dr. ir. F. G. Kuper

en assistent promotor: Prof. dr. ir. A. J. Mouthaan

“Death is not when you can not communicate, but when you can no longer be understood” Pier Paolo Pasolini To my mother Afra

Samenstelling van de promotiecommissie: Voorzitter:

Prof. dr. H. Wallinga Universiteit Twente Secretaris:

Prof. dr. H. Wallinga Universiteit Twente Promotor:

Prof. dr. ir. F. G. Kuper Universiteit Twente/ Philips Semiconductors Assistent promotor:

Prof. dr. ir. A. J. Mouthaan Universiteit Twente

Leden:

Prof. dr. P. H. Woerlee Universiteit Twente/Philips Research

Prof. dr. ir. B. Poelsema Universiteit Twente

Prof. dr. J. W. Slotboom Technische Universiteit Delft/ Philips Research

Dr. A. Amerasekera Texas Instruments, Dallas, Texas

Dr. H. van der Vlist Philips Semiconductors

Contents Chapter 1 Electrostatic Discharge Phenomenology........................................... 1

1.I Problem description: what is ESD? .................................................................... 2 1.II On-chip protection against ESD: principles and devices ................................ 3

1.II.a ggnMOSt’s....................................................................................................... 4 1.II.b Silicon controlled rectifier (SCR) ....................................................................... 6 1.II.c Lateral npn...................................................................................................... 7 1.II.d Diodes.............................................................................................................. 8 1.II.e Protection networks........................................................................................... 8

1.III Testing ESD protection elements: how robust are they? ................................ 9 1.III.a Human Body Model (HBM) ........................................................................... 9 1.III.b Machine Model (HBM) ................................................................................. 10 1.III.c Charged Device Model (CDM) ...................................................................... 10 1.III.d Square pulse testing ........................................................................................ 10

1.IV EOS/ESD induced failure mechanisms and criteria...................................... 11 1.IV.a Junction burnout............................................................................................. 11 1.IV.b Metallization burnout..................................................................................... 12 1.IV.c Oxide breakdown........................................................................................... 12 1.IV.d Leakage current as failure criterion ................................................................. 12

1.V Motivation of the work....................................................................................... 13 1.VI Thesis outline ....................................................................................................... 14 1.VII References ............................................................................................................ 16

Chapter 2 High Injection Basics in Semiconductors ....................................... 19

2.I One type carrier injection................................................................................... 20 2.I.a Current in a system without thermal free carriers ............................................. 21 2.I.b Current in a system with thermal free carriers .................................................. 23 2.I.c Current in a system with thermal free carriers and traps................................... 25

2.II Two-carrier currents............................................................................................ 26 2.II.a The semiconductor injected plasma................................................................... 27

2.III Analytical approach to injection in semiconductors....................................... 29 2.III.a Low injection level .......................................................................................... 33 2.III.b High injection level ......................................................................................... 33

2.IV Numerical approach to injection in semiconductors...................................... 34 2.IV.a The Poisson Equation .................................................................................... 34 2.IV.b The Continuity Equations .............................................................................. 35 2.IV.c Current Relations ........................................................................................... 36 2.IV.d Mobility ......................................................................................................... 36 2.IV.e Heat Conduction Equation ............................................................................ 37 2.IV.f Thermally generated carriers ............................................................................ 38

2.V Conclusions .......................................................................................................... 39 2.VI References ............................................................................................................ 39

Chapter 3 Diffused Resistors under High Injection Conditions .................. 41

3.I Introduction ......................................................................................................... 42

3.II Region 1: Linear regime...................................................................................... 44 3.III Region 2: Saturation regime ............................................................................... 44

3.III.a High resistivity structure ................................................................................. 46 3.III.b Low resistivity structure .................................................................................. 49

3.IV Region 3: Negative differential resistivity regime............................................ 53 3.V Region 4: High current regime .......................................................................... 56 3.VI Non-isothermal conditions ................................................................................ 58 3.VII Conclusions .......................................................................................................... 62 3. VIII References ............................................................................................................ 63

Chapter 4 High Injection Mechanisms in P+-N--N+ Substrate Diodes: Theory Validation ................................................................... 65

4.I Introduction ......................................................................................................... 66 4.II Analysis of P+-N--N+ structures........................................................................ 67

4.II.a Low injection conditions .................................................................................. 68 4.II.b High injection conditions ................................................................................. 68 4.II.c Auger recombination....................................................................................... 79

4.III Simulations vs. measurements under high injection conditions ................... 81 4.III.a Carriers concentration ..................................................................................... 82 4.III.b Electric field and potential .............................................................................. 83 4.III.c Recombination currents ................................................................................... 85 4.III.d Simulated IA(VA) characteristic ...................................................................... 86 4.III.e Experimental verifications .............................................................................. 86

4.IV Conclusions .......................................................................................................... 87 4.V References ............................................................................................................ 87

Chapter 5 P+-N--N+ Substrate Diodes under Ultra High Injection Conditions .............................................................................. 89

5.I Introduction ......................................................................................................... 90 5.II Simulations vs. measurements under ultra high injection conditions .......... 91

5.II.a Measured and simulated IA(VA) .................................................................... 91 5.II.b Carriers concentration ..................................................................................... 92 5.II.c Electric field ................................................................................................... 95 5.II.d Potential......................................................................................................... 97 5.II.e Recombination currents ................................................................................... 98 5.II.f Ultra high injection conditions....................................................................... 100 5.II.g Modeling issues............................................................................................. 103

5.III TLP Characterization........................................................................................ 104 5.IV Process and layout variations........................................................................... 108

5.IV.a Base region length effects................................................................................ 108 5.IV.b Base region doping effects............................................................................... 108 5.IV.c Lifetime effects .............................................................................................. 109 5.IV.d End regions doping effects.............................................................................. 110 5.IV.e End regions length ........................................................................................ 111 5.IV.f Carrier-carrier scattering effects...................................................................... 112

5.V Conclusions ........................................................................................................ 112 5.VI References .......................................................................................................... 114

Chapter 6 LDMOS Transistors under High Current Conditions ............... 115

6.I Introduction ....................................................................................................... 116 6.II Experimental results.......................................................................................... 118

6.II.a Poly length variation effects............................................................................ 119 6.II.b CO-PS spacing variation effects .................................................................... 120 6.II.c W variation effects ........................................................................................ 120

6.III Simulation results .............................................................................................. 121 6.III.a Simulation approach..................................................................................... 121 6.III.b Drift region length ........................................................................................ 123 6.III.c Another point of view: the Kirk effect ............................................................ 125 6.III.d DIBL effect.................................................................................................. 129 6.III.e Breakdown behavior of LDMOSt................................................................ 130 6.III.f Application of a gate voltage ......................................................................... 135 6.III.g CO-PS distance ........................................................................................... 136 6.III.h Temperature effects and failure analysis ......................................................... 137

6.IV Conclusions ........................................................................................................ 139 6.V References .......................................................................................................... 140

Chapter 7 Transient Phenomena in ggnMOSt’s under TLP Conditions..................................................................................... 143

7.I Introduction ....................................................................................................... 144 7.II Simulated devices .............................................................................................. 145 7.III Results and discussion: LDD option .............................................................. 147 7.IV Results and discussion: non-LDD implant .................................................... 152 7.V Overlap capacitance evaluation ....................................................................... 154 7.VI VMAX versus VT1.................................................................................................. 158 7.VII Soft failures......................................................................................................... 160 7.VIII Latency aspects .................................................................................................. 162 7.IX Conclusions ........................................................................................................ 163 7.X References .......................................................................................................... 164

Chapter 8 Conclusions ............................................................................................ 167

8.I Summary ............................................................................................................. 168 8.II Conclusions ........................................................................................................ 169 8.III Recommendations for future research ........................................................... 171

Samenvatting .................................................................................................................. 173

List of scientific publications ..................................................................................... 175

Acknowledgements....................................................................................................... 176

Biography ........................................................................................................................ 178

Chapter

Abstract: in this chapter the phenomenon of the Electrostatic Discharge (ESD) will be explained. After a

general introduction concerning the phenomenon and quantifying its impact in terms of field returns, the

principles of the on-chip protection will be presented, with particular emphasis on the physics of the basic devices

used in CMOS technology. Furthermore, the existing tests to assess the robustness of protection structures

against ESD events and the induced failure mechanisms will be analyzed. Finally, the outline of this thesis will

be presented.

Electrostatic DischargePhenomenology

1

Chapter 1 Problem description: what is ESD?

- 2 -Electrostatic Discharge Phenomenology

1.I Problem description: what is ESD?

Electrostatic Discharge (ESD) is a common phenomenon in the nature: its name

comes from the fact that different materials can carry static positive or negative charges

resulting into a built-in static voltage. The amount of this static charge depends on the

triboelectric characteristics of the material and from external parameters like the

relative humidity. But once the statically charged material is put in contact with a

grounded object (large enough to act as ground), charge balance will be restored

through a discharge of the charged material towards the ground. In spite of the phe-

nomenon's name the discharge is extremely fast, in the order of some tens of nanosec-

onds.

A human body has a typical capacitance of about 100pF and a contact resistance of

about 1.5K : with these characteristics, an electrostatic potential of several KV's

(depending on the environmental conditions) may mean current up to several amperes.

The discharge of this potential through a grounded object (like, for instance, the door

of a vehicle) causes only a minor discomfort for the body. But since we are reliability

engineers and not doctors we care only the case in which the discharge occurs through a

pin of an IC: the high current (and, eventually, the high voltage) could cause an irrevers-

ible failure to the device.

Not only a human body but any charged object contacting an IC could lead to the

same result: this is the case when, after manufacturing, IC's have to be tested. If the

equipment does not have a proper grounding, it can accumulate a potential that might

discharge towards the IC's pins once these are put into the socket. In general, during all

the phases of an IC manufacturing process (from the very early beginning to the final

testing) ESD is a primary concern and together with the EOS (Electrical Overstress, of

which ESD is a subset) it has been quantified [1,2] to constitute about 38% ( ) of

the overall field returns. Since the phenomenon is unavoidable, there is a strong need of

developing protection strategies. There are two possible ways to tackle the problem.

The first way is “external” and consists in minimizing the potential causes of risk:

neutralization of static charges through air ionizers, shielded bags, grounded wrist

straps during IC's handling together with the awareness of phenomenon itself are

fundamental. In fact, the human susceptibility from an ESD discharge is about 3KV

[3]: below this threshold the human body does not feel anything whereas the accumu-

lated potential could already be high enough to destroy an IC.

The second way of protecting an IC from an ESD event is “internal” and consists in

implementing an “on-chip” protection circuit. A close correlation between simulation

�

Figure 1


Chapter 1 On-Chip protection against ESD: principles and devices

results and experiments on silicon is the only way to design an effective on-chip protec-

tion. In fact, ESD is an electro-thermal interaction of many structures in a very short

time frame and since the phenomenon itself is not fully understood from the physical

point of view, there is a lack of modeling of the devices behavior up to very high

injection level as encountered during an ESD event.

To add complication to complication, it is worth noting that the efficiency of a

protection strategy depends critically on the technology it is designed for: in fact, there

is no guarantee that the same protection strategy will still be good when moving to a

smaller feature sizes.

Assembly: 14%

Good: 4%Mobile Ion: 3% Unknown: 15%

ESD/EOS: 38%Fabrication: 26%

Figure 1: Distribution of the causes for field returns after [ ].2

1.II On-Chip protection against ESD: principles and

devices

In general, any possible discharge path between whichever couple of pins of an IC

should be protected and, therefore, a protection implemented. In principle a protection

circuit should behave as an ideal switch in parallel with the node to be protected (

): when an ESD event occurs, it should be able to shunt all the stress current and clamp

the voltage across the node (short-circuit like behavior) to avoid that an excessive

overvoltage can harm the connected circuitry (for instance to break the thin oxide of an

input state buffer in CMOS technology). On the other hand, during the operating

conditions of the circuitry, it should be in a high impedance state not to interfere with

the normal operations (open-circuit like behavior).

Figure

2



On top of these basic specifics an ESD protection should fulfill several other charac-

teristics: turning-on fast (at least < 1nsec.), having a low on-resistance, minimizing the

area at the bond pad, minimizing the capacitance, be robust to numerous pulses,

offering protection for various ESD stress models, not interfere with the IC's func-

tional testing and so on.

There are many possible candidates that can act as a single element protection

structure, depending on the technology, the applications and the design constraints.

Single protection elements submitted to an ESD event are forced to work under high

injection conditions. It is therefore important to review the relevant aspects of the main

protection devices under these conditions, with particular emphasis on the principle of

the “snapback conduction mode” of the nMOS transistors.

In CMOS technology the nMOS transistors (in grounded gate configuration, with

all electrodes grounded with exception of the drain) are widely used as protection

elements because they exploit a very appealing characteristic when subjected to an ESD

strike: the snapback conduction mode ( ). This mode is characterized by low

voltage and low on-resistance (2-5 ), which imply low power dissipation. The

snapback conduction mode exploits the parasitic bipolar action intrinsic in the struc-

ture and is reached in this way: when a positive pulse (ESD) is applied to the drain

1.II.a ggnMOSt's

Figure 3

�

Pr.Net.

PINProtectionNetwork

Circuit toprotect

VPROT.

IESD

Figure 2: Ideal protection network behavior.



junction (n /p substrate) the device is forced into a high impedance state (reverse

biasing) until the breakdown voltage (V ) is reached ( ).

+

BR Figure 4

Figure 3: Parameters defining the snapback conduction mode.

Hole-electron pairs are generated inside the depletion region because of the high

value of the electric field: electrons are collected at the drain contact while the holes are

collected at the grounded substrate contact, increasing the local substrate potential with

respect to the grounded source junction. When this local potential difference is high

enough to forward bias the source-substrate junction, electrons are injected from the

source to the drain.

Figure 4: Art impression of the mechanisms turning-on the bipolar parasitic transistor in a ggnMOSt.

DrainSource

Gate

p

n+ n

+

Substrate

RSUB

IESD

CO-PSLCO-GS

IESD

VPROT.

ICOperating

Area

NominalVoltage

BVOX

VHOLD

Gate OxideBreakdown

Area

VT1

RON

Second Breakdown Region

(I ,V )T2 T2



If this parasitic bipolar structure (Drain=Collector; Substrate=Base;

Source=Emitter) has a forward gain high enough, it can provide its own base current,

keeping the structure self-biased. Once the bipolar structure turns on, the voltage can

decrease from its maximum value (V V ) to a minimum value (V ) because there

is no need anymore to force the drain junction in deep breakdown to sustain the forced

current. Notice that between the triggering voltage (V ) and the holding voltage

(V ) there is a negative differential resistivity (NDR) region that is not stable (or, in

other words, it is not possible to bias the device in these points) but it simply represents

the transition between two stable biasing points (high and low impedance).

Once the holding voltage is reached, the forced current is entirely sustained by the

parasitic bipolar transistor (snapback conduction mode). In this region the resistivity

becomes once again positive (the on-resistance, which assesses the shunting capabili-

ties of the device) because conductivity modulation of the substrate takes place,

implying that a larger substrate current is needed to keep the parasitic bipolar device on.

Still, it has to be noted that not all the substrate of the bipolar structure acts a base and,

similarly, only a portion of the collector junction is forward biased. By further increas-

ing the current, self-heating effects come into play, increasing the internal temperature.

When this reaches the melting point of silicon (1685 °K), a change of phase might

take place by leading to an irreversible change of the device characteristics. This phe-

nomenon, causing the destruction of the device, is called “second (or thermal) break-

down” (V ) and its relative current (I ) is considered as the onset of the irreversible

damage. Given its crucial importance, the ggnMOSt has been object of intensive

studies, in particular with respect to the impact of design parameters (CO-PS distance,

L, dynamic coupling, multi-fingers layout) and process parameters (LDD option,

Salicide, P-well profile) in order to maximize the performances and to generate reliable

models for compact modeling simulations.

The Silicon Controlled Rectifier (SCR) is the most efficient device for protection

against ESD. It simply consists of a pnpn structure ( ): it can be seen as a npn and

pnp transistors configured such that the base of the pnp (n-well) is also the collector of

the npn and, on the other way around, the base of the npn (p-well) is also the collector

of the pnp. When used as protection device it is configured as two terminals device: the

cathode and the n-well are grounded whereas the stress is applied to anode, which is

tied to the p-well. This ensures that during normal operating conditions, latch-up will

T1 BR HOLD

T1

HOLD

T2 T2

�

1.II.b Silicon controlled rectifier (SCR)

Figure 5



not take place. When an ESD stress is applied to the anode, the n-well/p-well junction

is forced into reverse biasing until it reaches the breakdown (V ). The generated holes

are collected at the p-well contact while biasing the base of the lateral npn and, there-

fore, turning it on. At this point the electron current injected into the n-well will bias the

base of the vertical pnp.

Therefore there is no need anymore of the current generated by the avalanche of n-

well/p-well to keep on the vertical pnp: the externally seen voltage decreases (and,

hence, we have a NDR region exactly as in ) until a minimum is reached (V ,

typically between 2V and 5V). Now the device has a R in the order of 1-2 , because

the main voltage drop is across to the region between the anode and the cathode, which

is conductivity modulated. Such a low R turns in an extremely low power dissipation

leading to a very high ESD robustness.

Nevertheless, the triggering voltage V corresponds to the breakdown of the n-

well/p-well junction, which is between 40V and 100V, depending on the n-well profile

and substrate doping level. It must be lowered in order to obtain good protection: both

design and process alternatives (MLSCR and LVTSCR) have been proposed to do that.

Actually it is difficult to obtain V below 10V.

T1

HOLD

ON

ON

T1

T1

Figure 3

�

1.II.c Lateral npn

Almost all what said about the ggnMOSt's applies to the lateral npn transistors (R =2-

5 ) and the main difference between the two structures consists in the presence of a

field oxide instead of the gate. This has beneficial effects in terms of gate edge prob-

lems and linear scaling with the width. The main drawback is that the base of the

ON

�

n+

p Substrate+

Rp-wel l

n+

p+

p+

p epi

n-well

p-well

Rn-wel l

Repi

Anode Cathode

Input Output

Figure 5: Cross-section of a SCR (pnpn structure).



transistor (LOCOS) might be very long leading to a higher V . Lateral pnp transistors

have higher on-resistance (R =30 ).

Simple diodes can be used as clamping elements during ESD events in forward

biasing mode, in which they show a low on-resistance (10 ) and a low triggering

voltage V . On the other hand, in reverse biasing mode they are bad clamping elements

because of their high on-resistance (100 ), which leads to a large power dissipation.

In very few cases it is possible to guarantee the needed protection with single

protection elements. More often a protection network is built up to exactly tailor to the

ESD requirements in terms of triggering voltage (V ) and holding voltage (V ). The

strategy to design a protection network can be quite complex. In a basic protec-

tion network is shown: two-stages are separated by an isolation resistor. The first stage

(the primary element) will shunt most of the current during an ESD event and for this

reason the potential candidates for this role are often the devices with the lowest on-

resistance (ggnMOSt's and SCR's). Still, a protection is needed in the early phase of the

ESD stress when the primary element has not been activated yet. This is the function of

the second stage, normally consisting in a small ggnMOSt or a diode. The resistive

element, while the initial ESD stress is clamped by the secondary element (protecting

the eventual gate oxide from breakdown), acts as a load enabling the switching-on of

the primary protection element.

T1

ON

T1

T1 H

�

�

1.II.d Diodes

1.II.e Protection networks

Figure 6

�

Isolation

Resistor

Primaryelement

PIN

��NetworkCircuit toprotect

Secondaryelement

Figure 6: Generical two-stages protection scheme.


Chapter 1 Testing ESD protection elements: how robust are they?

1.III Testing ESD protection elements: how robust are

they?

To assess the robustness of a given protection strategy against ESD much work has

been done in the past years in order to replicate the ESD strike and the caused damage.

According to the modality of the discharge, four different kinds of tests have been

developed.

It represents the discharge of a standing individual through a pointing finger, which

reproduces field failures caused by human handling. It is considered as “the ESD

model” because of its common presence in the daily life in a variety of situations. A

simple RC network describes the Human Body Model ( ): the static energy is

stored in the capacitor C (100pF) that, once the switch is open, can discharge

through the body resistor R (1.5K ) in the device under test. In practice, the HBM acts

like a current source with a rise-time of about 10nsec. and a current peak of 1.3A (for

2KV pre-charge).

The HBM with R =0 and R =500 , can be modeled by using a 4 order lumped

element model which is the highest order that can be analytically solved [14].

Other parasitic elements (C , L and C ) are added in order to account for the interac-

tion between the discharge source and the measurement board: their proper evaluation

is critical to assess reproducible stresses. In particular, the test board capacitance C is

crucial because its discharge occurs at every snapback point in the characteristic,

therefore causing an extra stress to the device under stress.

1.III.a Human Body Model (HBM)

Figure 7

I(V)

BODY

S

S S

S S T

T

�

� � th

DUTCT

CS

LS

C =100pFBODY

R =1.5KS �

Figure 7: RC network and the parasitics describing the HBM model.


Chapter 1 Testing ESD protection elements: how robust are they?

1.III.b Machine Model (MM)

Figure 7

1.III.c Charged Device Model (CDM)

1.III.d Square Pulse Testing

I(V) Figure 8

It represents the discharge of a sitting individual through a metal/low resistive tool

and it reproduces field failures caused by automatic testing. Analogously to the HBM, it

is modeled by an RC network but with R =0. It acts like a current source with a rise-time

of about 10nsec. and a current peak of 3.5A (for 200V stress). Therefore the tester

model is the same as in the case of HBM but with different values of the parasitics.

For instance, C has now a lower influence because R is very small ( ). The

major parasitic is the L because for its different values both the oscillations period and

the current peak will significantly change. Many studies have been carried on the

correlation between HBM and MM tests: it turned out that their comparison is mean-

ingful only if they induce the same failure [15,16,17]. In this case, it has been experi-

mentally verified that V 7…12.5*V .

The Charged Device Model is the most recently introduced test as it represents the

discharge of a charged device to ground through a single device pin: it is therefore a

complete different stress with respect to the HBM and the MM, aiming to reproduce

the real ESD world during handling, working, picking and so on. The rise-time is about

0.5nsec. and the current peak can easily exceed 7-10A. It is very difficult to model

[18,19] because the component and its parasitics vary with position and environment

(humidity, T) and so far a universally recognized standard is not available.

The transmission line pulse testing [TLP, 20] is a very popular method among the

ESD community to assess the robustness of an ESD protection circuits. It simply

consists in a square current pulse generator in which the pulse duration and the pulse

amplitude are respectively determined by the length of the transmission line and by the

pre-charging of the line itself. With increasing the pulse amplitude and averaging the

corresponding clamping voltage across it is possible to deduce the high current ESD-

like characterization in the relevant ESD domain ( ), by exactly unveiling the

trigger (V ) and the holding voltages (V ) of the device under test. Furthermore, after

each zap it is possible to fully characterize the DUT by immediately recognizing even-

tual degradations and therefore showing the maximum ESD stress handling capability.

S

S S

S

HBM MM

T1 H

�


Chapter 1 EOS/ESD induced failure mechanisms and criteria

The compatibility between the TLM and the HBM tests (meaning the same induced

failure) has been assessed with pulse duration of about 100nsec. [21]. In [22] it was

shown that V I (A)*(1.5…2). The TLP test is not compatible with the CDM

because the path of the discharge is different [23].

HBM T2�

ITLM

t

Square pulsegeneration

DUT

V

t

Voltage across DUT

I

t

Current across DUT

V(i)

I(i)

IHigh Current I-V

I(i)

V

;V(i)

Figure 8: Representation of a TLP measurement.

1.IV EOS/ESD induced failure mechanisms and criteria

The current densities associated with an ESD stress unavoidably imply high power

dissipations, with consequent rise in the lattice temperature that often results in thermal

damages. ESD induced failures can be grouped in two categories: soft and hard failures.

The former refers to a partial damage of the device, typically resulting in an increased

leakage that might not meet the requirements for a given logic.

Still, the basic functionalities of the device are operative but without any guarantee

about potential latency effects. So far, soft failures have not been fully understood yet.

Different is the situation about hard failures, whose nature has been deeply investigated

by many authors. They can be mainly distinguished according to three mechanisms:

In the devices based on the bipolar action (either explicit of intrinsic), in the deple-

tion region the temperature can cause a local overheating (due to the high power

dissipation), leading to silicon melt filament. In nMOS devices this filament is typically

located close the surface, where the dielectric acts a thermal insulator. For this reason

1.IV.a Junction burnout


Chapter 1 EOS/ESD induced failure mechanisms and criteria

devices in which hot spots occur deeper in the silicon (like Field Oxide Device, FOD,

where a thick oxide replaces the nMOS thin oxide) are sometimes used.

The relation between the energy of an ESD pulse and the corresponding rise in tem-

perature has been object of great attention in the past years. In particular, through the

analytical solution of the general heat equation combined with some simplifying

conditions on the geometry of the heat source, the following relation between the pulse

power P and its duration t was derived [24,25,26]:

� � Eq.1)ln

0432

1

1

1

1 TTkt

ktktkP ��

�

�

� ��

The curve is therefore split into four regions: the shortest time ( ) corresponds

to the adiabatic heating, in which the heat does not diffuse away from the junction. The

TLP, HBM and MM regimes lie in the logarithmic region. The fourth region corre-

sponds to a quasi-static bias like an Electrical Over Stress, EOS, or DC conditions.

Because of the high temperatures induced by the ESD pulse, a metal line close to a

junction can eventually melt, leading, in the worst case, to a metal open.

In CMOS technology input/output buffers require a protection that clamps the

voltage that, during an ESD event, could cause irreversible failure (rupture) of the gate

oxide. Being the breakdown voltage (V ) the maximum voltage across the protected

device, it is compulsory to maintain a margin between this voltage and the gate oxide

breakdown (BV ) to avoid oxide failures. The gate oxide breakdown (BV ) is a critical

function of its thickness. But with the scaling down of the device sizes, thin-oxides are

also reduced, implying a decrease of the BV . If no extra drain engineering is per-

formed, V can exceed BV . In this situation oxide failures are very likely [27].

On top of the above mentioned, other failure mechanisms can manifest them-

selves, depending on the technology and on the particular protection strategy. By

considering the metallization burnout a rare event, all the possible failure mechanisms

P(t) P t

1.IV.b Metallization burnout

1.IV.c Oxide breakdown

1.IV.d Leakage current as failure criterion

� -1

T1

OX OX

OX

T1 OX


Chapter 1 Motivation of the work

have as a consequence an increase of the leakage current with respect to the devices in

fresh conditions. In [27] a relationship between the increase of the leakage current and

the failure type was assessed. It is therefore possible to use a certain value of the leakage

current as failure criterion for a given device.

This is very handy with the TLP test because after each zaps a quick leakage current

evaluation is performed: when the degradation reaches a certain threshold the device is

considered damaged. It is important to note that this criterion might be quite tricky

[17,28]. In fact, if we look at a typical set of curves after pulses of increasing

severity ( , after [28]) we note that according to the chosen failure criterion the

results are very different. The curve 1 refers to the fresh device, whereas the curve 2

refers to a damage that will pass both tests (1 [email protected] and 1 [email protected]) but still the

device has been undoubtedly damaged. Curve 3 is even more complicated because it

will pass the first test (1 [email protected]) but not the second (1 [email protected]).

It is clear that it is fundamental to keep monitoring the evolution of the leakage current

corresponding to an increasing ESD pulses because a change of the leakage current

surely indicates that some form of damage has occurred.

I(V)

Figure 9

� �

� �

Figure 9: I(V)Typical set of curves afer stresses of increasing severity after [28].

1.V Motivation of the work

As briefly introduced in the previous paragraphs, ESD, in spite of its short name, is

a very broad subject requiring many different (and sometimes incompatible!) skills:

device physics, design of protection networks, testing procedures and failure analysis

are only few of the possible issues concerning ESD. Among them, the knowledge of

the high injection mechanisms taking place during an ESD event in single devices is


Chapter 1 Thesis outline

fundamental to understand and predict the behavior of more complex protection

networks.

Ultra high injection problems have received great attention in the past years, typi-

cally concerning the operating conditions of power devices.

When dealing with devices featuring sub-micron technologies, many issues related to

ultra high injection mechanisms are still open. For this reason, this thesis aims at pro-

viding some more insights into basic structures used in sub-micron technology under

ultra high injection conditions. Since in this regime in very few cases it is possible to

derive analytical solutions, numerical simulations become mandatory as the main

investigation tool.

The final goal is the generation of models that can be implemented in compact-

model simulators to provide reliable simulations prior to committing to silicon.

The organization of the thesis is as follows:

In a general overview of the means that will be used along the entire thesis

to better understand the phenomenon will be presented. First, the basic concepts of

one-type and two-type carriers injection will be introduced. Then, the ambipolar

equations will be derived to point out the limits of the analytical approach. Finally, the

physical models used in our numerical simulations will be outlined with particular

emphasis on the temperature dependencies.

In n-well diffused resistors will be analyzed under various conditions, with

a particular attention to the phenomena that take place under high injection conditions.

It will be shown that, depending on the injection level, the complete characteristic

of n-well resistors can be split into four different regions. The effect of different n-well

doping will be considered and explained. A condition describing the NDR region will

be presented. Transient electro-thermal simulations will be performed to better under-

stand self-heating effects in the high current regime.

In the theory of the P -N -N power rectifiers will be introduced as the

basis for understanding the behavior under high forward voltages of P -N -N sub-

strate diodes. The analytical solutions in the frame of the ambipolar treatment for the

excess of carriers will be derived. Through experiments and 2-D simulations, the limits

1.VI Thesis outline

Chapter 2

Chapter 3

I(V)

Chapter 4+ - +

+ - +


Chapter 1 Thesis outline

up to which the analytical solutions obtained for P -N -N power rectifiers are suitable

for modeling P -N -N substrate diodes under high injection conditions will be derived.

In the behavior of P -N -N substrate diodes under ultra high injection

conditions will be analyzed both numerically and experimentally. It will be shown that

when high injection conditions take place also at the end regions, a new depend-

ence will be found. This dependence will be analytically obtained, modeled and verified

both on numerical simulations and on measured devices. For modeling purposes, an

analytical fitting law matching the characteristic over a broad range of injection

levels will be proposed. Self-heating effects and process/layout variations will be

analyzed too.

In the suitability of the LDMOS transistors designed for medium voltage

applications will be investigated in sight of a use as single ESD protection structure.

Through measurements and 2D simulations the breakdown behavior of the

LDMOSt's will be analyzed and compared with that of the conventional ggnMOSt's. It

will be shown that the Kirk effect is an unavoidable feature of this type of structures.

The consequences of this phenomenon will be investigated. Failure analysis will be

presented in order to confirm the theoretical predictions.

In the clamping voltage of a grounded gate nMOS transistor (ggnMOSt)

under TLP stress will be analyzed in detail by means of a mixed-mode simulator. It will

be shown that the breakdown voltage of the ggnMOSt measured in static conditions

could underestimate the maximum voltage across the protection structure obtained by

TLP stress, depending on the rise-time of the applied pulse. In particular, the smaller

the rise-time, the larger the reached peak of the drain voltage is. It will be shown that

this can attributed to the charging of the overlap capacitance. The influence of the

LDD implant option with respect to the standard implant will be investigated too. The

relationship between the maximum clamping voltage and the triggering voltage of the

parasitic bipolar transistor associated to the structure will be explained. A simple

analytical model describing the response of the device in the early phase of the forced

pulse will be presented.

+ - +

+ - +

+ - +Chapter 5

J (V )

J (V )

Chapter 6

Chapter 7

A A

A A

Chapter 1 References


1.VII References

[1] Merrill, R., and Issaq, E., “ESD Design Methodology”, in Proceedings of 15

EOS/ESD Symposium, EOS/ESD 1993, Orlando, FL, pp. 233-237.

[2] Glenn Wagner, R., Soden, J.M., and Hawkins, C.F., “Extent and Cost of EOS/ESD

Damage in an IC Manufacturing Process”, in Proceedings of 15 EOS/ESD

Symposium, EOS/ESD 1993, Orlando, FL, pp. 49-55.

[3] Welsher, T.L., Blondin, T.J., Dangelmayer, G.T., and Smooha, Y., “Design for

Electrostatic-Discharge (ESD) Protection in Telecommunications Products”, AT&T

Technical Journal, Vol. 69, No. 3, 1990, pp. 77-96.

[4] Rountree, R.N., and Hutchins, C.L., “NMOS protection circuitry”, IEEE Trans.

Electr. Dev., Vol. ED-32, No. 5, 1985, pp. 910-917.

[5] Lin, D.L., “ESD Sensitivity and VLSI Technology Trends: Thermal Breakdown and

Dielectric Breakdown”, in Proceedings of 15 EOS/ESD Symposium, EOS/ESD

1993, Orlando, FL, pp. 73-81.

[6] Polgreen, T., and Chatterjee, A., “Improving the ESD failure threshold of Silicided

nMOS output transistors by ensuring uniform current flow”, in Proceedings of 11

EOS/ESD Symposium, EOS/ESD 1989, New Orleans, pp. 167-174.

[7] Duvvury, C., and Diaz, C., “Dynamic Gate-Coupled NMOS for Efficient Output

ESD Protection”, in Proceedings of 30 IRPS, 1992, pp. 141-150.

[8] Duvvury, C., McPhee, R.A., Baglee, D.A., and Rountree, R.N. “ESD protection

reliability in 1 m CMOS tecnologies”, in Proceedings of 24 IRPS, 1986, pp. 199-205.

[9] Dickson, N., Miller, J., Jackson, M., Kohn, S., Pyle, R., and Tatti, S., “An investigation

into the bake reversible low level ESD induced leakage”, SPIE Vol. 1082,

Microelectronics Manufacturing and Reliability, 1992, pp. 155-166.

[10] Ohtani, S., and Yoshida, M., “Model of leakage current in LDD output MOSFET

due to low-level ESD stress”, in Proceedings of 12 EOS/ESD Symposium,

EOS/ESD 1990, Orlando, FL, pp. 177-181.

[11] Gupta, V., Amerasekera, A., Ramaswamy, S., and Tsao, A., “ESD-related Process

Effects in Mixed-voltage Sub-0.5 m Technologies”, in Proceedings of 20 EOS/ESD

Symposium, EOS/ESD 1998, Reno, NV, pp. 161-169.

[12] Bock, K., Russ, C., Badenes, G., Groeseneken, G., and Deferm, L., “Influence of

well profile and gate length on the ESD performance of a fully silicide 0.25 m CMOS

technology”, in Proceedings of 19 EOS/ESD Symposium, EOS/ESD 1997, Santa

Clara, pp.308-315.

th

th

th

th

th

th

th

th

th

�

�

�



[13] Voldman, S., “ESD Robustness and Scaling Implications of Aluminum and

Copper Interconnects in Advanced Semiconductor Technology”, in Proceedings of

19 EOS/ESD Symposium, EOS/ESD 1997, Santa Clara, pp. 316-329.

[14] Russ, C., Gieser, H., and Verhaege, K., “ESD Protection Elements during HBM

stress-Further Numerical and Experimental Results”, in Proceedings of 16

EOS/ESD Symposium, EOS/ESD 1994, Las Vegas, NV, pp. 96-105.

[15] Kelly, M., Servais, G., Diep, T., Lin, D., Twerefour, S., and Shah, G., “A Comparison

of Electrostatic Discharge Models and Failure Signatures for CMOS Integrated

Circuits Devices”, in Proceedings of 17 EOS/ESD Symposium, EOS/ESD 1995,

Phoenix, AZ, pp. 175-185.

[16] Nikolaidis, T., Richier, C., Reffay, M., Mortini, P., Pananakakis, G., “Influence of

parasitic structures on the ESD performance of a pure bipolar process”,

Microelectronics Reliability, Vol. 36, 1996, pp. 1723-1726.

[17] Notermans, G., de Jong, P., and Kuper, F., “Pitfalls when correlating TLP, HBM

and MM testing”, in Proceedings of 20 EOS/ESD Symposium, EOS/ESD 1998,

Reno, NV, pp. 170-176.

[18] Renninger, R.G., Jon, M.C., Lin, D.L., Diep, T., and Welsher, T.L., “A Field-Induced

Charge-Device Model Simulator”, in Proceedings of 11 EOS/ESD Symposium,

EOS/ESD 1989, New Orleans, LO, pp. 59-71.

[19] Russ, C., Block, K., Roussel, P., Groeseneken, G., Maes, H., Verhaege, K., “A

Compact Model for the Grounded-Gate nMOS Behaviour under CDM ESD Stress”,

in Proceedings of 18 EOS/ESD Symposium, EOS/ESD 1996, Orlando, FL, pp. 59-

71.

[20] Maloney, T., and Khurana, N., “Transmission line pulsing techniques for circuit

modelling of ESD phenomena”, in Proceedings of 7 EOS/ESD Symposium,

EOS/ESD 1985, Minneapolis, MN, pp. 49-55.

[21] Pierce, D.G., Shiley, W., Mulcahy, B.D., Wagner, K.E., and Wunder, M., “Electrical

overstress testing of a 256K UVEPROM to rectangular and double exponential

pulses”, in Proceedings of 10 EOS/ESD Symposium, EOS/ESD 1988, Anaheim,

CA, pp. 137-146.

[22] Amerasekera, A., and Duvvury, C., “The Impact of Technology Scaling on ESD

Robustness and Protection Circuit Design”, in Proceedings of 16 EOS/ESD

Symposium, EOS/ESD 1994, Las Vegas, NV, pp. 237-245.

[23] Gieser, H., and Haunschild, M., “Very-fast Transmission Line Pulsing of

Integrated Structures andthe Charged Device Model”, in Proceedings of 18

EOS/ESD Symposium, EOS/ESD 1996, Orlando, FL, pp. 85-94.

th

th

th

th

th

th

th

th

th

th



[24] Wunsch, D.C., and Bell, R.R., “Determination of threshold failure levels of semi-

conductor diodes and transistors due to pulse voltages”, IEEE Trans. Nucl. Science,

Vol. NS-15, 1968, pp.244-259.

[25] Tasca, D.M., “Pulse power failure modes in semiconductors”, IEEE Trans. Nucl.

Science, Vol. NS-17, 1970, pp.364-372.

[26] Dwyer, W.M., Franklyn, A.J., and Campbell, D.S., “Thermal failure in semiconduc-

tor devices”, Solid State Electronics, Vol.33, 1990, pp.553-560.

[27] Amerasekera, A., Abeelen, W.van den, Roozendaal, L.van, Hannemann, M., and

Schofield, P., “ESD failures modes: Characteristics, Mechanisms and Process

Influences”. IEEE Trans. Electron Devices, ED-39, p. 430-435, 1992.

[28] Amerasekera, A., and Duvvury, C., “ESD in silicon integrated circuits”,

Chichester:Wiley, 1995.

Chapter

Abstract: in the previous chapter it has been explained that ESD causes a complex electro-thermal interaction

that can lead to the destruction of the device through which a discharge occurs. In this chapter a general overview

of the means that will be used along this entire thesis to better understand the phenomenon will be presented.

First, the basic concepts of one-type and two-type carriers injection will be introduced. Then, the ambipolar

equations will be derived to point out the limits of the analytical approach. Finally, the physical models used in

our numerical simulations will be outlined with particular emphasis on the temperature dependencies.

High Injection Basics inSemiconductors

2

Chapter 2 One type carrier injection

- 20 -High Injection Basics in Semiconductors

X=0(cathode)

X=L(anode)

Figure 1: Cross section of the specimen under study with one injecting contact.

2.I One type carrier injection

The knowledge of the current injection theory is a must before tackling any prob-

lem concerning semiconductor devices, typically when dealing with high injection

phenomena. Without going too deep in the theory, a phenomenological approach is

presented such that, in spite of all the approximations, it will furnish an insight of the

physics underlying the carrier injection problems. The problem is taken on through

several degrees of increasing complexity, moving from a one-type carrier injection in

highly idealized materials (which already include most of the concepts) to two types

carrier injection in a semiconductor.

The specimen under study is a “1-D” substrate of length L with contacts (cathode

and anode) in either side ( ). We first focus our attention on one type carrier

injection, which is characterized by only one contact (cathode) capable of injecting

carriers (electrons, but of course the analysis holds symmetrically in the case of injected

holes). The contact is supposed ohmic and taken to be an infinite reservoir of electrons

available for injection, independently on how it is practically possible to realize such a

contact.

The analysis focuses only on the average values of all the involved quantities (free-

carrier drift velocity, electric field intensity and free-trapped charge concentrations):

this procedure works because for planar current flow the spatial variation of these

quantities is limited. Because of that we can consider negligible any diffusive compo-

nent of the current, which is significant only in the immediate neighborhood of the

contacts.

Figure 1



2.I.a Current in a system without thermal free carriers

If on top of the above-mentioned hypotheses, the following assumptions are made:

The substrate is trap free

The concentration of free thermal carriers is negligible

we obtain a highly idealized object very useful to point out some characteristics of the

conduction, which are applicable in more realistic systems also [1]. Under these condi-

tions, ALL the injected electrons by the cathode remain FREE in conduction band and

they all contribute to the space charge.

The current density related to the injection is:

�

�

Eq.1a)electronfreeaofcitydrift veloaverage

ionconcentratchargefreeinjected,average,ewher

��

��

�

��

n

n

vvJ

��

or, equivalently:

The relationships among the parameters introduced in the and

are:

equation 1a equation 1b

Eq.1b)electrodesebetween thelectronfreeaofimetransit t

chargefreeinjectedtotalwhere

��

�

��

TRANTRANt

Q

t

QJ

Eq.2)LQv

Lt

n

TRAN ��

with spacing between cathode and anode. Analogously to the parallel plate condenser

of capacitance , we can expect that and, if the injected charge were

uniformly distributed between the electrodes, its average distance would be at ;

therefore the capacitance would be twice the geometric capacitance of the parallel plate

condenser with charge only on the plates. But since the charge is injected from the

cathode, we might expect a non-uniform distribution with the average distance some-

where between and . Hence it is expected that .

Within a factor 2 of the precision:

L

C (= /L) Q = CV

L/2

L L/2 C < C < 2C

0

0 0

Eq.3)0 VL

VCQ �

� �

��



Combining with the previous equations,

Eq.4)20

L

Vv

L

VvCJ nn ��

But at low field, the electron drift velocity is proportional to the applied field:

Eq.5)and2

V

Lt

L

VEv

n

TRANnnn ��

�

� �

��

Therefore, combining and :equation 4 equation 5

Eq.6)3

2

�

� �

��

L

VJ n�

If we want to obtain the exact solution, we have to consider:

� � � �

� �Eq.7)

equationPoisson

relationCurrent

��

��

�

�

�

xqndx

dE

xExnqJ n

�

Combining we have:

� � � �Eq.8)

dx

xdExEJ n��

Integration of subjected to the boundary condition of vanishing electric

field for yields:

Equation 7

x=0

� � Eq.9)2 2

1

�

� �

��

�n

JxxE

By integrating between and , we finally obtain:0 L

Eq.10)8

93

2

�

� �

��

L

VJ n�

which differs from the approximate solution ( ) only by factor 9/8. Although

the specimen under study was highly idealized the result is very useful because it repre-

sents the highest one-carrier injection current a given material with a given cathode-

anode spacing can carry. It is possible to demonstrate that is still useful at

Equation 6

Equation 9



high fields where the drift mobility is field-dependent so that the drift velocity is no

longer proportional to the applied field.

We now reduce the level of ideality of the specimen under study by considering the

presence of a concentration of thermal free carriers. For very low injection the

average number of injected electrons, , is negligible with respect to . Therefore we

expect Ohm's law to hold:

2.I.b Current in a system with thermal free carriers

n

n n

0

inj 0

Eq.11)0 ��

��

��L

VqnEJ n�

To describe more in detail the characteristics of the conduction in the ohmic regime

and how it relates to the space charge limited (SCL) current regime previously

described, it is important to introduce a fundamental property of any solid closely

related to the conductivity: the dielectric relaxation time.

The dielectric relaxation time represents a measure of the time it takes for charge

in semiconductor to become neutralized by conduction processes [2]. To better under-

stand that, consider a homogeneous one-carrier conductor of conductivity and

permittivity . Imagine a given distribution of the mobile charge density

in space at . If diffusion current is neglected, from the basic

laws of electromagnetism it is known that:

� �

D

(x, y, z;

t=0)=qn (x, y, z; t=0) t=0inj

Eq.12)

�

�

�

��

��

�

��

tJ

ED

D

�

�

�

By combining the above relations, we can write:

Eq.13)��

�

�

��

DEJt

By equating the first and the last term :equation 13

Eq.14)-lnln- 0 tt�

��

��

��


Hence:


where

� � Eq.15)-exp-exp)0()( 0 Dtttt ��

��

��

Eq.16)timerelaxationdielectric0

��n

Dqn �

�

�

But the injected charge at the time , , relates to the applied voltage through

Poisson equation:

t=0 n (t=0) Vinj

Eq.17))0( 2

qLtnV

inj ��

By recalling the average transit time ( ) and inserting we have that:equation 5 equation 16

Eq.18))0(

2

ninjn

TRANqtnV

Lt

�

� ��

By comparing and it is clear that for small applied voltage,

and the dielectric relaxation time is much smaller than the average

transit time . This means that all the injected charge will be “relaxed” by the con-

duction process and, in steady state conditions, there will not be net space charge. This

is the regime in which Ohm's law holds ( ).

By increasing the injection, the condition is reached: in this case the SCL

regime previously analyzed holds. Obviously the injection level at which the SCL

regime takes over the ohmic regime is given by:

equation 15 equation 17

n (t=0)<<n

t

equation 11

n (t=0) >n

inj 0

inj 0

�D

TRAN

Eq.19)0 D0 �� TRANinj tn)(tn

Still, it is important to note that in the SCL regime conductivity modulation takes place

and the dielectric relaxation time is reduced of the same amount as the average transit

time.

Therefore the condition not only sets the onset of the space charge limited

regime but it defines the regime itself [3]. The cross-over voltage from the ohmic

regime to the SCL regime is simply found by equating and the .

�D TRAN= t

V


X



Hence:

2.I.c Current in a system with thermal free carriers and traps

Q V Q = CV

equation 2

equation 3

When traps are also present in the material, the current will be reduced since the

empty traps immobilize some of the injected charge. But the amount of the total excess

charge in the material at any value of the applied voltage must be fixed at .

However, since now a fraction of the injected charge will be trapped, and

become:

Eq.20)9

8 2

0

Lqn

Vx �

where is the average injected trapped charge density (note that we cannot write

anymore). From thermodynamics we know that:

��

J=Q/t

� � Eq.21)VL

CVLQ T �

� �

��

��

where is the effective density of states in conduction band, the traps concentra-

tion, is the energy of the bottom edge of the conduction band, the energy level

of the traps, the Fermi-level at the equilibrium, the Boltzmann's constant and

the temperature in degrees Kelvin. Because of the trapping the current is reduced by a

factor [4]:

N N

E E

E K T

C T

C T

F

�

Eq.22)

ionconcentratsempty trapexp

ionconcentratelectronsfreeexp

��

��

�

��

!"

# ��

��

!"

# ��

KT

EENn

KT

EENn

TFTT

CFC

Eq.23)

�

� �

� ��

��

�

KT

EENN

N

nn

n

CTTC

C

t

�

It is apparent that the cross-over voltage V from Ohm's law to SCL current is also

affected by the factor in a way that:

X

�

Eq.24)2

0

�Lqn

Vx �


When all the recombination centers are filled the current abruptly returns to its

original value given by . Through the simple outlined theory of one carrier

injection, it is possible to have a better insight in some of the injection mechanisms in

which a “one-sign” current is injected in a semiconductor region where it exceeds its

doping level. A typical phenomenon in this sense is given by the “punchthrough” in

transistors [4]. Consider, for instance, an n -p-n transistor in common emitter configu-

ration with a supply voltage of V relative to the emitter.

When increasing the collector voltage, the collector-base depletion region pene-

trates into the base region until it eventually reaches the emitter. In this condition the n

emitter can inject electrons into a depleted base region, with injected electrons flowing

to a positive contact at the collector, which is incapable of holes injection in the base.

Therefore the space charge density of the injected electrons determines the one-sign

current.

By making one contact electron-injecting to the material under study and the other

hole-injecting and applying a voltage of proper polarity it is possible to obtain double

injection, that is, simultaneous injection of electrons and holes, as illustrated in .

Because the injected electrons and holes can largely neutralize each other, a two-carrier

injection current will be larger than either one-carrier current in the same crystal. But

on the other hand, another phenomenon makes its appearance: loss of current carriers

through recombination.

equation 9

Figure 2

+

+

CC

2.II Two-carrier currents

Chapter 2 Two-carrier currents

X=0(cathode)

X=L(anode)

Figure 2: Cross section of the specimen under study with two injecting contacts.


Chapter 2

In fact the injected electrons and holes can mutually recombine before they com-

plete their respective transits between anode and cathode. In indirect gap material such

as silicon, for a wide range if injection levels, the recombination is phonon-assisted, via

deep impurity levels (SRH recombination, [5]). Only at high injection levels a direct

recombination between an electron and a hole accompanied by the transfer of energy

to another free electron/hole is possible (Auger recombination).

It is interesting to have a closer look on how space charge and recombination limit

the current. From the Poisson equation we know that:

The presence of a space-charge implies a finite over the bulk, hence insuring that

a given current be associated with finite voltage . Recombination plays a similar

role: in fact, the continuity equation requires that the electron and hole currents, and

, have nonvanishing divergences. But since in the simplified theory and are pro-

portional to the electric field, nonvanishing divergences imply nonvanishing ,

analogously to the space charge.

A case of particular interest about two-carrier currents is given by the semiconductor

injected “plasma”. The assumptions defining the plasma are the following:

The average injected free electron and hole concentrations are equal and

exceeding the doping level.

The concentrations of localized defect states are assumed small enough that we

can neglect any changes in their occupancies: this implies constant lifetime for

the carriers.

Without losing any generality, we consider the case of plasma injected into an n-type

semiconductor ( ) having the hole-injecting contact at and the electron-

injecting contact at .

Therefore the complete set of equations describing the semiconductor injected plasma

is given by:

E

J V

J

J J J

E/ x

2.II.a The semiconductor injected plasma

n >p x=0

x=L

n

p n p

0 0

� �

�

�

Eq.25)TTOTx

E��

��

Two-carrier currents


Chapter 2

By introducing we can write:b= /�n p�

� � Eq.31)1 EnbqJJJ ppn ��

Multiplying (the second and the third term) by and adding to ,

exploiting the plasma condition ( ) and the local neutrality ( ) and,

finally, inserting from we obtain:

equation 29 b equation 28


n equation 31

� �$ % Eq.32)00 �� nppnq

J

x

EE

��

�

� �

��

which is a first order differential equation. Formally it is the same as . Since the

boundary condition is the same too:

equation 8

� � Eq.33)00 �E

� � Eq.34)8

93

2

00L

VpnqJ np ��

It follows that, analogously, the solution is:

We therefore conclude that the plasma injected into a semiconductor has the same

characteristic as a one carrier in a material without thermal free carriers and traps.

J(V)

Two-carrier currents

� �

� �

��

�

��

�

�

&&'

��

��

��

��

��

��

��

Eq.30)

Eq.29)1

Eq.28)1

Eq.27)

Eq.26),

00

00

, pnpn

rn

pExx

J

q

rn

nExx

J

q

pnpn

EqpJEqnJ

p

p

nn

ppnn

��

��

��

Chapter 2 Analytical approach to injection in semiconductors


2.III Analytical approach to injection in semiconductors

The combination of Poisson equation, continuity equations and the current rela-

tions (that fully describe the time-spatial evolution of all the variables in a system

subjected to external stimulations) represents a formidable set of equations that it is

possible to solve analytically only in few simplified cases. This is the reason for which

very often these equations are tackled numerically. But a numerical solution has the

unavoidable drawback to be physically “obscure”: or better, once performed a simula-

tion there is the problem to assign it a physical consistence.

For this reason many simulations are often performed, varying several parameters.

In this sense numerical simulations are little predictive. It is therefore preferable to

obtain analytic solutions because, even when limited by strong hypotheses, they are

directly tied to the physics of the phenomenon under study.

In this paragraph we introduce an approach to the above-mentioned set of equa-

tions that, under the condition of quasi-neutrality, allows the analytical treatment of

complex phenomena in semiconductors under both low injection and high injection

conditions. This approach, called ambipolar (for reasons that will be clear ahead), has

been introduced for the first time by Roosbroek [6] and it does not include the heat

equation (therefore neglecting self-heating effects) because it would add an enormous

analytical complexity.

If we write the continuity equations for electrons and holes in the steady state case we

have:

��

��

�

��

��

��

��

��

��

��

��

Eq.36)0

Eq.35)0

2

2

2

2

x

pD

x

Ep

x

pEU

x

nD

x

En

x

nEU

ppp

nnn

��

��

Multiplying by and by , we have:Equation 35 p Equation 36 n�p n�

��

��

�

��

��

��

��

��

��

��

��

Eq.38)0

Eq.37)0

2

2

2

2

x

pnD

x

Epn

x

pEnnU

x

npD

x

Enp

x

nEppU

pnpnpnn

npnpnpp

��

��

Since quasi-neutrality must hold we have that


Chapter 2

This condition implies that:

��

��

�

��

��

��

holesinjectedofexcess'

electronsinjectedofexcess'

where''

0

0

00

ppp

nnn

ppnnpn

Eq.39)''

x

p

x

n

x

p

x

n

��

��

��

��

Adding up and and imposing the quasi-neutrality condition in

we have:

Equation 37 Equation 38,

Equation 39,

� � � � � � Eq.40)02

2

��

��

��x

pnDpD

x

ppnEnpU pnnpnpnp ��

dividing by [ ,]:�p np+ n�

� �Eq.41)0

2

2

��

�

��

��

�

��

x

p

np

nDpD

x

pE

np

pnU

np

pnnp

np

np

��

��

��

��

By defining:

� �Eq.42)tcoefficiendiffusionAmbipolar

n ��

��

�

��

�

��

pn

pn

T

n

T

p

p

T

nn

T

p

np

pnp

ApDnD

DDpn

nV

Dp

V

D

nDV

DpD

V

D

np

nDpDD

��

��

Note that it is possible to write as:DA

Eq.43)111

pn

p

Dpn

n

DD npA ��

��

hence is like Matthiessen's rule, a weighted average of the n/p diffusion coefficient

with respect the relative concentration of n/p versus the total concentration. If we

define:

� �Eq.44)mobilityAmbipolar�

�

��

np

pn

np

np

A ��

��

To gain better insight on the bipolar mobility it is possible to rewrite is as:

� � � � � � � �Eq.45)

11111

0000 pn

p

pn

n

pn

p

pn

n

npnpA ��

��

��

��

��

Analytical approach to injection in semiconductors


Chapter 2

It is a sort of averaged mobility made with respect to the net charge and it has the

dimension of a mobility. To understand what it physically represents, we can consider

an n-type semiconductor with cathode-anode spacing L, as in [1].Figure 3

X=0 X=L

pn0 n0

d<<L

n=n +p0

Figure 3 d<<L: Representation of plasma “injected” over a thickness of the specimen, to assess thephysical meaning of the ambipolar mobility [1].

Suppose a plasma “injected” over a thickness , with the plasma otherwise filling

the cross section. The free-carrier concentrations inside the “injected” plasma are “

(for the holes) and “ ” (for the electrons, being the thermal concentration in

the semiconductor). With a voltage applied across the semiconductor, let the electric

field intensity inside the plasma be whereas elsewhere the electric field is

(because of the assumption ). The steady-state currents inside and outside the

plasma must be identical:

d<<L

p”

n=n +p n

V

E V/L

d<<L

0 0

P

� � 46)Eq.00L

VqnEqpEpnqJ npppn ��

Solving for , we obtain:EP

� �$ % Eq.47)0

0 �

� �

�

�(

�)*

��

��

��

L

V

ppn

nE

pn

np ��

�

Referring to , the holes are driven from left to right by the field . At the

advancing front of the hole-motion, the holes moving into a new region of semicon-

ductor are space charge neutralized by the thermal electrons in a time (the ohmic

relaxation time ) assumed short compared to all other significant times in

the problem. At the receding back of the plasma slab the excess electrons are drained

off in a comparably short time. Thus the motion of the holes is simultaneously the

Figure 3 E

= /qn

P

D 0 n� �



Chapter 2

motion of the plasma slab, that is, the plasma or ambipolar drift velocity equals the

hole drift velocity . Then writing:

v

v

a

p

as the definition of the ambipolar drift mobility we obtain:

Eq.48)�

� �

��L

VEv appa ��

� �Eq.49)

0

0

np

pn

pn

a pn

pn

ppn

n

��

��

�

��

��

Therefore the ambipolar mobility physically represents the group mobility for the drift

of the excess under the local field . Strictly speaking it is not a real mobility because

in the case of p-doping its value is negative, being that senseless for a mobility.

If in the we introduce the definitions of ambipolar diffusion coefficient

and ambipolar mobility, we finally obtain the :

p' E

Equation 41

p

Ambipolar Transport Equation

Eq.50)02

2

��

��

Ux

pE

x

pD AA �

Let's now consider how varies accordingly to different injection levels.

By introducing the excess carrier concentration and imposing quasi-neutrality condi-

tion in the definition of the ambipolar mobility, we have:

Equation 50

� � � �� Eq.51)

'''

''

0

0

00

00

pn

n

nnpp

ppnn

np

pn

pnn

np

nnpp

np

np

np

A ��

��

��

��

��

��

��

��

��

�

��

By following the same procedure for the ambipolar diffusion coefficient we obtain:

� � � � � �� Eq.52)

'

'2

''

''

0

0

00

00

pDDDn

DDpn

DpDpDnDn

DDppnn

pDnD

DDpnD

pnn

pn

ppnn

pn

pn

pn

A ��

��

��

��

�

��

Finally, we do the same for the net recombination term. Since for an indirect band-gap

semiconductor, is given by the SRH recombination expression (supposing that

injection is not so high that Auger recombination comes into play):

U

� � � �Eq.53)

'

''

00

2

0

0101

2

+��

'��

��

�� pn

ppn

ppnn

nnpU

pnp

i



Chapter 2

We can now discriminate the two different injection levels.

It is characterized by:

2.III.a Low injection level

Eq.54)0'

0

,n

p

Therefore the three terms , and reduce to:U D�a a

��

�

��

�

�

,

,

,

pA

pA

p

DD

pU

��

�

Eq.55)

'

0

Considering that in these conditions the electric field is very small, the ambipolar

transport equation becomes:

Eq.56)'

0

2

2

p

p

p

x

pD

��

��

and therefore it reduces to the familiar minority carrier diffusion equation.

In this case we have that:

2.III.b High injection level

Eq.57)'

0

+,n

p

��

�

��

�

�

�,

,

��,

+

+

�

�

pU

DD

DDDD

A

pn

pn

A

Eq.58)0

2

Therefore the three terms , and reduce to:U Da a�



The ambipolar transport equation then becomes:

Chapter 2

Therefore the ambipolar treatment allows solving high injection level phenomena in

terms of low injection level equations (with replacing with and with ) giving,

at the same time, a meaningful physical representation.

Numerical solutions of the set of equations defining the behavior of a system

subjected to external stimulations are indispensable when dealing with complex struc-

tures like realistic devices, in which it is impossible to obtain an analytical solution. We

run our simulations by means of “Atlas” by Silvaco [7] but the results we obtained

could have been performed with other software packages commercially available. To

note that, in order to obtain “realistic results”, it is mandatory to figure out which

models should be used to proper represent the behavior of the structure under study.

In particular, when dealing with electro-thermal phenomena like ESD, particular

care must be put in the range of validity of the thermal variables. This is the reason for

which in the following we review the main physical models implemented in the simula-

tor we used.

It is derived from Maxwell's equations and relates the net charge to the electrostatic

potential:

D D

2.IV.a The Poisson Equation

p p p0 A� �

2.IV Numerical approach to injection in semiconductors

Eq.59)'

00

2

2

pn

p

x

pD

��

��

+

� �$ % � �

� �

Eq.60)

materialtheoftypermittivi

chargeelementaryelectron

ionconcentratdopingnet

densitiesholeelectron,,

:throughtorelatedfield,electric

potentialticelectrosta

rewhe

��

�

��

�

�

�

�

�

�

-��-�

�-

��-��

r

q

C

pn

EE

Cnpqr

Numerical approach to injection in semiconductors


Chapter 2

2.IV.b The Continuity Equations

They simply state the conservation charge principle in any possible volume of the

semiconductor:

Eq.61)ratetionion/generarecombinatnet

densitycurrentsholeandelectron,

��

�

��

�

�

��

�

��

�

�

��

�

qRt

pqJ

R

JJ

qRt

nqJ

p

pn

n

R describes the carrier exchange between conduction and valence band in the semicon-

ductor and can be expressed as:

:whereGRRR AUGSRH ��

� �Eq.62)

11

2

ppnn

nnpR

np

iSRH ��

��

��

��

��

�

�

�

�

leveltrapat thewerelevelFermitheifresultingconc.n/pby thegivenconst.,

ionconcentratintrinsic

lifetimeminorityholeandelectron,

11 pn

ni

pn ��

Eq.64)ratesionizationholeandelectron,

densitycurrentsholeandelectron,

��

��

�

��

pn

pnp

pn

n

JJ

q

J

q

JG

� � Eq.63)2

icpcnAUG nnppCnCR ��

1) is the Shockley-Read-Hall recombination for single trap level and is given by:RSRH

where:

2) is the Auger recombination, which is expressed by:RAUG

where and are constants.

3) is the generation due to the impact ionization and is modeled, according to

Chynoweth [8], by:

C Ccn cp

G

n pand are both field and temperature dependent: to represent this dependence we

used the Selberherr model [9], which performs the highest accuracy in the case of high

temperatures.



Chapter 2

2.IV.c Current Relations

They describe the transport of the charge:

Eq.65),,,

,,,

��

��

��

��

TqpDEpqTqpDpqDEpqJ

TqnDEnqTqnDnqDEnqJ

pTpFppTppp

nTnFnnTnnn

��

��

where:

��

�

��

�

�

�

�

�

�

constantsdiffusionetemperatur,

holesandelectronsforlevelsFermi-Quasi,

constantsdiffusion,

mobilitiesholeandelectron,

,,

,,

pTnT

pFnF

pn

pn

DD

EE

DD

��

2.IV.d Mobility

The mobility describes the behavior of the current flow submitted to the driving forces

E and T. The different scattering mechanisms contributing to the mobility can be

combined by using the Mathiessen's rule:

� F,n,p �

/�i iTOT ��

11

where the 's are the mobilities corresponding to the i-th scattering mechanism. In the

case of low field the experimental dependence found by Caughey-Thomas has been

used under the following analytical form [10]:

�i

Eq.66)

3001

300300

300

12

1nn

nn

n

cn

nn

nn

N

N

K

T

K

T

K

T

K

T01

.2

. ��

�

� �

��

��

��

��

��

��

��

� �

��

There exists a similar expression for holes. The first term accounts for the scattering of

charge carriers with acoustic and optical phonons (lattice) whereas the second accounts

for the scattering with impurities (doping). For both terms the temperature range of

validity of the measured data is between 200°K to 450°K [11].



When the carrier concentration becomes very high the carrier-carrier scattering is

accounted through the expression [12]:

Chapter 2

In the case of high field the carrier velocity saturates and the mobility becomes field-

dependent: to provide a smooth transition between low-field and high-field behavior

the following expression is used:

� �Eq.67)

3001045.71ln

3001004.1

31

2

13

23

21

��

�

��

��

� ��

�

� ��

��

npK

Tnp

K

T

CC�

� � Eq.68)

1

1

1

,0

,0,

�

��

��

��

�

�

��

�

�

��

� ��

��

sat

pn

pnpn

v

EE

where is the low-field mobility and is a constant (1 for electrons, 2 for holes). The

temperature dependence of the saturation velocity is expressed by:

� �0n,p

� � Eq.69)

600exp8.01

104.2 7

�

� ��

��

TTvsat

The temperature fitting is up to 430°K [13].

It describes the total transport of heat in the device:

2.IV.e Heat Conduction Equation

� � Eq.70)

generationheat

tyconductivithermal

capacityheat

ewher��

��

�

�

�

�

��

H

K

C

TKHt

TC

The temperature dependence of the thermal conductivity is empirically modeled

with [14]:

K



The range of validity of this dependence extends from 200°K to above 700°K. The

heat generation term has been modeled according to the rigorous thermodynamical

approach followed by Wachutka [15]. In its complete form it reads:

H

Chapter 2

� � Eq.71)1

2cTbTaTK

��

� ��

Eq.72)ppnnp

p

nn

pnnp

p

pp

n

nn

PTJPTJt

pP

TqT

t

nP

TqT

PPTqRJJJJ

H

��

�

� �

��

�

��

�

��

�

� �

��

�

��

��

��

��

��

where and are the thermoelectric powers for electrons and holes. The first two

terms represents the electrons/holes Joule heating rates; the third term is recombina-

tion heat; the fourth and the fifth term are the exchange of electrochemical energy due

to the time changes in carrier concentration.

The last two terms can be written as the sum of two heat contribution: the

Thomson heat, due to the current flowing across a gradient of T and the Peltier heat,

due to the current flowing across a gradient of thermoelectric power under isothermal

conditions. In our simulations the transient terms were not taken into account because

they are normally negligible [16]. To solve the heat equation it is necessary to set a

proper “thermal” boundary condition characterizing “how fast” the heat can flow out

from the semiconductor to the adjacent material. This is done by defining the “thermal

surface resistance ” in the following expression:

P P

R

p n

TH

� � Eq.73)1

ˆ. EXT

TH

TTR

ngradTK ��

In the particular case of thermally insulating surface the right term of the above expres-

sion becomes “0”; in the case of an ideal “heat sink” the condition is applied.

The dependence of the intrinsic carrier concentration on the lattice temperature has a

fundamental importance in ESD phenomena because the high temperature reached

during an ESD event cause a large number of thermally generated carries, which

significantly alter the behavior of the device under study.

In our simulator the intrinsic carrier concentration as a function of the temperature is

modeled in the following way:

T =T

2.IV.f Thermally generated carriers

EXT



Chapter 2

where , and are respectively the effective density of states in the

conduction band, the effective density of states in the valence band and the band-gap

energy.

In this chapter the main “tools” that will be used along this entire thesis were

presented. The main concepts of the injection theory have been outlined. Particular

emphasis has been devoted on the difference between “one-type carrier” and “two

carriers” injection currents with respect to the space charge and the quasi-neutrality

condition. The ambipolar representation in the frame of the drift diffusion model has

been introduced to enhance the possibility of getting analytical solutions to high

injection problems.

Finally, the main physical models implemented in the numerical simulator we will be

using have been reviewed. To note that all the thermal variables involved in the simula-

tions implementing the heat equation have a range of validity which does not exceed

900-1000°K. But in electro-thermal phenomena like ESD, the maximum reached

temperatures are much higher (at the limit of the melting point of the Silicon, 1688°K).

Therefore one does not have to rely too much on simulations were lattice temperature

exceeds 1000°K.

[1] Lampert, M.A., and Mark, P., “Current injection in solids”, Academic Press, New

York, 1970.

[2] Muller, R.S., and Kamins, T.I., “Device electronics for integrated circuits”, John

Wiley & Sons, 2 edition, New York, 1986.

[3] M.P.Shaw, V.V.Mitin, E.Schöll and H.L.Grubin, “The Physics of Instabilities in

Solid State Electron Devices”, Plenum Press, New York, 1992.

[4] Ghandhi, S.K., “Semiconductor Power Devices”, John Wiley & Sons, New York,

1977.

[5] Shockley, W., and Read, W.T., “Statistics of the recombination of holes and elec-

trons”, Phys. Rev., vol.87, p.835, 1952.

[6] Roosbroek, W. van, “The Transport of Added Current Carriers in a Homogeneous

N (T) N (T) E (T)C V G

2.V Conclusions

2.VI References

nd

Eq.74)2

)(exp)()()(

�

� �

� ��

KT

TETNTNTn G

VCi

Conclusions



Semiconductor”, Phys. Rev., 91, 1953, pp. 282-289.

[7]ATLAS, two dimensional device simulation program, Silvaco International, Santa

Clara, USA, 1997

[8] Chynoweth, A.G., “Ionization rates for electrons and holes in silicon”, in Phys. Rev.,

vol. 109, pp.1537-1540, 1958.

[9] Selberherr, S., “Analysis and simulation of semiconductor devices”, Springer-

Verlag, Wien, 1981.

[10] Caughey, D.M., and Thomas, R.E., “Carrier mobilities in silicon empirically related

to doping and field”, in Proc. IEEE, vol. 55, pp. 2192-2193, 1967.

[11] Lombardi, C., Manzini, S., Saporito, A., and Vanzi, M., “A physically based mobility

model for numerical simulations of non-planar devices”, in IEEE Trans. on CAD, vol.

7, no. 11, pp. 1164-1171, 1988.

[12] Dorkel, J.M., and Leturcq, P., “Carrier mobilities in silicon semi-empirically related

to temperature, doping and injection level”, Solid State Electronics, vol. 24, no. 9, pp.

821-825, 1981.

[13] Canali, C., Maini, G., Minder, R., and Ottaviani, G., “Electron and hole drift veloc-

ity measurements in silicon and their empirical relation to electric field and tempera-

ture”, in IEEE Trans. Elec. Dev., vol. ED-22, pp. 1045-1047, 1975.

[14] Glassbrenner, C.J., and Slack, G.A., “Thermal conductivity of silicon and germa-

nium from 3°K to the melting point”, in Phys. Rev., vol. 134, pp. A1058-A1069, 1964.

[15] Wachutka, G., “Rigorous thermodynamic treatment of heat generation and

conduction in semiconductor device modeling”, in IEEE Trans. Elec. Dev., vol. CAD-

9, pp. 1141-1149, 1990.

[16] Kells, K., Muller, S., Fichtner, W., and Wachutka, G., “Simulation of self-heating

effects in a power p-i-n diode”, in Proc. SISDEP-5, 1993, pp. 41-44.

Chapter

Abstract: in this chapter n-well diffused resistors will be analyzed under various conditions, with a particular

attention to the phenomena that take place under high injection conditions. It will be shown that, depending on

the injection level, the complete I(V) characteristic of n-well resistors can be split into four different regions. The

effect of different n-well doping will be considered and explained. A condition describing the NDR region will be

presented. Transient electro-thermal simulations will be performed to better understand self-heating effects in the

high current regime.

Diffused Resistorsunder High Injection

Conditions

3

Chapter 3 Introduction

- 42 -Diffused Resistors under High Injection Conditions

3.I Introduction

Diffused resistors are structures widely exploited in protection strategies against

ESD. At high current level they show a saturated characteristic that acts as a current

limiter. Moreover, in multi-finger protection circuits, in CMOS technology, they may be

integrated into the drain of each finger to ensure uniform triggering of the structure

[1]. Even more important, the extension of the drain contact to poly spacing (the so-

called “ballasting resistor”) in an grounded gate nMOS is known to have a crucial role in

ESD performance [2]: in spite of its importance, the intricate behavior of the ballasting

resistor is not perfectly described.

Given a process the designer must respect ballasting resistors rules to spread the

current as much as possible during an ESD event. But so far the optimal value of these

resistors has been obtained from a trial and error mode approach (slow and expensive)

because of the lack in the correlation between high current and process related parame-

ters. Diffused resistors are subjected to all the main physical mechanisms taking place

during an ESD stress event: velocity saturation, single-double injection, avalanche,

negative differential resistivity regions, self-heating and filamentation. Therefore

diffused resistors have a remarkable didactical relevance too.

For this reason in this chapter an investigation on the behavior of these structures

under high injection conditions will be presented and, based on our results, previous

studies will be critically reviewed. Our study will rely entirely on numerical simulations

on n-well diffused resistors with the physical models introduced in previous chapter.

The simulated structures ( ) are 2-D with constant doping profiles in the y-

direction (1D-like).

Figure 1

X=L(cathode)

X=0(anode)

Lw wI

N-well=10 cm14...18 -3

N =10cm

+ 2 0

-3

N =10cm

+ 2 0

-3

y

x

Figure 1: Cross-section of the n-well resistors under study.



In more realistic structures, there is a p-substrate underlying the n-well: in our

simulations it has been left out because it does not play any role in the behavior of the

structure under high injection conditions. Indeed, a part the fact that the current in

diffused resistors flows mainly laterally, the only relevant 2-D effect is the pinch-off of

the resistor [3] due to the reverse biasing of the underlying grounded p-substrate: by

increasing the anode voltage, the p-substrate/n-well junction is forced into reverse

biasing and the depletion region extends in the n-well, therefore reducing the number

of thermal free carriers available for conduction.

The effect is obviously 2-D because the voltage across the p-substrate/n-well

junction is a function of the position along the axis anode-cathode. But usually, for

ESD purposes, the n-well is highly doped (for reasons that will be clearer ahead) and

hence, the extension of the depletion region is very limited.

Furthermore, we are mainly concerned with high injected currents and the argument

of the pinching (and, therefore, the one of carriers depletion) is irrelevant because

under high injection conditions the current is mainly an excess current and, therefore,

independent of the thermal carriers.

For the sake of clarity the analysis will be carried out for each of the typical four

regions (defined in ) into which it is possible to divide the complete charac-

teristic of a diffused resistor up to ultra high level of injection.

Figure 2 I(V)

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 10 20 30 40 50Vanode (V)

I an

od

e(A

)

1 2

3

4

Figure 2 I(V): Generic characteristic for a n-well resistor showing the typical four regions from lowinjection level up to ultra high injection level.

3.II Region 1: Linear regime

In linear region the electrons concentration due to injection ( ) is much smaller

than the thermal carriers concentration due to the doping of the material. In this

situation the system of equations describing the physical status of the structure is:

ninj

Chapter 3 Region 1: Linear regime


Therefore the material is neutral (no space-charge) and, from Poisson equation, the

electric field is constant from the anode to the cathode and, consequently, the poten-

tial varies linearly. This is the well-known Ohm's law, extensively analyzed in .

The slope of the characteristic depends on the resistivity of the material. More

precisely, the resistance of a sample having length , area and resistivity is:

E

Chapter 2

I(V)

L A �

Eq.2)1

A

L

NqA

LR

Dn

��

�

Note that since is doping dependent, R is not only inversely proportional to the

introduced doping because decreases when increasing the doping (through the

relation expressed in ).

With increasing the injection level a value of the electric field will be reached such

that the mobility cannot any longer be considered constant because it becomes field-

dependent. The drift velocity reaches a saturation value (equal to in our

model, see ) that is independent from the doping level [4]. Note that, because

of the dependence of the mobility with the doping level, also E is doping dependent.

When the injection is such that velocity saturation is reached, it physically means that

the carriers available through the doping in the n-well are not enough to sustain the

injected current. Therefore the limit at which saturation regime takes place is current

controlled and given by:

�n

n

sat

�

Chapter 2

v 2.4*10 cm/sec

Chapter 2

3.III Region 2: Saturation regime

7

sat

Eq.3)0 satDsatsat vqNvqnJ ��

Eq.1)0

0

0

��

�

��

EqnJ

ENnn

n

Dinj

�

�

Chapter 3 Region 2: Saturation regime


Hence, the higher the doping, the higher the current saturation limit, the more

“extended” (in current) the linearity of the resistor. With varying the n-well doping, the

V at which there is the onset of the saturation regime changes: from the simulated

values in one notes that by increasing the doping not only J is increased but also

V does the same. This is not obvious because in one hand, fixed a doping level, a

decrease of current reduces the voltage drop, but in the other hand, fixed a current, a

decrease of doping level increases the voltage drop.

sat

sat

sat

Table 1

ND=1014

cm-3

ND=1015

cm-3

ND=1016

cm-3

ND=1017

cm-3

Jsat (A/cm2) 3.84*10

23.84*10

33.84*10

43.84*10

5

Vsat (V) 1.5 4 6 9

Table 1: J and V as a function of the n-well doping.sat sat

We have, then, to evaluate which of the two effects prevail. This is simply done by

considering:

but

Eq.4)JV ��

from which it follows that:

�Eq.6)

1

Dn NV

��

But given (which is a monotonically decreasing function as N increases) we

have that a decrease in (that is, an increase of the resistivity) causes an increase of

the mobility that results in a reduction of the voltage drop.

The injection of carriers exceeding the saturation limit necessarily implies the

creation of a net space charge. In our particular case, for J >J , a negative excess

charge is stored throughout the resistor such that:

n D

D

(N )

N

D

inj sat

�

Eq.7)sat

inj

Dv

JqN ��

� Eq.5)

being

1

��

��

�

��

�

constvNJ

NN

satD

DDn��


Chapter 3

As shown in , it is already clear that the excess current in the saturation

regime will be space charge limited, partly or completely depending on the doping level.

For this reason it is important to point out the differences between two extreme cases

of resistivity.

We first consider a structure with N =10 cm . Considering the limit for the space

charge limited current the condition n =n =N , we have that (from Poisson) the

average electric field corresponding to this situation is (in the hypothesis that the charge

is homogeneously distributed all along the n-well):

Chapter 2

3.III.a High resistivity structure

D

inj o D

14 -3

Eq.8)V/cm108 3

0 �� xnq

EAVER �

At this value of the electric field, the drift velocity begins to saturate. This fact

represents the main difference between the space charge limited current in silicon with

realistic doping levels and a material without thermal free carriers as seen in . In

silicon, because of the free thermal carriers, it is NOT possible to have pure space

charge limited current because this condition necessarily implies the saturation of the

drift velocity. Hence, beyond the limit for the linear regime (which is

J =qn v =3.84*10 A/cm ) we have that all the injected carriers contribute to the space

charge. In the characteristic is shown: note that the linear regime is very

limited and the conduction is mostly space charge limited.

Chapter 2

Figure 3 I(V)

sat 0 sat

2 2

0.0E+00

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

0 5 10 15 20 25 30Vanode (V)

I an

od

e(A

)

ND=1e14cm-3

Figure 3 I(V): characteristic for the n-well resistor with N =1e14cm .D

-3

Region 2: Saturation regime


Chapter 3

This is clearly confirmed from the evolution at different biasing points of the

carrier's density ( ) and of the electric field ( ). From we have that

the net charge (negative, in this case) is homogeneously distributed all over the bulk,

confirming the estimate in .

Figure 4 Figure 5 Figure 4

equation 8

It follows that the electric field is linearly decreasing from the cathode, where it has

its maximum value (obviously equal to ), and the potential has a quadratic

dependence with the distance.

2V/L

0

2

4

6

8

10

12

14

16

18

20

0 1 2 3 4 5Distance (�m)

log

10

[Co

nc.]

(cm

-3)

Doping

n@8V

p@8V

n@15V

p@15V

n@22V

p@22V

Figure 4 I(V)Figure 3

: Carriers concentration at different biasing points corresponding to the characteristicin in the space charge limited regime.

0.0E+00

1.0E+04

2.0E+04

3.0E+04

4.0E+04

5.0E+04

6.0E+04

7.0E+04

8.0E+04

9.0E+04

0 1 2 3 4 5Distance (�m)

Ele

ctr

icfi

eld

(V/c

m) Vanode=8V

Vanode=15V

Vanode=22V


: Electric field evolution at different biasing points corresponding to the characteristicin in the space charge limited regime.



Chapter 3

This situation is described by the following equations:

Therefore, any increase of injection beyond J will increase the net negative charge

and the slope of the electric field, leading to an increase of its maximum value nearby

the cathode. When this value reaches the threshold for the avalanche (roughly,

), the anode junction begins avalanching, then producing a very large

number of both electrons and holes. Electrons tend to accumulate at the positive

contact of the structure. The holes are drifted toward the negative contact of the

resistor, where they can neutralize the negative space charge due to the injected elec-

trons, then creating a quasi-neutral region.

At this point the structure is split up in two regions with a different behavior as a

function of the injected current. In the first region ( , extended from the anode

onwards) the space charge still slightly increases (and, therefore, the voltage) by increas-

ing the injection and the electron current is space charge limited. Note that in this

region, in addition to the set of , the continuity equation expressing the

avalanche generation of holes and electrons must be incorporated:

sat

E =10 V/cm

region 1

equation 9

AV

5

� � bis)Eq.9nnpp

pn JJx

J

x

J��

�

��

��

In the second region ( , close to the cathode) the space charge decreases (and,

therefore, the voltage) by increasing the injection because of the charge neutralization

due to the holes generated by impact ionization at the anode side and drifted towards

the cathode. In this quasi-neutral region the current is purely drifted (with v smaller

than v ) and due to BOTH type of carriers. Therefore the set of equations describing

the conduction is now:

region 2

d

th

� ��

�

�

��

��

��

0

Eq.10)

, 0

injinj

pinjninj

Dinjinj

pnqE

EqpEqnJ

Nnpn

�

��


� �Eq.9)

00

�

��

�

��

EqnJ

nnqENnn

ninj

injDinj

�

�


Chapter 3

Because of the opposite behavior of the two regions by increasing the injection

level, the voltage across the device will depend on which of the two regions prevail.

More precisely, the voltage across the device will keep increasing until the increase of

the voltage due to the increased space charge in produced by injection is equal to

the decrease of the voltage in where charge neutralization (and, then, quasi

neutrality) takes place. The carrier concentration where this condition holds (approxi-

mately at from ) is shown in where the two regions are well

distinguishable: the arrows indicate the evolution of each region by increasing the

injected current.

region 1

region 2

V=29V Figure 3 Figure 6

12

13

14

15

16

17

18

19

20

0 1 2 3 4 5Distance (�m)

log

10[c

on

c.]

(cm

-3)

n@snap

p@snap

Nd when Jinj

�=0when Jinj

1 2

� 0�

Figure 6: Carriers concentration at the snapback voltage: notice the evolution of the space chargeregion as a function of the injected current.

3.III.b Low resistivity structure

In the case that the structure under study has an highly doped n-well N =1e17cm

and considering the condition n =n =N as the limit for the space charge limited

current, we have that the average electric field corresponding to this situation is:

D

inj o D

-3

Eq.11)V/cm108 6

0 �� xnq

EAVER �

which is un unphysical value, as the breakdown field for Si is about . This

rough analysis presupposes a homogeneous distribution of the net charge all along the

resistor, which is not physically possible.

3*10 V/cm5



Chapter 3

Instead, it is possible that over J =qn v =3.84*10 A/cm some net charge (very

small) will appear. In the characteristic is shown: unlike the previous

analyzed case, a linear regime holding up to is apparent. Beyond this voltage,

saturation velocity takes place by clamping the current at the saturation level.

sat 0 sat

5 2

Figure 7 I(V)

8-9V

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04

3.5E-04

0 10 20 30 40 50Vanode (V)

I an

od

e(A

)

Nd=1e17 cm-3

Figure 7 I(V): characteristic for the n-well resistor with N =1e17cm .D

-3

The clamping is not perfect because over the saturation limit, the small excess

negative charge is too small to force the current in a “full” space charge limited regime,

but large enough to influence Poisson equation. In fact by substituting the net charge in

into Poisson equation it is possible to obtain [5]:equation 7

Eq.12)22L

Av

V

Isat��

��

By comparing the characteristics as a function of the n-well doping in the

range of interest ( ) it is clear how the resistivity of the structure increases in the

saturation regime, moving from the pure space charge limited current behavior

(N =1e14cm ) to the small net charge corresponding to the N =1e17cm .

I(V)

Figure 8

D D

-3 -3



Chapter 3

The role played by the space charge signifies the largest difference between the two

resistive structures: in the evolution of the space charge at different injection

levels is shown.

Figure 9

Starting from , at the edge of the linear region, at the cathode side of the

resistor, a negative space charge region is built up.

V=8V

1.0E+04

1.0E+06

1.0E+08

1.0E+10

1.0E+12

1.0E+14

1.0E+16

1.0E+18

0 1 2 3 4 5Distance (�m)

|Ne

tc

ha

rge

|(c

m-3

)

8V

15V

30V

45V

Jinj

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

0 10 20 30 40 50Vanode (V)

I an

od

e(A

)

1e14

1e15

1e16

1e17

Figure 8 I(V): characteristics up to the snapback point as a function of the n-well doping.


: Space charge evolution at different biasing points corresponding to the characteristicin in the “saturated” regime.



The presence of this space charge region results (from Poisson equation) in a

gradient of the electric field ( ) close to the cathode. But in the region in which

there is virtually no excess of electrons, the electric field (whose gradient is zero) must

increase in order to sustain the increased injected current. Therefore, by increasing the

current in the saturation regime, we have a situation in which the resistor is split up in

two parts.

Figure 10

Chapter 3

In the first region (close to the cathode) the space charge is moving towards the

anode by increasing the injection: in this region the current is space charge limited.

The second region is close to the anode and is neutral: with increasing injection,

because of the pushing of space charge region belonging to the first region, it becomes

more and more narrow and the electric field increases in order to sustain the increased

injected current. In this second region the current is purely drifted.

When the electric field in the region nearby the anode reaches the onset for the

avalanche injection, we have a situation similar to the one previously described for the

high resistivity structure. Once the anode junction begins avalanching, the electrons

produced tend to accumulate at the anode where they contribute to further increase the

electric field, whereas the holes are drifted toward the cathode; here they reduce the

electric field through charge neutralization of the negative space charge.


: Electric field evolution at different biasing points corresponding to the characteristicin in the “saturated” regime.

0.0E+00

1.0E+04

2.0E+04

3.0E+04

4.0E+04

5.0E+04

6.0E+04

7.0E+04

8.0E+04

9.0E+04

1.0E+05

0 1 2 3 4 5Distance (�m)

E.

Fie

ld(V

/cm

)

8V

15V

30V

45V


3.IV Region 3: Negative differential resistivity regime

We have seen how in the saturation regime higher injection necessarily means an

increase of the space charge that results (through the Poisson equation) in an increase

of the voltage. When, for the above-mentioned mechanisms, the electric field is high

enough to cause avalanche injection, a competing mechanism tending to reduce the

total space charge (and, then, the voltage) sets in. At a certain point, the latter mecha-

nism will prevail and the voltage across the structure will reduce. Therefore, the device

shows a region with a negative differential resistivity (NDR) that is, of course, current

controlled.

The maximum voltage reached, prior the NDR takes place, is called “snapback

voltage” or “turn-over voltage” and in is shown as a function of the n-well

doping level. In [6] an attempt to solve analytically the cumbersome system of equa-

tions describing the pre-snapback region has been made and approximate solutions for

the snapback current and voltage were found. Still, a rigorous analytic solution is

lacking. For ESD purposes, semi-empirical models that can be readily implemented in

circuit simulator SPICE-like are very useful [7].

Figure 11

Chapter 3 Region 3: Negative differential resistivity regime


1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 10 20 30 40 50 60VANODE (V)

I AN

OD

E(A

)

10^18

10^17

10^16

10^15

10^14

Figure 11: NDR characteristics as a function of the n-well doping.


Chapter 3

From our simulations it is clear that the current density at which the snapback

occurs ( ) does not depend on the length of the structure, once the n-well

doping is fixed: snapback is a CURRENT CONTROLLED mechanism. This implies

that the snapback voltage is perfectly scaling with the length.

Figure 12

Several authors have tackled the problem of negative resistance behavior in a bulk

semiconductors and insulators. In [8] the case of an insulator with two different inject-

ing contacts and a single set of recombination centers (lying well below the Fermi level,

hence fully occupied by electrons in thermal equilibrium) was analyzed. Because of

dependence of the holes/electrons lifetimes with the injection level (due to the interac-

tion with the recombination centers), a negative resistivity zone could be assessed.

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 10 20 30 40 50 60 70 80 90 100VANODE (V)

I AN

OD

E(A

)

2um

5um

10um

Figure 12 I(V): characteristic for the n-well with resistor with N =1e17cm as a function of the n-well length.

D

-3

10

12

14

16

18

20

0 1 2 3 4 5Distance (�m)

log

10[c

on

c.]

(cm

-3)

n, p @ snapback

n, p @ NDR

n, p @ holding

Figure 13: Carriers concentration at different biasing points in the NDR region of the n-well withresistor with N =1e14cm .D

-3

Region 3: Negative differential resistivity regime


In our case the situation is different: the evolution of the carrier density in the NDR

region is shown in and for both type of resistors showing a similar behavior

for either structures. As the injection increases, the quasi-neutral region is extending

from the anode to the cathode side until a new minimum in the voltage is reached

(“holding voltage”) in which the whole structure is quasi-neutral.

Figure 13 14

Chapter 3

Notice that charge neutrality implies the electron and hole density be nearly equal

and exceeding the background doping meaning that conductivity modulation is an

unavoidable consequence of the NDR regime. But conductivity modulation sets in the

conduction as a two carriers current: therefore we can see the NDR regime (from the

snapback to the holding voltage) as the region in which the current passes from one

type carrier (electrons) to two types carriers. The actual path followed during NDR

region in general depends on the external circuit forcing the regime [9]: in our case, an

ideal current generator is connected to the cathode contact, as this condition the most

similar to what happens during an ESD event.

14

15

16

17

18

19

20

0 1 2 3 4 5Distance (�m)

log

10[c

on

c.]

(cm

-3)

n,p @ snapback

n,p @ NDR

n,p @ holding

Figure 14: Carriers concentration at different biasing points in the NDR region of the n-well withresistor with N =1e17cm .D

-3

Region 3: Negative differential resistivity regime


Chapter 3 Region 4: High current regime

3.V Region 4: High current regime

Once holding voltage is reached all the space charge in the n-well is neutralized by

the holes injection due to the avalanche in the anode region with the above-mentioned

mechanisms. In the electric field distribution for the structure with low

resistivity under ultra high current is shown: the largest part of the n-well has a relatively

small electric field (compared, for instance, with the field in the saturation regime,

) whereas, close to anode junction in the avalanching portion of the structure, the

electric field is very narrow with a peak at the edge of realistic values.

From it is also possible to note that the electrons concentration is exceed-

ing the doping level not only in the well region but also in the N diffusion regions. This

means that in this high current regime the structure is completely conductivity modu-

lated. The current transport is due to both types of carriers and the carriers concentra-

tion is already so high that a higher current can be sustained with a negligible change in

carrier concentration: therefore the resistivity is almost constant and the charac-

teristic is linear.

Figure 15

Figure

10

Figure 15

I(V)

+

0.0E+00

1.0E+05

2.0E+05

3.0E+05

0 1 2 3 4 5Distance (�m)

Ele

ctr

icfi

eld

(V/c

m)

15

16

17

18

19

20

21

log

10

[Co

nc

.](c

m-3

)

Electric field

Net doping

n conc.

Figure 15: Carriers concentration and electric field distribution for the structure with N =1e17cmunder ultra high current.

D

-3


Chapter 3

Since the mechanism of the conductivity modulation has the same modality irre-

spectively of the n-well doping, all the curves (relative to different n-well doping)

show the same dependence ( ).

But given the very high current densities involved in this regime, pure electrical

simulations represent an unrealistic situation because in practice self-heating effects

take place and cause a strong deviation from the isothermal case.

I(V)

Figure 16

0.0E+00

2.0E-02

4.0E-02

6.0E-02

8.0E-02

1.0E-01

1.2E-01

4 8 12 16Vanode (V)

I an

od

e(A

)

1e14cm-3

1e15cm-3

1e16cm-3

1e17cm-3

Figure 16 I(V): High current characteristics as a function of the n-well doping.

Region 4: High current regime


Chapter 3 Non-isothermal conditions

3.VI Non-isothermal conditions

As introduced in , the increase of the lattice temperature due to self-

heating effects causes a significant alteration of the main parameters of the structure

under study. In particular we focus our attention on the dependence of the conductivity

as a function of the lattice temperature. For low injections and negligible self-heating,

the thermal free carriers (due to the doping) represent the carriers available for the

conduction; therefore the conductivity of an n-type substrate with N donors is given

by:

Chapter 2

D

13)Eq.)()( Dn NTqT ��

The mobility decreases quite strongly as a function of the lattice temperature (see

and in ). On the other hand self-heating effects cause a

creation of thermally generated carriers that, at a certain temperature, exceed the

doping level: in this case N must be substituted with the actual value of the thermally

generated carriers. Therefore the conductivity as a function of the temperature shows

two different branches, dependently on which of the two phenomena will prevail: for

low lattice temperatures the reduction of the mobility is not compensated by an equal

increase of the thermally generated carriers, making the conductivity to decrease by

increasing the temperature. But at large lattice temperatures the effect of increasing the

thermal generated carriers will take over the reduction in mobility, making the conduc-

tivity to increase by increasing the temperature.

In addition, in the diffused resistors under study, there is a third phenomenon

characterizing the high current regime and affecting the conductivity: impact ioniza-

tion. In fact, as seen in the previous paragraph, in the high current regime conductivity

modulation takes place, due to the hole-electron pairs produced by the avalanche in the

area close to the anode. But the avalanche phenomenon is itself strongly dependent on

the temperature: in particular, the higher is the lattice temperature the lower is the

efficiency of the process and, therefore, the production of hole/electron pairs.

The lattice temperature is mainly determined by the imposed thermal boundary

conditions. In silicon it is assumed that the heat flow at the surface of the semiconduc-

tor is dissipated at a rate proportional to the excess temperature.

n

D

�

equation 66 equation 67 Chapter 2


Chapter 3

That is:

The thermal surface resistance characterizes “how fast” the heat can flow out

from the semiconductor to the adjacent material and its definition is crucial to properly

model self-heating effects. It has been suggested [10] that a value of the thermal resis-

tance (placed on either contacts side) between 10 K/W and 10 K/W represents a

realistic condition. In a comparison between the isothermal in DC

condition and that with a R =2*10 K/W for the structure with N =1e17cm is

shown.

R

Figure 17 I(V)

TH

3 4

4 -3

TH D

� Eq.14)1

ˆEXT

TH

TTR

ngradTK ��

The linear and the saturated regimes are not affected by self-heating effects: indeed,

when the snapback occurs the maximum lattice temperature in the device is about

T =320°K. When the device reaches the holding voltage, the lattice temperature

starts to increase markedly and with it the resistivity of the device. More precisely, at the

the maximum lattice temperature is T =360°K whereas at the is

T =775°K. The thermal generated carriers (according to the implemented model

introduced in , see ) corresponding to these temperatures are

n (360°K)=8*10 cm and n(775°K)=7*10 cm , hence below the doping level.

SNAP

A

B

i i

point A point B

Chapter 2 equation 7411 -3 16 -3

0.0E+00

2.0E-03

4.0E-03

6.0E-03

8.0E-03

1.0E-02

1.2E-02

1.4E-02

0 10 20 30 40 50Vanode (V)

I an

od

e(A

)

Isothermal

Rth=2e4 K/W

AB

Figure 17: Isothermal DC characteristic vs. non-isothermal with R =2*10 K/W for the structure

with N =1e17cm .TH

D

4

-3

Non-isothermal conditions

Therefore the thermal production of carriers is not the cause for the increased

resistivity. The average carrier densities (supported by the avalanche process) corre-

sponding to the same temperatures are n»p(360°K)=3*10 cm and

n»p(775°K)=6*10 cm . Hence, in this temperature range, there is an increase of the

average carrier density of a factor 2. But in the same temperature range the electron

mobility is falling from (360°K)=754cm /V*sec. to (775°K)=212cm /V*sec.

leading to a decrease of a factor 3.5. Therefore the mobility reduction prevails over the

increased average carrier density, resulting in a higher resistivity.

Note that even when self-heating effects are accounted, the high current regime

does not necessarily introduce irreversible damages: in fact recent studies on n-well

resistors showed how they might reach reversibly a first snapback and a subsequent

high current regime without observing any physical damage [1].

Beyond the in , the temperature is so high that is not possible to find

steady state solutions to the heat equation. To understand the cause for that, transient

simulations have been performed with the same thermal boundary conditions as in the

DC case. The forced current pulse had the same features as a realistic ESD pulse: rise-

time of 10nsec. and duration of 100nsec.

In the transient characteristic for a forced current pulse of 4.2mA/ m is

shown. Note that already at the (t =11nsec.) the resistivity of structure starts

increasing: at this point the maximum lattice temperature is T =478°K.

18 -3

18 -3

2 2� �

�

n n

C

C

point B Figure 17

Figure 18 I(V)

point C


Chapter 3

0

10

20

30

40

50

60

0 5 10 15 20 25t (nsec.)

Van

od

e(V

)

0

1

2

3

4

5

I an

od

e(m

A/ �

m)

Vanode

Ianode

C

D

Figure 18 I(V)

Figure 17

: Transient characteristic for a forced current pulse of 4.2mA/ m andR =2*10 K/W for the same structure as in .

�TH

4



Chapter 3

Beyond this point the lattice temperature and the resistivity keep increasing until the

is reached, where the voltage begins to decrease. The maximum lattice tempera-

ture at the is T =1350°K, which corresponds to a density of thermal generated

carriers n (1350°K)=8.3*10 cm . From the analysis of the carrier's distribution in

structure under study it is clear that at this temperature the thermal generated carriers

prevail over the avalanche generated carriers.

Because of the thermal boundary conditions (thermal insulators at the bottom and

at the top of the structure) and of the electric field distribution, the maximum tempera-

ture is located close to the anode side and is symmetrical with respect to the bottom and

to the top of the structure. Because of that, there is a different concentration of ther-

mally generated carriers in the y-direction also, which implies a decrease of the resistiv-

ity. Hence, the forced current tends to flow where the resistivity is lower by increasing

the LOCAL power dissipation (in fact, beyond the , the GLOBAL power dissi-

pation is decreasing, as the voltage is reduced being the current constant).

point D

point D

point D

D

i

18 3

Figure 19a-b-c-d Figure 19a point D Figure18 Figures 19b-c-d point D .

: Development of a current filament ( corresponds to the inand represent the filament evolution beyond the )

c

b

d

a


This causes a higher temperature and a larger production of thermally generated

carriers in this region: because of the positive temperature coefficient of the latter

phenomenon, the result is that the current is confining into a smaller and smaller area,

where the temperature is getting higher and higher, until a damage occurs. The develop-

ment of the current filament is clearly pictured in (corresponding to the

in ) and in (beyond )

In this chapter diffused resistors have been analyzed under various conditions. It

has been shown that the complete characteristic can be split into four different

regions. In the first region, for low injection levels, Ohm's law holds and the is

linear. By increasing the injection level, the behavior strongly depends on the n-well

doping. For high resistive structures, a space charge limited regime takes place already at

low injection. For low resistive structures space charge plays only a minor role. In both

structures, the electrons drift velocity reaches a saturation value and, as injection

increases, the electric field is more and more confined into a small region close to the

anode. When the threshold for the impact ionization is reached, the generated hole-

electron pairs alter the carrier's distribution in the structure until, after a maximum

voltage (snapback voltage), a current controlled NDR region takes place.

In the NDR region the conduction moves from one-carrier current (electrons) to a

two-carriers current. When a minimum voltage is reached (holding voltage) the struc-

ture is in the high current regime and is now fully conductivity modulated. In this

regime self-heating effects significantly affect the performance of the device with

respect to the isothermal case. In particular, in this regime the resistivity increases

because of the mobility reduction and of the thermal production of carriers. Through

transient electro-thermal simulation it has been possible to assess that when the lattice

temperature is such that the thermal generated carriers prevail over the avalanche

generated carriers, the current crowds into a small filament in which a positive feedback

(due to the positive thermal coefficient of the thermal generated carriers) the tempera-

ture is getting higher and higher, until a damage occurs.

Figure 19a point

D Figure 18 Figures 19b-c-d point D .

I(V)

I(V)

3.VII Conclusions

Chapter 3 Conclusions




3.VIII References

[1] Notermans, G., “On the use of N-Well Resistors for Uniform Triggering of ESD

Protection Elements”. In Proceedings of 19 EOS/ESD Symposium, EOS/ESD

1997, Santa Clara, CA, pp. 221-229.

[2] Rountree, R.N., and Hutchins, C.L., “NMOS protection circuitry”, IEEE Trans.

Elec. Dev., Vol. ED-32, No. 5, 1985, pp. 910-917.

[3] Krieger, G. and Niles, P., “Diffused Resistors Characteristics at High Current

Density Levels Analysis and Applications”, IEEE Trans. Elec. Dev., Vol. 36, No. 2,

1989, pp. 416-423.

[4] Dumke, W.P., “On the additivity of ohmic and space charge limited currents”, Solid

State Electronics, vol.26, pp. 101-103, 1982.

[5] Hower, P.L., and Reddi, V.G.K., “Avalanche Injection and Second Breakdown in

Transistors”, IEEE Trans. Elec. Dev., Vol. ED-17, No. 4, 1970, pp. 320-335.

[6] Caruso, A., Spirito, P., and Vitale, G., “Negative Resistance Induced by Avalanche

Injection in Bulk Semiconductors”, IEEE Trans. Elec. Dev., Vol. ED-21, No. 9, 1974,

pp. 578-586.

[7] Parikh, C.D. and Patrikar, R.M., “A compact model for the N-well resistor”, Solid

State Electronics, vol.43, pp. 683-685, 1999.

[8] Lampert, M.A., and Mark, P., “Current injection in solids”, Academic Press, New

York, 1970.

[9] Shaw, M.P., Mitin, V.V., Schöll, E., and Grubin, H.L., “The Physics of Instabilities in

Solid State Electron Devices”, Plenum Press, New York, 1992.

[10] Amerasekera, A., Chang, M.C., Seitchik, J.A., Chatterjee, A., Mayaram, K., and

Chern, J.H., “Self-Heating Effects in Basic Semiconductor Structures”, IEEE Trans.

Elec. Dev., Vol. 40, No. 10, 1993, pp. 1836-1844.

th

Chapter

Abstract: in this chapter the theory of the P -N -N power rectifiers will be introduced as the basis for

understanding the behavior under high forward voltages of P -N -N substrate diodes. The analytical solutions

in the frame of the ambipolar treatment for the excess of carriers will be derived. Through experiments and 2-D

simulations, the limits up to which the analytical solutions obtained for P -N -N power rectifiers are suitable

for modeling P -N -N substrate diodes under high injection conditions will be derived.

+ - +

+ - +

+ - +

+ - +

High InjectionMechanisms in P -N -N

Substrate Diodes:Theory Validation

+ - +

4


- 66 -High Injection Mechanisms in P -N -N Substrate Diodes: Theory Validation+ - +

4.I Introduction

Substrate diodes are structures commonly present in any protection circuitry

against ESD events and therefore the understanding of their behavior under ultra high

injection level is crucial to properly simulate the effectiveness of a given protection

strategy. In a basic ESD protection element for CMOS technology (a grounded

gate nMOSt with the intrinsic bipolar transistor in evidence) is shown.

The structure formed by the n pad contact, the epitaxial p and the p substrate

contact is called substrate diode”. With respect to a conventional diode the substrate

diode is characterized by a low-doped middle region (defined by the n/p-substrate or

the n/p-well) that can be several microns long (“ ” in ) even in deep sub-

micron technologies.

The substrate diode significantly determines the behavior of the entire protec-

tion network under high injection conditions. In fact, when a negative ESD pulse is

forced at the pad, the diode goes into high forward biasing. High currents can be

sustained under these conditions, hence providing the needed shunt for the stress

current. But since the injected electrons can easily exceed the dope of the epitaxial

region, conductivity modulation occurs in that region and this can affect the neighbor-

ing circuitry.

One must never forget that ESD events are not phenomena limited to a single device,

but, through electrical-thermal coupling, many other structures can be involved. This is

the reason for which the effectiveness of a protection network should be tested with a

compact model simulator accounting for all the neighboring structures, whereas the

Figure 1

2d Figure 1

+ +

Figure 1: Cross section of a CMOS protection structure showing thesubstrate diode and the parasitic bipolar device.

n+

p-Substrate

p+ n

+p

+

VSS PAD VSS

2d

RSUB


Chapter 4 Analysis of P -N -N structures+ - +

intimate behavior of any of them must be investigated through device level simula-

tions. For the sake of completeness, when a positive ESD pulse is forced at the pad, the

diode goes into reverse bias conditions until, eventually, it breaks down and the ava-

lanche regenerative process (involving the parasitic bipolar structure) begins.

Not less important the fact that the study of a substrate diode under high

forward injection conditions is relevant irrespectively of the injection mechanism: in

fact we are dealing with ESD conditions, that is, an ideal current generator. But if we

considered as injection mechanism the “collector”current of the parasitic bipolar

transistor intrinsic in a grounded gate nMOSt or the drain current of a DMOS (double-

diffused) transistor, conceptually nothing would change. Therefore the analysis of a

substrate diode under high injection conditions has a much wider interest than that

specifically related to the ESD protection networks.

To start with the analysis of substrate diodes, in the first part of the chapter the

theory of the P -N -N power rectifiers is detailedly discussed. In fact P -N -N power

rectifiers differ from substrate diodes mainly in the size, which can be easily reduced by

two orders of magnitude in the latter structures. And since P -N -N power rectifiers

were widely used in earlier times their behavior under high injection conditions has

been object of intensive studies [1, 2, 3]. For this reason in the second part of the

chapter a numerical and experimental verification of the correctness of the discussed

theory is presented to check up to which limit it holds.

Since there is no conceptual difference whether the low-doped middle region is

nearly intrinsic, p-type or n-type (high injection conditions force the device to work in

conductivity modulation conditions), the attention is focused on the P -N -N struc-

ture in without any loss of generality.

+ - + + - +

+ - +

+ - +

4.II Analysis of P -N -N structures+ - +

Figure 2

Figure 2: Cross section of the substrate diode under study.

ANODE CATHODE

N-

P+

N+

-d +d-d-WP+ d+WN+x=0

2d

IA



Eq.1)1exp2

tanh

2

��

��

��

��

��

��

�

T

A

ppD

ip

AV

V

L

d

LN

nqDJ

��

�

��

�

�

��

�

�

�

voltagethermalV

holesforconstantdiffusionD

holesforlengthdiffusionL

regionmiddleinionconcentratdonor

T

p

p

q

KT

ND

From now on the N region will be referred as “middle region” or “base”, whereas the

P and the N regions will be referred as “end regions”.

For the sake of completeness, we start considering the behavior of the P -N -N

structure under low injection conditions. When a small forward voltage is applied holes

are injected by the P contact in the middle region where they are minority and where

they recombine. Since the electrons injected by the middle to the P region are negligi-

ble, the current across the device is entirely sustained by diffusion of holes in middle

region where the electric field is zero. The only difference with a standard p-n junction

is the presence of the N -N junction, which leads to an extra voltage drop. In [1] it has

been demonstrated that the relation is expressible as:

-

+ +

+ - +

+

+

- +

4.II.a Low injection conditions

J (V )A A

where

Therefore, it follows the same functional dependence as a standard p-n junction.

When increasing the applied voltage at a certain point the injected holes in the middle

region exceed its doping level: hence, high injection conditions now hold in the middle

region. In order to proceed with the analysis some assumptions are made:

Quasi-neutrality must hold in the middle region and it dictates that an almost equal

concentration of electrons (injected by the N -N junction) be present. Therefore:

4.II.b High injection conditions

�

+ -



��

��

��

��

regionmiddleinionconcentratholesexcess)()()('

regionmiddleinionconcentratelectronsexcess)()()('

:where

)()()(')('

0

0

xpxpxp

xnxnxn

xpxnxpxn

Eq.2))(

)'(

)'(

)(*

*

dn

dn

dp

dp

p

p

��

��

�

�

�

�

�

�

The P -N and N -N junctions have an abrupt profile (step junctions).

On either side of the junctions the carriers are in thermodynamic equilibrium with

the lattice and their concentrations are related to quasi-Fermi levels by Boltzmann

relationships.

Recombination of carriers in the space-charge layers is neglected.

Self-heating effects are not taken into account.

Recombination inside the end regions is assumed negligible (or, in bipolar terms,

the junctions have a “unit injection efficiency”).

+ - - +

This is a consequence of the assumption 3: with reference to , the relation

among the carrier densities on either side of the P space charge region is:

Figure 3+

Because of this relation, when high injection begins to hold in the middle region, it is

reasonable to suppose that the excess of minority in the P region is very small and the

electric field there is negligible. Therefore, only a small current of minority electrons

flows to the P contact whereas the current is carried almost entirely by holes injected

+

+

Figure 3: Detail of the carriers distribution at the edge of the P /N space charge region.+ -

-d*

N-

NA

n(-d')=p(-d')

np0

-d'

n (-d*)p

p (-d*)p

-d

SP

AC

E-C

HA

RG

E



Eq.3)2)(

��

�

�

�

��d

d AA

d

d

A

nqdxnqxUqJ

��

from the P layer into the N region.

At the other side of the structure, in the N -N junction, the converse is true: the

current is chiefly constituted by electrons injected into the middle region with a small

current of minority holes flowing to the N contact.

The main consequence of this assumption is that the recombination in the

middle region (accounting for the difference between the holes injected from the P

contact and those entering the N contact minus the electrons injected from the N

contact and those entering the P contact) DEFINES the current flow. In fact, since

neither electrons nor holes can be considered minority carriers in the middle region, the

current flow cannot be modeled using the minority-carrier transport concept.

+ -

+ -

+

+

+ +

+

If we assume that SRH statistics are the dominant recombination mechanisms in the

middle region and by integrating the recombination rate throughout the entire middle

region, we have that the injected current density can be expressed as ( ):Figure 4

where

Figure 4: Hole and electron current density in the case of recombination taking place ONLY in thebase region.

-d +d-d-WP+ d+WN+

J = +TOT Jp

Jp

Jn{Jn

��

�

�d

d

M xRq

��

�

��d

d

MppMTOT xRqdJdJJJ )()(



��

��

�

�

��

�

regionmiddlein thelifetimeambipolar

regionmiddlein theionconcentratcarrieraverage)(2

1

A

d

d

xxnd

n

�

Eq.4)0)()(

2

2

��

�

A

A

xn

x

xnD

�

��

��

�

��

��

�

lifetimeambipolar

constantdiffusionambipolar2

where

00 npA

pn

pn

ADD

DDD

��

AAA DL �� lengthdiffusionambipolar

Eq.5))()(

22

2

AL

xn

x

xn�

��

From we see that the total current density is proportional to the average

injected carrier concentration implying that a higher injection corresponds to a higher

conductivity modulation.

We now have all the analytical and physical background to deduce the carrier distribu-

tion in the middle region and the voltages all over the structure to calculate the

characteristic.

The transport mechanism in the middle region is characterized by a lifetime and mobil-

ity, which do not correspond to those of the minority carriers because of the simulta-

neous presence of both species of carriers. To account for this phenomenon in

the ambipolar transport equation has been introduced and discussed. Under the

previously described assumptions the transport mechanism in the middle region can be

described by [4, 5]:

equation 3

J (V )

Chapter

II

A A

By introducing:

equation 4 becomes:



� � � � Eq.6)0��

��dx

pppx

pqDdpqdJ ��

� � Eq.7)111

dxdxdxp

p

x

n

nq

KT

x

p

pq

KT

x

p

p

Dd

��

��

��

��

�

� � � � Eq.8)2dx

n

dx

nnnAx

nqD

x

nqDdqndJJ

��

��

��

Eq.9)2 n

A

d qD

J

x

n�

��

Eq.10)2 p

A

d qD

J

x

p�

��

�

To find the boundary conditions to solve the carrier distribution in we can

exploit the hypothesis of unit injection efficiency: at the N -N junction this implies a

vanishing holes current:

equation 5+ -

Hence unit injection efficiency assumption implies the presence of an electric field in

the middle region. The electric field (very small and such to not conflict with quasi-

neutrality hypothesis) needed to reduce the flux of holes is given by:

where the quasi-neutrality condition has been applied. But at the same junction only

electrons carry the current, then we have:

and hence we obtain the first boundary condition:

By applying a similar argument to the P -N junction we obtain the second boundary

condition:

+ -

The solution of with the two previous boundary conditions is given by [2]:equation5



Eq.11)

cosh

sinh

sinh

cosh

2)()(

��

�

�

��

�

�

��

��

��

��

�

��

��

��

��

��

A

A

A

A

A

AA

L

d

L

x

B

L

d

L

x

qL

Jxpxn

�

1

1

1

1

��

��

��

b

bB

p

n

p

n

��

��

� � � � � � � �x

nKTxqn

x

pD

x

nDqxpnqxJxJxJ pnpnpnpnpnA �

��

��

��

��

�� )()()()(

where

The distribution in is pictured in : notice that in the case of equal

mobility's (B=0) the distribution is symmetrical.

equation 11 Figure 5

To find the voltage drop in the middle region, we need to integrate the electric field

in this region. The electric field distribution can be extracted by the current density

equation at any point between and :

V

x -d d

M

Figure 5 equation 11: Plot of the distribution in as a function of the parameter B.

5.0E+18

7.0E+18

9.0E+18

1.1E+19

1.3E+19

1.5E+19

1.7E+19

-1.0E-03 -5.0E-04 0.0E+00 5.0E-04 1.0E-03

Distance (�m)

co

nc.

(cm

-3)

B=0

B=0.33

B=0.5



Eq.12))(

)(x

n

qn

KTB

qn

Jx

pn

A

��

��

��

�

tanh1

tanh1

lnsinhtanh1

tanh1

sinh

)1(

8

2

2

22

22

2

��

�

�

��

�

�

��

� �

��

� �

��

��

��

��

��

�

��

��

��

� �

��

��

��

� �

��

�

��

A

A

AA

A

A

M

LdB

LdB

BL

dL

dBarctg

LdB

Ld

b

b

q

KTV

Eq.13)exp)( 0 �

��

��

KT

qVpdp P

n

from which we can deduce the electric field strength (under quasi-neutrality hypothe-

sis):

The first term represents the “ohmic” contribution whereas the second accounts for

the different mobility's. Integration between and gives the voltage drop in the

middle region [3]:

d +d

Note that V is independent from the injected current and only depends on the two

parameters and : high current can ideally be sustained without any increase of

the voltage drop. This is the reason for which these structures were used as power

rectifiers.

To find the final we need to express the voltage drop across the space charge

regions as function of carrier concentration.

M J

(d/L ) b

J (V )

A

A

A A

With reference to , we can write:Figure 6

Figure 6: Carrier distribution in the case of high injection conditions in the base region and lowinjection at the end regions.

-d +d-d-WP+ d+WN+

N =n-

n 0

N =nD n 0N =pA p 0

p(-d)

np 0 pn 0pn 0

n(d)



��

��

� ��

�

� 2

)(ln

i

Pn

Ndp

q

KTV

��

��

� ��

��N

dn

q

KTVN

)(ln

Eq.14))()(

ln2 �

�

��

� ��

i

NPn

dndn

q

KTVV

��

��

�

�� NPMA

MA

VVVV

JJ

Eq.15)2

exp2

�

��

��

� �

KT

qV

LdF

d

nqDJ A

A

iAA

where is the minority carrier density in the middle region at zero current. Then the

voltage drop across the P -N junction is:

pn0

+ -

Analogously for the N -N junction:- +

By imposing once again the condition of quasi-neutrality, the total voltage drop due to

the space charge regions is:

We now have all the elements to obtain the final ; in fact:J (V )A A

The combination of , and [3] gives:equation 5 12 14

where is a complex function depending only on structural parameters. Then,

from a functional viewpoint, the structure shows the same dependence as a conven-

tional diode under high injection conditions.

When further increasing the injection level, it is not possible to consider the assumption

of unity injection efficiency of the end regions valid anymore. In other words, the

recombination currents in these areas become relevant with respect to the total current.

From a physical viewpoint, it simply means that the holes injected by the P -N junction

do not entirely recombine in the middle region before reaching the N -N junction in

which they become minority carriers. An analogous condition is verified for the elec-

trons injected by the N -N junction. To quantitatively evaluate the process, we can

F(d/L )A

+ -

- +

+ -



Eq.16))(

)'(

)'(

)(*

*

dn

dn

dp

dp

p

p

��

��

�

! " Eq.17))'()(2* dndnN pA ��#

! " Eq.18))'()(2* dndnp �$�

! " Eq.19))()(2

dndnp �$�

� � � � � � � � � � Eq.20)dJxxn

dJdJJdJJ pN

d

d A

nPpNMnPA �

�

��

once again to refer to : the application of Boltzmann statistic at the edge of the

P -N junction space charge region dictates that:

Figure 3+ -

In the case of low injection level in the P region and by applying quasi-neutrality:+

and then:

with a negligible error:

Then the diffusive component of the electron current density at the point (quanti-

tatively defined by the term in the left side of increases quadratically with the

injected carrier density in the middle region. A similar reasoning applies to the N -N

junction. Therefore, although it may sound odd, the total injected current can be

expressed by adding up the three following contribution:

x=-d

equation 19+ -

To better understand the concept, with reference to the recombination currents in the

three different regions ( ), it is useful to imagine the middle region playing the

role of “stretched” depletion region (where recombination occurs) in a conventional

p-n junction: therefore the total current is found by adding up the purely diffusive (end

regions are neutral) current densities at either side of the depletion region and the

recombination current in the middle region.

Figure 7



Eq.21)expexp

tanh

0�

��

��

��

��

�

�

��

�

�

��

��

� �

��

�

��

��

KT

qVJ

KT

qV

L

WL

nqDJ P

satnPP

nP

PnP

pnP

nP

��

�

��

�

�

�

�

�

�

�

��

��

��

regionPin themequilibriuat theionconcentratelectron

regionPin theelectronsforconstantdiffusion

regionPin theelectronsforlengthdiffusion

regionPtheoflength

0p

nP

nP

P

n

D

L

W

Since the expression of current density in the middle region does not change because

of the presence of others current components ( is still valid), to further

proceed we need to express the diffusion currents J and J as a function of the

injected carrier density in the middle region.

This is simply done by applying the low injection theory and assuming the case of a

“short-base” diode because in the considered structure end regions are “short”. The

electron current density J in the P region is then given by:

equation 3

nP+ pN+

nP+

+

where:

Figure 7: Hole and electron current density in the case of recombination taking place all over thestructure.

-d +d-d-WP+ d+WN+

J = +TOT Jn

JpN+

JnP+

Jp

� � � �dJJdJJ pNMnPTOT ��

{ {



Eq.22)exp �

��

� ��

KT

qVJJ N

satpNpN

! " Eq.23)expexp)()()( 2

0

2�

��

��

��

��

KT

qVn

KT

qVnNdndpdn P

iP

pApp

Eq.24)n

n(-d)exp

2

i

��

��

��

��

� ��

�� satnPP

satnPnP JKT

qVJJ

Eq.25)n

d)n(2

i

��

��

� �� satpNpN JJ

nJM $

! " ! " Eq.26))(and)( 2222ndnJndnJ pNnP $$$�$ ��

Similarly, at the other junction the hole current density J in the N region is given by:pN+

+

By making use of and the diode law:equation17

Combining with we obtain:equation 21

Similarly, the holes current density in the N region is given by:+

Remembering from that depends linearly from the average injected current

in the middle region:

equation 3 JM

we now have:

Then and depend quadratically on the average injected current in the middle

region. When these terms become of the same order of magnitude of the recombina-

tion current in the middle region, it follows that also the total injected current must have

a quadratic dependence from the average injected current in the middle region. But

J JpN+ nP+



��

��

�

�

�

�

�

satN

satP

J

Jb

n

s

regionmiddlein theionconcentratinjectedaverage

� � Eq.27)2

DAA VVJ �$

Eq.28))()( 22

,

22

, iepAienAAUGER pnnpCnnpnCU ��

! " Eq.29))(3

xnCU AAUGER �

since J is still proportional to , this implies that in the middle region the current is

carried more and more as a drift current: this is possible because from the

electric field scales with the average injected current.

Herlet [3] showed that by expressing all the involved quantities (J , J , J , V , V and

V ) as function of the parameters:

M

N+ P+ M N+ P+

M

n

equation12

it is possible to obtain a new dependence, which reads:J (V )A A

where is the voltage drop across the end regions for the zero current case (built-in

voltage).

Without going too much in detail in the rather complicated analytical approach pre-

sented in [6], the main reasoning for the bending of the characteristic from the

to the dependence is the following.

When the diffusion currents at the end regions become comparable with the recombi-

nation current in the middle region, the contribution to the conductivity modulation in

this region will be decreased for a given injected current and, then, the voltage drop

across the structure increased.

When the injected carrier density in the middle region becomes very high, it is reason-

able to suppose that Auger recombination comes into play. The Auger recombination

term is implemented through ( ):

V

J (V )

exp(V /2V ) (V -V )

4.II.c Auger recombination

Chapter 2, equation 111

D

A A

A T A D

2

In the case of quasi-neutrality this term reduces to:



Eq.30))(

A

SRH

xnU

��

Eq.31)1

)(AAC

xn�

�

! " Eq.32))()()( 3

2

2

xnCxn

x

xnD A

A

A ��

��

Eq.33)'

)(

1

00

�

��

��

��

��

�� m

L

xxcnnxn

)12('and1

12

2

0

2

0

��

��

��

� mDLnC

nC

m AA

AA

AA

��

�

By equating this term with the SRH recombination for the case under study:

we find that the carrier concentration at which Auger recombination prevails is:

By setting C =1.210 cm /sec. and =6.6610 sec, we obtain n(x)=210 cm , value

at which Auger recombination sets in and the does not hold anymore. To find

out the carrier distribution in the middle region in this case one should solve:

A A

. -31 6 . -8 . 19 -3�

equation 4

A solution for this differential equation has been obtained [6]:

where is the jacobian elliptic function of argument . The parameter and the

modified diffusion length are given by:

cn(u|m) u m

L'


Chapter 4 Simulations vs. measurements under high injection conditions

4.III Simulations vs. measurements under high injection

conditions

In the theory presented in the previous paragraph it has been outlined that the

characteristic of a P -N -N structure under high injection conditions can be

deduced from the recombination currents relative to each region. According to

whether or not the recombination in the middle region represents the main contribu-

tion to the total injected current, different current-voltage dependences were found.

The fundamental hypothesis under which the theoretical approach holds is the

presence of low injection at the end regions (that is, a negligible electric field implying

that the current is mainly carried by diffusion). This is certainly the case for power

structures, since the average electric field is quite small along the entire device. But for

the P -N -N substrate diodes of our interest this is not true anymore because of the

much shrunk dimensions. In the coming section the introduced theory will be both

numerically (through the investigation of the main parameters at different biasing

points) and experimentally verified on P -N -N substrate diodes in order to check out

up to which limit it can be applied.

The “exemplary” structure on which numerical simulations were performed (with

reference to shown once again for convenience's sake) has the following

characteristics:

The end regions P and N are doped with N =N =10 cm and they have a length

W =W =0.2 m.

The middle N region has N =10 cm and a length =5 m.

The carrier lifetime is set to =10 sec.

J (V )

Figure 2

2d

A A

+ - +

+ - +

+ - +

+ + 20 -3

- 17 -3

-7

�

�

�

A D

P+ N+

BASE

0

�

�

�


ANODE CATHODE

N-

P+

N+


2d

IA


Chapter 4

Simulations were performed in DC conditions for anode voltages V up to 1.6V. Self-

heating effects were not taken into account.

By comparing the electrons and the holes concentration for the shown biasing points

( ) we can note that:

Already for V =1V the injected carriers in the middle region are exceeding the

background doping level and, then, high injection conditions hold in this region.

Holes and electrons concentration verifies quasi-neutrality in the middle region; it is

also possible to verify that their profiles are in good agreement with the distribution

shown in .

The carrier concentration on either side of the space charge regions can be

described in terms of Boltzmann relationships.

The assumption of short-base diode is correct, as it was predictable from the short

length of the end regions.

A

A

4.III.a Carriers concentration

Figure 8

Figure 5

�

�

�

�

Figure 8: Electrons and holes concentration for V up to 1.25V.A

1.0E+17

1.0E+18

1.0E+19

1.0E+20

0 1 2 3 4 5Distance (�m)

Ele

ctr

on

s/h

ole

sc

on

c.

(cm

-3)

Doping

n@V=1V

p@V=1V

n@V=1.25V

p@V=1.25V

Simulations vs. measurements under high injection conditions


Chapter 4

4.III.b Electric field and potential

Figure 9

Figure 10

By looking at the electric field distribution ( ) we can confirm that the electric

field in the middle region scales with the average number of injected carriers, as we

would expect. Note also that the electric field increases in the end regions. This turns in

an additional voltage drop, as we can verify on the potential plot ( ).

To better understand this graph, it is better to consider the relationship between the

applied and the built-in voltage.

Figure 9: Electric Field distribution for V up to 1.25V.A

Figure 10: Potential distribution for V up to 1.25V.A

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

0 1 2 3 4 5Distance (�m)

Ele

ctr

icfi

eld

(V/c

m)

V=1.25V

V=1V

V=0.1V

-0.5

0.0

0.5

1.0

0 1 2 3 4 5Distance (�m)

Po

ten

tial(V

)

V=0.1V

V=1V

V=1.25V



Chapter 4

V99.0ln2

��

��

�%

�

��

i

A

NP n

NN

q

KT

V178.0ln ��

��

�%��

N

N

q

KT D

NN

V168.1ln2

2

��

��

�%�%�% ��

i

A

NNNPBIn

N

q

KT

V9.0)'(

ln2

��

��

��

�

�i

Pn

Ndp

q

KTV V087.0

)'(ln

2��

��

��

i

Nn

dn

q

KTV

In the zero bias condition the built-in voltage is obtained by adding up the two built-

in voltages relative to P /N and N /N junctions. That is:

%BI

+ - - +

and

then,

Note that if the middle material were intrinsic, the built-in voltage would be equally

distributed on either side (0.584V). The application of a forward voltage lowers the

built-in voltage; in particular for V =1V, we have that:A

Since the average electric field in the middle region is 2.510 V/cm the voltage drop

across this region is V =0.0125V.

Then we have:

V =V +V +V =0.9+0.087+0.0125=1 V,

exactly the applied voltage, which means that the end regions are still neutral. In partic-

ular the applied voltage lowered the potential barrier to 0.091V on either junctions

(0.99-0.9=0.178-0.087=0.091V).

Similar results can be obtained for V =1.25V but in this case the potential barrier is

reduced to 0.031V on either junctions and there is the onset of a voltage drop in the end

regions (this could be clearly seen also on the electric field plot).

. 1

M

A P+ N+ M

A



Chapter 4

Eq.3)2)(

��

�

�

�

��d

d AA

d

d

M

nqdxnqxUqJ

��

� � � � Eq.35)

tanh

)(andEq.34)

tanh

)( **

**

��

��

�

��

��

�

��

�

�

��

�

�

��

pN

Np

pN

pN

nP

Pn

nPnP

L

W

dpLqdJ

L

W

dnLqdJ

��

4.III.c Recombination currents

V

Table 1

equation 3

Since for up to 1.25V in each region the values of the electric field are small, we have

that the current should be mainly due to recombination. To confirm this, in a

comparison between the simulated recombination currents in each region and the

analytically calculated values for different biasing points is shown. The recombination

current in the middle region is calculated by making use of :

A

whereas the end regions currents are evaluated through (assuming a “short base” diode

profile):

From we can clearly state that the recombination provides almost all the current.

In addition by comparing the recombination currents in the three different region for

V =0.7V and V =1V, we have that in the first case the structure behaves as a conven-

tional p-n junction (the recombination in the middle region prevails over the one at the

end regions). But for V =1V the three components become of the same order of

magnitude. This two facts leads to the conclusion that in this range of biasing we are in

the case analytically analysed in the previous paragraph [1, 2, 3].

Table 1

A A

A

Table 1: Simulated and calculated recombination currents in the three regions.

VA (V) InP+ (-d) IREC Middle (A) IpN+ (d) ITOT (A)

0.7 Sim. 5.20E-13 2.20E-08 3.40E-13 2.30E-08

Calc. 3.90E-13 2.12E-08 2.90E-13

1 Sim. 3.60E-05 7.20E-05 2.60E-05 1.38E-04

Calc. 3.41E-05 5.60E-05 2.49E-05



Chapter 4

4.III.d Simulated I (V ) characteristic

I (V )

Figure 11 I (V )

V/V

V/2V

A A

A A

A A

T

T

Since the relationships among the physical parameters for the studied structure

are both functionally and quantitatively well in agreement with the analytical treatment

presented so far, one would expect the simulated characteristic to follow the

theory. And in fact, as pictured in , the simulated characteristic up to 2V

clearly shows the three different dependencies: for low injection levels a standard

characteristic is found. As the injection increases the dependence bends to a

[2] at around V =0.8V. Finally, at about 1V, the quadratic dependence [3] takes

place. The fitting is very good but it is immediately noticeable that at 1.6-1.7V it starts

diverging from this law.

A

4.III.e Experimental verifications

Figure 12 I (V )

I (V )

Several substrate diodes have been measured up to the same range of injection of the

simulated devices where self-heating effects are not supposed to play a major role. In

a typical characteristic is shown. As it possible to see, the situation is

very similar to the simulated one. The quadratic law is perfectly fitting the measured

till 1.5V.

A A

A A

Figure 11 I (V ): Fitting of the simulated characteristic up to 2V.A A

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 0.4 0.8 1.2 1.6 2

VANODE (V)

I AN

OD

E(A

)

Sim. 5 um

V/VT fitting

V/2VT fitting

Quadratic




4.IV Conclusions

4.V References

In this chapter the applicability of the theory of P -N -N power rectifiers to substrate

diodes, structures virtually present in any ESD protection strategy, under high injection

conditions has been verified.

Through numerical simulations and experimental verifications it has been possible to

assess the suitability of the above-mentioned theory to substrate diodes for applied

voltages up to 1.6-1.7V.

It has been shown how in such structures the transport mechanism is mostly due to

recombination. According to whether the main contribution to recombination is in the

middle region (where high injection occurs) or in the end regions (where low injection

level is still present), different characteristics have been found.

[1] Hall, R.N., “Power Rectifiers and Transistors”, Proc. IRE, vol. 40, 1952, pp. 1512-

1518.

+ - +

J (V )A A

Figure 12 I (V ): Fitting of the measured characteristic up to 2V.A A

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 0.5 1 1.5 2VANODE (V)

I AN

OD

E(A

)

Measures

Quadratic fitting

V/VT fitting

V/2VT fitting



[2] Howard, N.R. and Johnson, G.W., “P -i-n Silicon Diodes at High Forward Current

Densities”, Solid State Electronics, Vol. 8, 1965, pp. 275-284.

[3] Herlet, A., “The Forward Characteristic of Silicon Power Rectifiers at High Current


[4] Roosbroek, W. van, “The Transport of Added Current Carriers in a Homogeneous

Semiconductor”, Phys. Rev., 91, 1953, pp. 282-289.

[5] Ishaque, A.N. et al., “An extended ambipolar model: Formulation, analytical investi-

gations, and application to photocurrent modeling”, J. Appl. Phys., vol. 69, 1991, pp.

307-319.

[6] Baliga, B.J., “Power Semiconductor Devices”, Krieger Publishing Company, 1995.

+ +

Chapter

Abstract: in this chapter the behavior of P -N -N substrate diodes under ultra high injection conditions will be

analyzed both numerically and experimentally. It will be shown that when high injection conditions take place

also at the end regions, a new J (V ) dependence will be found. This dependence will be analytically obtained,

modeled and verified both on numerical simulations and on measured devices. For modeling purposes, an

analytical fitting law matching the J (V ) characteristic over a broad range of injection levels will be proposed.

Self-heating effects and process/layout variations will be analyzed too.

+ - +

A A

A A

P -N -N SubstrateDiodes under Ultra

+ - +

HighInjection Conditions

5


- 90 -P -N -N Substrate Diodes under+ - +

Ultra High Injection Conditions

5.I Introduction

In the previous chapter the theory of P -N -N power rectifiers has been

analyzed to verify whether it could properly describe the behavior of P -N -N sub-

strate diodes under high injection conditions. Through numerical simulations and

experimental verifications it has been possible to assess the suitability of the above-

mentioned theory to substrate diodes for applied voltages up to 1.6-1.7V. In fact, up to

this range of biasing in such structures the transport mechanism is mostly diffusive.

Depending on where contribution to recombination takes place (middle region or end

regions), different characteristics were found: when the injected current is

mainly sustained by the recombination in the middle region, a dependence propor-

tional to is found. But increasing the injected current, the contributions

of the diffusive components at the end regions come into play and the character-

istics bends to a dependence proportional to , where is the built-in voltage.

In this regime high injection conditions hold in the middle region, whereas low

injection is still characterizing the end regions. But ESD events could force the device

into an even higher injection level characterized by an high electric field all over the

structure: in this case low injection conditions at the end regions are not verified any-

more and a different characteristic is expected. The main goal of this chapter is

to study and to model the new characteristic.

The exemplary structure on which the numerical analysis will be focused (

) is the same as that introduced in . It consists of two highly doped "end"

regions (P and N , with N =N =10 cm and with a length of 0.2 m) in the middle of

which there is the "base" N region (with N =N =10 cm ) 5 m long. The carrier

lifetime is set to =10 sec. Other process and layout variations (middle region length

and doping, lifetime, end regions length and doping, carrier-carrier scattering) will be

considered during the chapter. Self-heating effects will be considered ahead.

+ - +

+ - +

+ + 20 -3

- - 17 -3

-7

J (V )

exp(V /2V )

J (V )

(V -V ) V

J (V )

J (V )

Figure

1 Chapter IV

A A

A T

A A

A D D

A A

A A

2

A D

BASE

0

�

�

�


ANODE CATHODE

N-

P+

N+


2d

IA



Chapter 5 Simulations vs. measurements under ultra high injection conditions

5.II Simulations vs. measurements under ultra high

injection conditions

5.II.a Measured and simulated I (V )

I (V ) Figure 2

Figure 2

A A

A A

Several devices were measured up to very high forward biasing in DC condi-

tions: a typical measured characteristic is pictured in . Note that the

device suffered of an irreversible damage for V =3.2V (corresponding to an

I =0.55A). From it is apparent that the quadratic dependence is not valid

beyond 1.6-1.7V (corresponding to an I =200mA). On the other hand, thermal effects

cannot be considered playing a major role in the deviation from that dependence

because, from the failure analysis of the measured devices, the location of the damage

was always “outside” the device (typically resulting in a melting of thin metal lines).

It is also clear that DC measurements for very high forward voltage are prob-

lematic due to presence of many limiting factors (high dissipated power, quality of the

contacts and metal lines melting) and pulsed measurements become mandatory.

A

A

A

The same results as in the measurements were found when simulating the

characteristic for applied voltages up to 5V ( ): once again, the quadratic depend-

ence is well in agreement with the simulated characteristic up to the same applied

I (V )

Figure 3

A A

Figure 2 I (V ): Measured characteristic under DC conditions up to the destruction of the device.A A

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3VANODE (V)

I AN

OD

E(A

)

Quadratic fitting

DC Measurement



Chapter 5

voltage as in the measured case. Afterwards, a sub-quadratic dependence takes place. In

order to figure out which and why, the main simulated physical parameters in the range

of interest are analyzed.

In the holes concentration for several biasing levels is shown. When passing

from V =4V to V =5V, the holes concentration in the middle region changes only very

slightly (notice that from V =1V to V =1.25V, the carriers concentration in the middle

region changes of a factor 10).

5.II.b Carriers concentration

Figure 4

A A

A A

Figure 3 I (V ): Simulated characteristic for V up to 5V.A A A

Figure 4: Holes concentration in different biasing points for V up to 5V.A

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

Quadratic fitting law

Simulated

1.0E+17

1.0E+18

1.0E+19

1.0E+20

1.0E+21

0 1 2 3 4 5Distance (�m)

Ho

les

co

nc.(c

m-3

)

V=5V

V=4V

V=1.25V

V=1V

Doping

Simulations vs. measurements under ultra high injection conditions



Chapter 5

It is also possible to note that for high forward voltages (V =4V and V =5V) at

the P side of the structure there is an excess of majority carriers (holes), which are

exceeding the doping level (N =10 cm ); this excess of majority carriers is accompa-

nied by a concentration of minority carriers ( ) having the same order of magni-

tude of the doping level (N =10 cm ).

A A

A

A

+

20 -3

20 -3

Figure 5

Moreover, at the end regions the dependence of the majority carriers with the

distance from the junction is such that its derivative equals that of the minority carriers

indicating that quasi-neutrality is taking place ( ).Figure 6

Figure 5: Electrons concentration in different biasing points for V up to 5V.A

Figure 6: Carriers concentration in the P region.+

1.0E+17

1.0E+18

1.0E+19

1.0E+20

1.0E+21

0 1 2 3 4 5Distance (�m)

Ele

ctr

on

sc

on

c.

(cm

-3)

V=5V

V=4V

V=1.25V

V=1V

Doping

2.0E+19

6.0E+19

1.0E+20

1.4E+20

1.8E+20

2.2E+20

0 0.1 0.2 0.3 0.4 0.5Distance (�m)

Carr

iers

co

nc.(c

m-3

)

p conc.@5V

p conc.@4V

p conc.@2V

n conc.@5V

n conc.@4V

n conc.@2V

Doping




Chapter 5

� � Eq.1))'()()(2** dpdndp pp ��

These two facts lead to the conclusion that high injection conditions now hold

at the P side of the structure. Similar results apply in a symmetric way to the P side of

the structure.

Simulations of structures with different middle region lengths (1 m, 5 m and 20 m),

different base doping (N =10 cm and N =10 cm ) and different lifetimes

( =10 sec. and =10 sec.) show always the same result: the bending from the qua-

dratic dependence is triggered by the onset of high injection conditions at the end

regions.

It can be verified that without the excess of majority carriers at the end regions,

there would not be carriers enough to sustain the injected current. To quantify this

statement it is sufficient to consider the relation among the carrier concentrations on

either side of the P -N junction (an analogous relation holds for the other junction):

+ +

15 -3 17 -3

-7 -6

+ -

� � �

� �

BASE BASE

0 0

where the involved quantities are drawn, for convenience's sake, in . The validity

of this relation (which is simply the consequence of the application of Boltzmann's

statistic) is confirmed in where the carriers concentration at the P -N junction

edge for all the simulated middle region lengths -1 m, 5 m and 20 m- is shown. From

we can note that when low injection condition holds at the end region, is

constant and equal to the doping concentration .

Figure 7

Table 1

equation 1 p (-d )

N

+ -

� � �

p

A

*

Figure 7: Detail of the carriers distribution at the edge of the P -N space charge region.+ -

-d*

N-

NA

n(-d')=p(-d')

np0

-d'

n (-d*)p

p (-d*)p

-d

SP

AC

E-C

HA

RG

E




Chapter 5

By increasing the injected holes in the middle region, , the injected elec-

trons in the P side, must quadratically increase, according to the above men-

tioned relation. But since cannot exceed it follows that, at a certain injection

level, will not be any longer constant, therefore triggering the onset of high

injection. From is seems that high injection is triggered as soon as is in the

order of 6*10 cm , then becoming comparable with N .

p(-d')

n (-d ),

n (-d ) p(-d')

p (-d )

Table 1 n (-d )

+

18 -3

p

p

p

p

*

*

*

*

A

5.II.c Electric field

Figure 8The simulated electric field for different biasing values is shown in . It is

possible to note the high electric field build up at the end regions for high forward

voltages (V =4V and V =5V), confirming that high injection is taking place there. As a

consequence, there is an extra voltage drop across these regions. To note also that from

V =1.25V to V =5V the electric field is increasing in all the three regions with the same

factor. The electric field never reaches values that could lead to impact ionization

A A

A A

Table 1: Carrier concentrations at the P -N junction edge corresponding to the middle region with

length 1 m, 5 m and 20 m.

+ -

� � �

VA (V) Base length

(�m)

IA (A) pp(-d*) np(-d*) p(-d’)= n(-d’)

1 1 9.19E-05 1.00E+20 1.21E+17 3.52E+18

1.25 1 2.47E-02 1.24E+20 2.40E+19 5.44E+19

2 1 2.94E-01 2.13E+20 1.13E+20 1.49E+20

3 1 7.58E-01 2.87E+20 1.67E+20 1.89E+20

4 1 1.2 3.22E+20 2.22E+20 2.49E+20

5 1 1.59 3.50E+20 2.50E+20 2.73E+20

1 5 1.08E-04 1.00E+20 7.87E+16 3.00E+18

1.25 5 7.47E-03 1.06E+20 6.02E+18 2.65E+19

2 5 7.07E-02 1.25E+20 1.12E+19 6.75E+19

3 5 1.79E-01 1.52E+20 3.45E+19 1.01E+20

4 5 2.98E-01 1.87E+20 9.81E+19 1.24E+20

5 5 4.18E-01 1.98E+20 1.17E+20 1.39E+20

1 20 3.39E-05 1.00E+20 1.07E+16 1.07E+18

1.25 20 7.18E-04 1.00E+20 1.10E+16 1.25E+18

2 20 6.17E-03 1.06E+20 6.05E+18 2.56E+19

3 20 1.52E-02 1.14E+20 1.39E+19 3.97E+19

4 20 2.49E-02 1.21E+20 2.10E+19 5.01E+19

5 20 3.48E-02 1.27E+20 2.75E+19 5.85E+19




Chapter 5

because the carrier densities ( and ) would imply unrealistic current

densities. Yet, velocity saturation could play a relevant role in triggering the onset of the

excess of majority carriers: in fact, once the carriers move with their saturating velocity,

there is a need of more carriers to sustain the injected current.

Figure 4 Figure 5

�

�

�

�

�

�

��

�

��

��

��

� ��

�

pecarrier tyon thedependent2,or1

Eq.2)10

mobilityfieldlow

rewhe

1

)( 7

0.0

1

0.0

0,0

,

n

cm/sv

v

E

E SAT

pn

nn

SAT

pn

pn

pn

�

�

��

But by looking at (in which the average electric field for different biasing points

is shown for the P region, where the highest electric field is located), this could be a

consistent argument for the shortest structures ( =1 m) but it is not clearly true for

the others. Indeed, when accounting for saturation velocity effects by using:

Table 2

2d

+

�

the mobility decrease caused by the electric fields from is negligible. Since the

electric fields in all the three regions are not negligible anymore, we therefore expect

that recombination will play a less important role in the transport mechanism.

Table 2

Figure 8: Electric field distribution in different biasing points for V up to 5V.A

Table 2: Average electric fields across the P region for different base length and biasing conditions.+

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

0 1 2 3 4 5Distance (�m)

Ele

ctr

icfi

eld

(V/c

m)

V=5V

V=4V

V=1.25V

V=1V

NB=1017

, �0=10-7

, P+

- N+ Medium E@2V Medium E@4V Medium E@5V

L=1�m 1.5.10

4(V/cm) 6

.10

4(V/cm) 7

.10

4(V/cm)

L=5�m 6.10

3(V/cm) 1.5

.10

4(V/cm) 2.5

.10

4(V/cm)

L=20�m 7.10

2(V/cm) 2.5

.10

3(V/cm) 3.2

.10

3(V/cm)




Chapter 5

5.II.d Potential

Figure 9

Figure 8

The simulated potential for different biasing values is shown in .

Interesting observations can be made in the depletion regions. First, we focus on the

potential drop across the P -N space charge region (the “real” junction at the end

region on the left). When the applied forward voltage is very low (V =0.1V) the built-in

voltage is effectively lowered by that amount. If the forward voltage is further

increased, the built-in voltage reduces. At V =1V the built-in voltage is much reduced

but still detectable. In terms of Poisson equation it means that the space charge term is

still positive, although reduced. At V =1.25V the situation is changing: no voltage drop

across the junction, which means that the applied voltage has completely cancelled out

the built-in voltage or, in other words, the space charge region does not exist anymore.

Therefore the charge term in Poisson equation is zero. At this point high injec-

tion takes place at the end region and with it the change from the quadratic dependence

between current and voltage. For larger applied voltages (V =4V and V =5V) the

potential even changes sign, which means that the charge term in Poisson equation

becomes negative. This can be also seen from the electric field plot in : for large

applied voltages the electric field is strongly decreasing (approximately by a factor 4)

when passing from the P side to the N side of the junction.

+ -

+ -

A

A

A

A A

Figure 9: Potential plot in different biasing points for V up to 5V.A

-0.5

0.5

1.5

2.5

3.5

4.5

0 1 2 3 4 5Distance (�m)

Po

ten

tial(V

)

V=5V

V=4V

V=1.25V

V=1V

V=0.1V




Chapter 5

Eq.3)2)(

��

�

�

�

��d

d AA

d

d

M

nqdxnqxUqJ

��

� � � � Eq.4)

tanh

)(and

tanh

)( **

**

��

��

��

��

��

��

��

�

�

��

�

�

��

pN

Np

pN

pN

nP

Pn

nPnP

L

W

dpLqdJ

L

W

dnLqdJ

��

5.II.e Recombination currents

Table 3Analogously to what we have previously done, in a comparison between

the simulated and the analytically calculated recombination currents (for each region) in

the biasing points at which an excess of majority carriers appears is shown. For conve-

nience's sake, the formulas through which the recombination currents are calculated

are shown once again.

The recombination current in the middle region is evaluated by means of:

whereas the end regions diffusion currents are calculated with:

As immediately noticeable from the recombination currents (in all three

regions) are becoming a smaller and smaller fraction of the total current. Based on the

carriers distribution and the electric field in , and , we can more precisely

assess this statement. We first focus on the middle region. For V =4V, at the left side of

the middle region (at x =0.5 m) we have that:

Table 3

Figure 4 5 8

A

1 �

Table 3: Simulated versus calculated recombination currents for different biasing points.

VA (V) InP+ (-d) IREC Middle (A) IpN+ (d) ITOT (A)

2 Sim. 2.05E-02 2.50E-02 1.10E-02 7.07E-02

Calc. 1.85E-02 3.75E-04 8.95E-03

3 Sim. 4.10E-02 5.30E-02 2.30E-02 1.79E-01

Calc. 3.90E-02 6.80E-04 2.15E-02

4 Sim. 6.00E-02 8.10E-02 3.20E-02 2.98E-01

Calc. 5.08E-02 7.20E-04 2.20E-02

5 Sim. 7.70E-02 1.37E-01 3.90E-02 4.18E-01

Calc. 5.56E-02 8.40E-04 2.26E-02




Chapter 5

� ��

��

��

�

��

��

��

�

4-24

1

3-19

1

3

1

cm102.1

cm104

V/cm105

xxx

n

xn

xE

� ��

��

��

�

��

��

��

�

4-24

4

3-19

4

4

4

cm102.4

cm1066.8

V/cm1022.1

xxx

n

xn

xE

from which:

Similar results apply to the medium point (x =2.75 m) and at the right side

(x =5 m) of the middle region. It is then apparent how the drift component of the

current in the middle region prevails over the diffusive one. We now apply the same

reasoning to the P side: for V =1V the P region was almost neutral and the current

was largely diffusive (see , ). For V =4V, at x =0.45 m, we now have:

2

3

A

A 4

�

�

�

+ +

Table 1 Chapter IV

from which:

Therefore, we are moving onto a situation in which the current transport is

mainly field driven all over the structure. To note also from that at high forward

voltages the recombination current in the middle region is much larger than what

predicted from the . The reason for that is the onset of Auger recombination,

as expectable from carrier density in the order of 10 cm (see, for instance, ).

The impact of Auger recombination in power rectifiers has been found to be

responsible for increasing the voltage drop across the middle region [1, 2]. But since in

ultra high injection conditions the current is mainly field driven we expect that all

parameters related to recombination will not play such an important role anymore like

it was for medium applied voltages.

Table 3

equation 3

Chapter 419 -3

� � � � -26

1DIFF

-27

1DRIFT cmA103.3JcmA102.1J �� xx

� � � � -26

4DIFF

-27

4DRIFT cmA101.1JcmA102.1J �� xx




Chapter 5

�

��

�

��

nV

nJJJ

A

pNnPA

2

Eq.5))( 2

AA VJ �

5.II.f Ultra high injection conditions

Chapter IV

In the previous chapter it has been shown that for high forward voltage (approx-

imately up to V =1.6V) the current depends quadratically on the applied voltage.

Complementary to the rigorous analytical approach followed by Herlet [3], the main

reason for that dependence in this regime is based on the following features of the

transport mechanisms:

The diffusion currents at the end regions support a large part of the injected cur-

rent.

The middle region supports the largest part of the applied voltage, being the

voltage drop across the end regions negligible because of the low injection there.

The electric field scales linearly with average injected carrier in the middle region

It is convenient to express all the involved quantities in terms of the parameter “average

injected carrier in the middle region”. With reference to the analytical treatment pre-

sented in the we can then write:

A

�

�

�

From which, by eliminating the parameter, we obtain:

When moving into ultra high forward voltage we can apply the same reasoning by

considering that the transport mechanisms is now characterized by the following new

features:

In all the three regions of the structure the current is mainly field driven

Since the device is fully conductivity modulated, a higher injected current is sus-

tained by a very small increase of the carrier concentration and then, the conductiv-

ity of the structure does not change significantly with the injected current (

and )

As a consequence, the electric field is a weak function of the carrier concentration

( ).

�

�

�

Figure 4

5

Figure 8




Chapter 5

� �

nV

VnqJ

A

AnA

offunctionweak

�

Eq.6)AA VJ �

By expressing once again all the involved quantities as a function of the parameter

“average injected carrier in the middle region”, we have:

From which it follows:

Therefore the device behaves as a non-linear resistor. The main difference with

the diffused resistors studied in is that none of the three regions of the

structure is now neutral. The voltage across the device is simply sustained by a small

deviation from quasi-neutrality condition. The linear characteristic is clearly

shown in .

Chapter III

I (V )

Figure 10

A A

Figure 10 I (V ): Simulated characteristic plotted on linear scale.A A

0.0E+00

1.0E-01

2.0E-01

3.0E-01

4.0E-01

5.0E-01

2 2.5 3 3.5 4 4.5 5VANODE (V)

I AN

OD

E(A

)

Simulated:2d=5 micron;N-=1e17cm-3




Chapter 5

� � Eq.7)EpnqJ pnA ��

� � Eq.8)��

��

��

��

��

E

p

E

nqEpnq

E

Jpnpn

A ��

� � Eq.9)��

��

��

��

��

��

��

E

x

x

p

E

x

x

nqEpnq

E

Jpnpn

A ��

� � Eq.10)��

��

��

��

��

��

x

p

x

n

E

xqEpnq

E

Jpnpn

A ��

� � Eq.11)pnq

x

E��

��

� ��

Eq.12)��

��

��

��

��

��

x

p

x

n

pn

Epnq

E

Jpnpn

A ��

��

To analyze more in detail this behavior, we need to deduce the dependence of

the injected current with the electric field and to include Poisson equation. Since the

current is field driven in all the three regions, referring to any of them we can write:

By deriving with respect to the electric field :E

Reworking:

From which:

But Poisson equation reads:

By introducing in in:equation 11 equation 10




Chapter 5

!��

��

��

��

�

��

�

�� 6.8)()(

2

)(NpNNnN

N

MpMMnMPpPPnP

P

PMNTOTpnqA

W

pnqA

d

pnqA

WRRRR

��

� � Eq.13)2

DAA VVJ ��

� � Eq.14)ln2

AA VJ �

The first term on the right side is the conductivity per unit of area of the consid-

ered region and, as already remarked, it does not change significantly from V =2V on.

The second term represents the deviation from the linear law due to the recombination

and the not perfectly verified neutrality condition.

By substituting the values from , and , it is apparent that the latter term

is negligible with respect to the former. The fact that applies to all three

regions also means that the device can now be modeled as a series of three resistors, all

conductivity modulated. In fact, if we calculate the resistivity of the structure by adding

up the three components and by considering only the average values of the involved

quantities (hypothesis reasonable by considering the distributions in , and ),

we obtain:

A

Figure 4 5 8

equation 12

Figure 4 5 8

This value is the same found in the simulated characteristic in , then

confirming the quality of the model.

For modeling purposes it would be very useful to merge the two dependencies

describing the behavior of the structure up to ultra high forward voltages into one only

expression. The quadratic dependence that holds up to 1.5-1.6V reads:

I (V ) Figure 10

5.II.g Modeling issues

A A

The built-in voltage acts as a threshold voltage and it is normally close to 1V. Given

that, it is interesting to consider the following fitting function:

VD

In this function the concept of threshold is “intrinsic” in the logarithm nature.

Moreover, it is quite easy to verify that:




Chapter 5 TLP characterization

� � � ��

��

��

""��

V6.1forln

V6.11.1Vforln

2

22

AAA

ADAA

VVV

VVVV

This characteristic makes this function ideal for modeling the P -N -N sub-

strate diodes over a very broad range of high injection conditions. In the

quality of this fitting function is confirmed over a range starting from V =1.2V.

+ - +

Figure 11

A

5.III TLP characterization

In order to simulate ESD zap conditions and to verify the proposed model,

several devices have been tested under transmission line pulse stress (TLP, see

). The pulse duration was set in 100ns. and the current pulses were increased until

damage occurred. The tested devices were P -P -N -N diodes on insulating substrate

(SOI, ). These diodes under high injection conditions behave exactly as P -N -

N substrate diodes, with the exception of a higher resistivity (and, then, a higher

voltage drop for a given injected current) due to extra P region. P -P -N -N diodes

Chapter

1

Figure 12

+ - - +

+ -

+

- + - - +

Figure 11 equation 14: Fitting of the simulated characteristics for V up to 5V by using .A

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (Volts)

I AN

OD

E(A

)

2d=1 micron

Fitting 1 micron

2d=5 micron

Fitting 5 micron

2d=20 micron

Fitting 20 micron



Chapter 5

were mainly chosen because of their matching properties with our simulated struc-

tures. In fact, with reference to , one should note that:

The layout is such that the current is mainly flowing laterally.

In SOI technology both the top and the bottom of the active device are virtually

acting as thermal insulators, therefore making the choice of the thermal boundaries

much easier.

Figure 12

�

�

In a typical pulsed characteristic is shown. Note that the loga-

rithmic fitting law proposed in the previous section exactly matches the measured

characteristic up to the point .

Figure 13 I (V )

I (V ) 1

A A

A A

Figure 12: Cross sections of the tested P -P -N -N SOI diode under TLP conditions.+ - - +

Figure 13 I (V ) Figure 12: Pulsed characteristic of the device in .A A

GateCathode

P+

L=5 m�

Anode

P- N+N- (epi)

Insulator

1.0E-02

1.0E-01

1.0E+00

1.0E+01

0 5 10 15 20 25VANODE (V)

I AN

OD

E(A

)

TLP Measurement

Logarithmic fitting

1

2

TLP characterization



Chapter 5

In the time dependence of the voltage and of the forced current

corresponding to the zap at the point is shown: when the device is subject to a pulse

with amplitude of about 1.05A, the voltage clamps, for the entire duration of the pulse,

to approximately 10V. In the same plot as in but relative to the zap at

the point is shown: in this case a pulse with amplitude of about 1.75A causes a

remarkable variation of the clamp voltage during the pulse. This means that self-

heating effects strongly determine the clamp voltage.

Beyond the point the device is irreversibly damaged as its leakage increased by

four orders of magnitude. From , and we can conclude that as long as

self-heating effects are not determinant, the logarithmic fitting law exactly matches the

measured . Once temperature effects come into play, a sub-linear dependence

takes place until the device is led to destruction. Yet, by using the logarithm fitting law

also in the temperature driven regime, we found an introduced error not exceeding the

20%.

Figure 14

1

Figure 15 Figure 14

2

2

Figure 13 14 15

I (V )A A

Figure 14: Transient current and voltage characteristics corresponding to a current pulse of 1.05A.

Figure 15: Transient current and voltage characteristics corresponding to a current pulse of 1.75A.

-20

-10

0

10

20

30

40

50

0 2 4 6 8 10 12t (sec.*10

8)

VA

NO

DE

(V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

I AN

OD

E(A

)Voltage

Current

-20

-10

0

10

20

30

40

50

60

70

0 2 4 6 8 10 12t (sec.*10

8)

VA

NO

DE

(V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

I AN

OD

E(A

)

Voltage

Current




Chapter 5

Some more insights can be earned by making use of non-isothermal simula-

tions. In the isothermal characteristic versus the non-isothermal one is plot-

ted. The simulated result is very similar to the measured one and the difference between

the two characteristics becomes apparent only at about V =4V. For V =5V the maxi-

mum temperature inside the device is about 900ºK and the deviation from the isother-

mal characteristic is in the order of 35%.

From the analysis of the main parameters there are two competing factors as a

function of temperature: in one side there is an increase of carriers (with respect to

isothermal conditions) due to the lattice heating but, on the other side, there is a strong

decrease of the carriers mobility, which are temperature dependent according to the

formula in ( ). Evidently, from , the latter prevails over the

former.

Figure 16

Chapter 2 paragraph III Figure 16

A A

Figure 16 I (V ): Simulated isothermal versus non-isothermal characteristic.A A

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

Isothermal

Lattice Temperature




Chapter 5 Process and layout variations

5.IV Process and layout variations

5.IV.a Base region length effects

Figure 17 I (V )

2d 2d

Figure 17

In the effect of changing the base length on the characteristic

from =1 m to =20 m is shown: the longer the structure, the lower is the current

for a given applied forward voltage.

Since the structure therefore behaves as a non-linear resistor, this behavior can be easily

understood in the light of the transport mechanism. By increasing the base length, the

average electric field is proportionally reduced. In addition the average carrier distribu-

tion in the middle region tends to be reduced by the length because of the increased

recombination thereby increasing the resistivity of the middle region. The combination

of these two facts (reduced electric field + reduced carrier concentration) explains the

curves in .

A A

� �

5.IV.b Base region doping effects

Chapter II

The change of the doping level in the base region affects several parameters. In the field

driven regime the most important is the low field mobility, both for electrons and holes,

which is increased when passing from N =10 cm to N =10 cm , according to

the implemented model introduced in . This is the reason for which at a given

BASE BASE

17 -3 15 -3

Figure 17 I (V ): Simulated characteristic as a function of the base length.A A

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

Base=1 micron

Base=5 micronBase=20 micron



Chapter 5

Eq.15)105.

lifetimesholesandelectronsewher

13-16

00,00,0

,�

��

��

��

��

cmconstNN

NSRH

pn

SRH

BASE

pn

pn

��

applied forward voltage, the structure with N =10 cm shows a larger current

( ). Yet, the change of the base region doping affects the lifetimes in this region,

according to the following dependence (based on the SRH statistic):

BASE

15 -3

Figure 18

Therefore the lifetimes in the base region increase from =3.3310 sec to

=9.801110 sec when passing from N =10 cm to N =10 cm (for

= =10 sec.). This fact increases the recombination in the middle region but this is

relevant only in the diffusion driven regime (low and medium forward voltages).

�n/p

BASE BASE

no p0

. -8

. -8 17 -3 15 -3

-7

�

� �

n/p

5.IV.c Lifetime effects

Figure 19

For high forward voltage the lifetime does play only a minor role: in fact an

increase of the lifetime implies an increase of the recombination and then, in the field

driven regime, a reduction of the total current ( ). But the lifetime, in the regime

in which the transport mechanism is diffusive (low and medium forward voltage) has a

Figure 18 I (V ): Simulated characteristic as a function of the base region doping.A A

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

N-=1e17cm-3

N-=1e15cm-3

Process and layout variations



Chapter 5

Eq.16)1

tanh

)(

tanh

)()(

**

n

n

Pn

nnTH

n

Pn

nn

L

W

dnVq

L

W

dnLqPJ

��

��

��

��

��

��

�

��

��

��

��

�

major impact [4]. In fact by decreasing the lifetime from = =10 sec. to =10 sec.

the recombination current in the base region is increased by a factor 20 ( )

whereas at the end regions the increase of the current is proportional to:

�0 n0,p0 0

-7 -6� �

equation 3

Therefore, the smaller the lifetime, the larger is the current (insert of ).Figure 19

5.IV.d End regions doping effects

Figure 20

equation 1

The effect of changing the end regions doping from 10 cm to 10 cm is

shown in : the result can be easily be interpreted by noting that this corre-

sponds to an increase of the resistivity of the end regions. But there are also effects on

the conductivity modulation that takes place once high injection occurs in the middle

region. In fact, by remembering the Boltzmann relation between the carriers on either

side of the space charge region ( ), a reduced end region doping causes a

reduction of the average carrier concentration in the middle region.

20 -3 18 -3

Figure 19 I (V ): Simulated characteristic as a function of the carriers lifetime from low injection(insert) to high injection.

A A

0.0

0.4

0.8

1.2

1.6

2.0

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

tau=1e-6 sec.

tau=1e-7 sec.

1.0E-15

1.0E-13

1.0E-11

1.0E-09

1.0E-07

1.0E-05

0 0.2 0.4 0.6 0.8 1VANODE (V)

I AN

OD

E(A

)

tau=1e-6 sec.

tau=1e-7 sec.




Chapter 5

This turns in a higher resistivity of the structure in the field driven regime and, there-

fore, in a smaller current for a given applied voltage.

5.IV.e End regions length

Figure 21

The effect of varying the end regions length from the value of 0.2 m to 0.4 m

and 0.8 m is shown in . The longer the end regions are, the lower is the current

for a given applied voltage. The reason is simply in the increased length of the overall

structure, while keeping all the other parameters fixed. This causes a higher resistivity

of the structure.

� �

�

Figure 20 I (V ): Simulated characteristic as a function of the end regions doping.A A

Figure 21 I (V ): Simulated characteristic as a function of the end regions length.A A

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)End regions=1e20 cm-3

End regions=1e19 cm-3

End regions=1e18 cm-3

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

3.0E-02

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

End regions=0.2umEnd regions=0.4umEnd regions=0.8um





5.IV.f Carrier-carrier scattering effects

Figure 22

Figure 22

The effect of including carrier-carrier scattering mechanisms in the mobility is

shown in . With respect to the concentration dependent mobility, carrier-

carrier scattering causes a strong decrease of the electrons and holes mobility [5]: from

675 cm /V*sec. to 27 cm /V*sec. for the electrons mobility and from 300 cm /V*sec.

to 30 cm /V*sec. for the holes mobility. The factor 25 between the electron mobility

when carrier-carrier scattering is considered, is the SAME between the currents in

. Therefore the carrier-carrier scattering greatly increases the resistivity of the

structure by reducing the mobility.

2 2 2

2

5.V Conclusions

In this chapter a study on P -N -N substrate diodes under ultra high injection

conditions has been presented. The problem has been tackled both from an experi-

mental point of view (through DC and pulsed analysis) and with the support of numer-

ical simulations. It turned out that the as soon as high injection takes place at the end

regions too (characterized by an excess of majority carriers) a new linear charac-

teristic is found.

In this regime, the current is field driven in all the three regions of the P -N -N

substrate diode, which now behaves as a non-linear resistor. A fitting law that matches

the characteristic over a broad range of injection conditions has been proposed

and verified both on numerical results and on measured devices. Self-heating effects as

well as process and layout variations have been analyzed.

+ - +

+ - +

J (V )

J (V )

A A

A A

Figure 22 I (V ): Simulated characteristic as a function of the scattering mechanism.A A

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)

Conc-dependent

Carrier-carrier




� �2ln AA VJ �

Finally, we can therefore summarize the modeling of P -N -N substrate diodes for all

the possible injection conditions with four regions as shown in .

: Dependence " ".

In this region the structure behaves as a conventional diode under low injection condi-

tions. The injected current is entirely sustained by the recombination of minority

carriers (holes) injected by the P region into the middle region. With the exception of

the P -N space-charge region, the entire structure is neutral. The voltage range of this

region goes from V =0V till V =0.8V.

: Dependence " ".

In this case high injection in the base region takes place. The current is sustained

through the recombination in the middle region of electrons and holes that, because of

the quasi-neutrality condition imposed by high injection, have nearly the same concen-

tration. The diffusion currents at the end regions (where low injection still holds) are

negligible with respect to the recombination current in the middle region ( ).

The transport mechanism is the same as in the previous case. The voltage range of this

region goes from V =0.8V till V =1.1V.

: Dependence " ".

In this case the diffusive components of the currents at the end regions ( and )

become of the same order of the recombination current in the middle region ( ).

Although at the end regions low injection level is still verified, in the middle region the

current is more and more field driven. For "long" power structure and will largely

exceed ( ). This is not the case for substrate diodes because another

dependence takes over due to the rising of the electric field at the end regions. The

voltage range of this region goes from V =1.1V till V =1.5-1.6V.

: Dependence "V ".

In this case high injection takes place also at the end regions. The transport mechanism

is fully field driven all over the structure, which now acts as a non-linear resistor. This

dependence is valid beyond 1.5-1.6V. For simulation purposes, the last two dependen-

cies can be conveniently merged onto the following fitting function:

+ - +

+

+ -

Figure 23

exp(V /V )

exp(V /2V )

J =J

(V -V )

J J

J

J J

J J =J +J

Region 1

Region 2

Region 3

Region 4

A T

A T

A M

A D

N+ P+

M

N+ P+

M A N+ P+

A A

A A

A A

A

2




5.VI References

[1] Ghandhi, S.K., “Semiconductor Power Devices”, John Wiley & Sons, New York,

1977.

[2] Baliga, B.J., “Power Semiconductor Devices”, Krieger Publishing Company, 1995.

[3] Herlet, A., “The Forward Characteristic of Silicon Power Rectifiers at High Current


[4] Choo, S.C., “Effect of Carrier Lifetime on the Forward Characteristics of High-

Power Devices”, IEEE Trans. On Electr. Devices, Vol. ED-17, No. 9, 1970, pp. 647-

652.

[5] Choo, S.C., “Theory of Forward-Biased Diffused-Junction P-L-N Rectifier-Part I:

Exact Numerical Solutions”, IEEE Trans. On Electr. Devices, Vol. ED-19, No. 8,

1972, pp. 954-966.

Figure 23 I (V ): Specimen of the typical characteristic covering all the possible injection levels inforward biasing conditions..

A A

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

1.0E+00

0 1 2 3 4 5VANODE (V)

I AN

OD

E(A

)1

23 4

Chapter

Abstract: in this chapter the suitability of the LDMOS transistors designed for medium voltage applications

will be investigated in sight of a use as single ESD protection structure. Through measurements and 2D

simulations the breakdown behavior of the LDMOSt's will be analyzed and compared with that of the

conventional ggnMOSt's. It will be shown that the Kirk effect is an unavoidable feature of this type of

structures. The consequences of this phenomenon will be investigated. Failure analysis will be presented in order

to confirm the theoretical predictions.

LDMOS Transistorsunder High Current

Conditions

6

- 116 -LDMOS Transistors under High Current Conditions

6.I Introduction

In the course of the last 15 years, Smart Power technology showed a spectacular

evolution, moving from the first generation in 1985 till the most recent “System

Oriented Generations”, in which non-volatile memories (EPROM and EEPROM) are

integrated. Up to the mid eighties power IC's were realized with pure bipolar technol-

ogy thanks to their excellent amplification characteristics and matching properties.

In bipolar processes logic functions were implemented through I L (Integrated

Injection Logic) technology. But the I L approach became unsuitable as soon as the

demand for more logic capabilities arose due to its intrinsic limitations (complex

design, high power consumption and difficult shrinkability). Because all these limita-

tions were not present in CMOS technology, the need of combining bipolar and

CMOS was apparent. Furthermore, as the provided power to the load was increasing,

the maximum power dissipation was reached. Then DMOS transistors represented the

ideal solutions: no driving DC current requirement (limiting power dissipation) and

efficient working in fast switching condition [1].

The term BCD indicates a mixed process technology that allows the integration

on the same chip of Bipolar, CMOS and DMOS devices. Moreover, in the DMOS the

current density depends on the geometrical ratio W/L, while in the power bipolar

components it depends on the emitter area so that no improvements in density can be

obtained from the lithography progress. DMOS transistors are structures in which the

channel length is determined by the different rate in the lateral diffusion of two kinds

of dopant impurities introduced through the same opening in the polysilicon layer.

Because of that, these structures may have a very short channel length independently

from the lithographic step in the used process.

A low-doped N region (drift region, N ) follows the channel [2]. Many config-

urations of DMOS transistors are available, dependent on the voltage range they are

conceived for. For low voltage-high current application (few tens of V) the best choice

in terms of on-resistance is the device pictured in : the layout is very similar to

that of a conventional MOS device with the exception of the extra P-well. For high

voltage-low current (several hundreds of V) the device pictured in is normally

used: the high reverse voltage blocking capability is achieved through the spreading of

the electric field underneath the channel in correspondence of the P-well corner.

This is normally obtained with a polysilicon field plate overlaying the gate and

the field oxide. The optimization of the plate (trade-off between maximum obtainable

breakdown voltage and minimum contribution to the on-resistance) is derived through

2

2

EPI

Figure 1

Figure 2

IntroductionChapter 6

Figure 1: DMOS transistor for low voltage-high current application (few tens of V).

Figure 2: DMOS transistor for high voltage-lowcurrent application .(several hundreds of V)

Figure 3: DMOS transistor for medium voltage-mediumcurrent application.

- 117 -


Back-Gate

Gate

Drain

N+

Source

P substrate

Buried N

CO-PS

L

IP+

P- NEPI

N+

Back-GateGate

DrainSource

P substrate

Buried N

CO-PS

Field Oxide

I

P-

P+ N+

NEPI

N+

P+N+

P-

Back-Gate

N+P+

Source

P-

Gate

NEPI

P substrate

Buried N+

Drain

N+

Sinker N+

Field Oxide

SourceBack-Gate

2-D simulations. With this approach blocking voltages in the order of 250-300V have

been reached. By applying the reduced surface field concept -RESURF [3]- voltages till

750V were possible. For medium voltage-medium current, a vertical approach is

followed ( ): the current flow is vertical but is brought to the surface via buried

layers and sinkers. This “parallel” configuration allows the integration of any number

of devices into the same silicon island.

The problem of finding a protection element without resorting to a complex

protection network for medium supply voltage applications cannot be addressed

through the conventional approach by using a ggnMOSt (V too low) or a pure

bipolar structure (V too high).

Figure 3

HOLD

T1

LDMOS Transistors under High Current Conditions

Figure 4: Measured DC characteristic of LDMOS with W=7 m, CO-PS=3 m and L variable.I(V) � �

- 118 -

Chapter 6 Experimental results

Therefore in this chapter the suitability of the lateral DMOS transistor

(LDMOSt, see ) as single ESD protection element for medium voltage applica-

tions will be investigated. In particular our study will be targeted to the breakdown

behavior (positive current pulse at the drain) and to the relationship between snapback

(V ) and holding voltage (V ) and the layout & process parameters.

For this reason the analysis will be carried out entirely under DC conditions. For

the sake of completeness, it is worth noting that when the current pulse at the drain

contact is negative, the device is forced into high forward biasing conditions: in this case

the analysis carried out on P -N -N substrate diodes under ultra high injection condi-

tions holds (see and ).

Several LDMOS transistors have been tested in DC conditions (HP4145). With

reference to , the varied parameters were: poly length L from 3 to 6 m, CO-PS

(contact to poly gate spacing) from 3 to 8 m and width W from 7 to 20 m (one module

with W=100 m was available too).

Figure 1

Chapter 4 Chapter 5

Figure 1

T1 HOLD

+ - +

6.II Experimental results

�

� �

�

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

30 35 40 45 50 55VDRAIN (V)

I DR

AIN

(A)

L=3.5 micron

L=4 micron

L=4.5 micron

VT2VH

VT1


Figure 5: Measured DC characteristic of modules with W=100 m, L =3 m and CO-PSvariable.

I(V) � �

- 119 -

Chapter 6

6.II.a Poly length variation effects

Figure 4

Figure 4

Chapter I

In the effects of the poly length L variations (3.5 m, 4 m and 4.5 m) on the

DC characteristics are pictured. Source, back-gate and gate contacts are grounded,

while CO-PS=3 m and W=7 m. From we can see that:

V (snapback) is around 45V and I is apparently constant (3*10 A/ m): this

suggests that the mechanism leading to the DC snapback conduction mode be

current controlled.

The length of the drift region (dependent on L) modulates V .

V is around 40V for all the structures: the snapback swing is very limited in

voltage and this might be attributed to the poor beta of the parasitic bipolar

structure associated to the device (see ). Such a large V causes a

considerably high Joule power dissipation.

V is around 50V with an I constant for all the structures (1.3*10 A/ m); the

DC current capability looks poor, likely as a consequence of the high V .

� � �

� �

�

�

�

�

�

�

T1 T1

T1

HOLD

HOLD

T2 T2

HOLD

-5

-4

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

25 30 35 40 45 50VDRAIN (V)

I DR

AIN

(A)

CO-PS=3 micron

CO-PS=5 micron

CO-PS=8 micron

VT1

VT2

Experimental results


- 120 -

Chapter 6

6.II.b CO-PS spacing variation effects

Figure 5

Figure 4

6.II.c W variation effects

Figure 6

In the effects of the contact to poly gate CO-PS spacing variations (3 m, 5 m,

and 8 m) are pictured. L=3 m and W=100 m. It is possible to note that:

V is at the same level as in the previous components.

The drop in voltage at the snapback is just perceptible leading to an even higher

V .

The extra resistance due to the increased CO-PS spacing does not improve the DC

performance at all.

Note also that the tested devices have a width increased by a factor 14 with respect

to those shown in . In spite of that, both I and I do not scale properly with

the increased W (only a factor 5). This suggests that inhomogeneities in the current

flow are taking place. The behavior of the device is then moving towards a 3-D

dependence, making difficult comparisons with 2-D simulations.

In the effects of the width W variations (7 m, 10 m and 20 m) are shown.

CO-PS=3 m and L=4 m. The measurements indicate:

V , V , V do not significantly change with W.

I and I do not scale as expected with the increased W (30% instead of factor 2),

therefore confirming the presence of inhomogeneities in the current flow.

In conclusion we can state that the DC performances are unsatisfactory with respect to

the maximum current sustaining capability and the scaling properties of the character-

izing parameters. Therefore it is expected that these transistors will be bad ESD protec-

tion elements. In the next paragraphs the causes of these disappointing results will be

investigated to assess whether or not there is room for some improvements.

� �

� � �

� � �

� �

�

�

�

�

�

�

T1

HOLD

T1 T2

T1 H T2

T1 T2

Experimental results


- 121 -

Chapter 6 Simulation results

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

30 35 40 45 50VDRAIN (V)

I DR

AIN

(A)

W=7 micron

W=10 micron

W=20 micron

VH

VT2

VT1

Figure 6: Measured DC characteristic of LDMOS with L=4 m, CO-PS=3 m and W variable.I(V) � �

6.III Simulation results

6.III.a Simulation approach

As earlier mentioned, the studied devices are very large structures: CO-PS

spacing in the order of 5 m and gate length of 6 m are usual values and, therefore, the

length of the entire structure can easily exceed 20-25 m. This fact together with the

complexity of the structures would impose computationally prohibitive meshing when

simulating.

Furthermore, the background available in the literature about these devices is

very poor. For this reason we adopted an approach addressed to scale down the device

into a “test structure device” rigorously keeping fixed the process features (doping

profiles and sheet resistance): in this way the main physical phenomena taking place

during high reverse voltages do not change, even if the results obtained will underesti-

mate the ones from the real structure.

The structures have been designed with a Device Editor implemented in Silvaco

2-D/3-D simulation tool [4]. The main advantages of this choice are:

� �

�


- 122 -

Chapter 6

�

�

The possibility of analytically defining doping profiles and process/layout features

even with unlikely parameters in order to get insight on the behavior of the struc-

ture.

Meshing optimization based on the same mesh parameters: this is important when

comparing structures with layout variation [5].

Most simulations are performed in isothermal conditions because our main interest is

not the second “thermal” breakdown but the mechanisms modulating the first break-

down and the holding voltage. A simulation taking into account lattice temperature will

be shown, too. The simulated structures have an high resistive P-substrate

(N =3e13cm ), a buried N region between the drift region (N =5e14cm ) and the

substrate, a back-gate contact on the P region which may be tied together with the

source contact, minimum CO-PS distance, a channel length of about 0.25 m, mini-

mum bulk-source implant distance and 0.7 m gate length.

On this structure (which, from now on, we will refer to as “standard” and whose

a cross section is shown in ) we simulated some variations, both layout (channel

length and CO-PS distance) and process (epitaxial layer doping and P profile).

SUB EPI

-3 + -3

-

-

�

�

Figure 7

Figure 7: Simulated LDMOS structure.

Simulation results


- 123 -

Chapter 6

6.III.b Drift region length

I(V)

Figure 8

Figure 4

The simulated characteristic of the “standard” device with all the electrodes

grounded (except the drain contact) is shown in : V is 11V and V about 4V.

Notice that the current density at which the snapback occurs (I =4*10 A/ m) is

approximately the same we obtained for a measured similar structure ( ). Notice

also that the simulated V is reduced by a factor 4-5 with respect to the measured

similar structure: this factor is the same existing between the simulated and the real drift

region length. In fact, as we will show later, the voltage mostly drops across the drift

region, leading to a voltage scaling with its length.

T1 HOLD

T1

T1

-5�

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

Standard

A

B

Figure 8: Simulated DC characteristic of the "standard" device.I(V)

The first variation we experimented is the drift region length (and, consequently,

the poly length, but the channel length is still unchanged) while keeping constant its

doping level. As pictured in the drift region length modulates the snapback

voltage but the current density at which the snapback occurs is unchanged.

This result, in spite of the difference in the magnitude of the voltages involved (be-

cause of the different geometry), is the same as that we obtained from measurements

on real devices ( ).

Figure 9

Figure 4

Simulation results


Figure 9: Simulated effect of changing drift region length.

Figure 10: Simulated electric field in the "standard" LDMOS at different biasing points.

- 124 -

Chapter 6

The relationship between the drift region length and the snapback voltage has been

investigated in previous work [6] and in about the high current characteriza-

tion of N-well resistors: as a consequence it is suggested that the driving mechanism for

the snapback of the entire structure is the breakdown of the drift region resistor.

Chapter 3

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

Standard -0.2 umStandardStandard +0.2 umStandard +0.4 um

Simulation results

N+

N+

P-

NEPI

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

StandardA

Gate

N+N

+

P-

NEPI

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

Standard

C

Gate

N+N

+

P-

NEPI

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

Standard

D

Gate

N+

N+

P-

NEPI

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

Standard

B

Gate


- 125 -

Chapter 6

As detailedly explained in , in N-well resistors the snapback is the

consequence of the electric field localization at N /N diffused junction (anode/N-

well) because of the N-well avalanche under high current conditions: the more holes

are produced by impact ionization, the more the electric field becomes confined into a

smaller region close to N /N junction, keeping its peak almost constant.

This implies a reduction of the voltage and is externally seen as a snapback: note

that this mechanism is current controlled because a production of minority carriers in

the order of background doping of the N-well is needed to alter the integrated electric

field in the Poisson equation.

A similar phenomenon happens in the structures under study as can be verified

from the localization of the electric field ( , in which its values are pictured for

different biasing points). At the point A (low current) there are two main components:

one due to the built-in voltage across N /P source/back-gate contact and an other one

behind the drain corner under the gate oxide edge.

The latter is always present and it is due to the depletion of the diffused junction

N /N when a positive potential is applied to the drain while the gate is grounded.

When the device reaches the holding voltage (at the point D) the electric field is com-

pletely confined near the N /N junction. Then the concept of the drift region

breakdown seems likely applicable in these structures too.

It is important to remark that in this particular structure the electric field con-

finement may also be viewed as the Kirk effect in the lateral bipolar structure formed by

N /P /N /N . This is a current controlled mechanism too, which takes place in

bipolar transistors with a lightly doped epitaxial collector region under high current

injection condition when the collector current requires more electrons than available

through the doping [2].

With reference to the structures under study, the Kirk effect manifests itself in

the following way: from the simulated characteristic shown in , it is possible

to note that for V up to 2V (point A) only a small MOS channel current can flow

across the reverse biased N /P junction. A further increase of the applied voltage

causes the avalanche of this junction, as can be figured out from the considerable

increase of the drain current between V =2V and V =6V (point B, 6 orders of magni-

tude). The generated electrons current is drifted towards the positive drain contact.

Chapter 3

Figure 10

6.III.c Another point of view: the Kirk effect

I(V) Figure 8

+ -

+ -

+ +

+

+

+ - +

-

EPI

EPI

EPI

DRAIN

EPI

D D

Simulation results


- 126 -

Chapter 6

When the electrons density injected in the epitaxial region exceeds its doping

level, the sign of the space charge term in the Poisson equation changes from positive

to negative. Then the electric field flow-lines end in the free electrons carrying the

current and the whole space charge region is moved towards the edge of the N /N

diffused junction. As a consequence, the high field region is relocated from the N /P

to the N /N diffused junction.

A cross-section of the electric field in three different biasing points (low cur-

rent, avalanche and snapback) along a line under the gate is shown in : the

electric field relocation is apparent. A second aspect worth noting is the triangular

shape of the electric field, similar to the profile shown by a bipolar transistor under high

injection conditions: this particular shape means that [7] in addition to the limiting

current density there is also a space-charge limited component.

EPI

EPI

EPI

+

-

+

Figure 11

Figure 11: Simulated electric field for different biasing points along a section under the gate.

0.0E+00

2.0E+05

4.0E+05

6.0E+05

8.0E+05

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Distance (�m)

Ele

ctr

icF

ield

(V/c

m) A

B

C

P- NEPI P

+

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

StandardA

BC

The Kirk effect has been found to be responsible for performance limitations in

similar lateral LDMOS devices [8]. From the above analysis it is also clear that the Kirk

effect sets in as soon as a critical value of the current is reached. This value is given by

the current density needed to alter the charge term in the Poisson equation inside the P

/N depletion region [2].

-

EPI

Simulation results


- 127 -

Chapter 6

That is:

in which it has been supposed that all the carriers move with their saturated velocity.

By considering a junction area of 2*10 cm (depth=2*10 cm and width=10 cm -2D

simulations are normalized to 1 m width-) the currents required to initiate Kirk effect

as a function of the epitaxial doping are reported in .

-9 2 -5 -4

�

Table 1

sec/104.2ewher7cmvvqNJ SATSATEPIKIRK ��

NEPI (cm-3

) JKIRK (A/cm2) IKIRK (A/�m)

1e15 3.8e3 7.6e-6

5e15 1.9e3 3.8e-5

1e16 3.8e4 7.6e-5

Table 1: Calculated values for the onset of the Kirk effect.

The characteristic as a function of the epitaxial doping is shown in

: note that the current flowing before the Kirk effect takes place increased as a

consequence of the varied breakdown voltage of the P /N junction. With reference

to the calculated values in , it is clear that the larger the number of carriers is, the

later the onset of the Kirk effect is reached and the current tends to saturate.

I(V) Figure

12

Table 1

-

EPI

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

Epi dop=1e15 cm-3

Epi dop=5e15 cm-3

Epi dop=1e16 cm-3

Figure 12: Simulated effect of changing the drift region doping.

Simulation results


- 128 -

Figure 14: Comparison between the LDMOS drain characteristic and the “equivalent bipolar”collector characteristic.

Chapter 6

Since the Kirk effect is typically a bipolar effect and in the library of our process

many bipolar structures were available (showing a DC behavior comparable with the

results reported in , and ), we simulated a bipolar device ( ) with the

same features as the structure in .

Figures 4 5 6 Figure 13

Figure 7

For the sake of comparison, the drain characteristic of the LDMOS is superim-

posed to the collector characteristic of the equivalent bipolar structure ( ). At

low voltage (V up to 2V) in the bipolar device the collector-base leakage takes place

instead of the channel current in the MOS structure; for larger voltages, the behavior is

similar, confirming the bipolar nature of the mechanism leading to the breakdown of

the drift region.

Figure 14

COLL

Figure 13: Simulated bipolar structure with the same features as the simulated LDMOSt.

1.0E-16

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12VDRAIN, COLLECTOR (V)

I DR

AIN

,C

OL

LE

CT

OR

(A/ �

m)

Standard

Bipolar

Simulation results


- 129 -

Figure 15: Simulated effect of changing channel (intrinsic base) length through definition of lateraljunction spreading.

Chapter 6

6.III.d DIBL effect

Figure 15 I(V)

It should be also noted that the DIBL (Drain Induced Barrier Lowering) effect

might play a role in the enhancement of the leakage current before the Kirk effect takes

place. This effect manifests itself with the effective reduction of the channel length by

increasing the drain voltage: the drain depletion region moves closer to the source

depletion region, resulting in a significant field penetration from the drain to the source.

Due to this field penetration the threshold voltage is lowered, resulting in

increased injection of electrons by the source over the reduced channel barrier, giving

rise to increased drain current [9]. In the effect in the characteristic of

changing the channel length (through the analytical definition of the back gate junction

lateral spreading) is shown: it is apparent the enhanced leakage for short channel length

as a result of threshold voltage reduction due to DIBL effect.

1.0E-15

1.0E-13

1.0E-11

1.0E-09

1.0E-07

1.0E-05

1.0E-03

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

Base=-0.050

Base=-0.025

Standard

Base=+0.025

Base=+0.050

Moreover, the enhanced leakage due to DIBL effect causes the Kirk effect to set

in earlier: this results in a reduction of the snapback voltage. It is interesting to note that

if in the bipolar structure shown in the lateral spreading of the base junction is

varied as we did for the LDMOS (thus reducing the intrinsic base resistance), the

characteristics reported in are obtained. It is clear that the leakage current

characteristic is not significantly affected by modulating the base junction.

Figure 13

Figure 16

Simulation results


- 130 -

Chapter 6

This fact confirms that the phenomenon we experienced in the LDMOSt's was really

DIBL effect.

6.III.e Breakdown behavior of LDMOSt

I(V) Figure 8

Figure 17

We now have the sufficient background to explain the parasitic bipolar action in

the devices under study. For this purpose the current density at different biasing points

is analyzed. With respect to the simulated DC characteristic shown in , at

the point A ( ) the leakage of N /P junction flowing along the MOS channel

(that might be enhanced by DIBL effect) is well visible.

EPI

-

1.0E-15

1.0E-13

1.0E-11

1.0E-09

1.0E-07

1.0E-05

1.0E-03

0 2 4 6 8 10 12VCOLL (V)

I CO

LL

(A/ �

m)

Bip+0.50

Bip+0.25

Bipolar

Bip-0.25

Bip-0.50

Figure 16: Simulated effect of varying the base length in the bipolar structure shown in .Figure 13

Figure 17: Total current at the point A.density

Simulation results

Gate


Gate Gate

- 131 -

Chapter 6

For higher current injection levels, because of the N /P junction avalanche combined

with the eventual enhanced leakage, the Kirk effect takes place resulting in the reloca-

tion of the electric field (and, ultimately, of the N /P junction) close to the N /N

junction.

when in this region the electric field is large enough to cause impact

ionization there is a production of electron-hole pairs: electrons recombine at the drain

contact and holes are traveling towards the P contact increasing the voltage drop

across the back gate region, resulting in the local biasing of the base/emitter (source-

back gate) of the lateral parasitic bipolar structure ( , current density at the

snapback voltage).

EPI

EPI EPI

-

- +

+

Snapback Voltage:

Figure 18

Figure 18: Total current at the snapback voltage.density

This represents the first important difference with the behavior of the

ggnMOSt's under high reverse biasing conditions: in the LDMOS transistors under

study the avalanche ofthe collector-base junction (speaking in bipolar terms”) cannot

be very “deep” because the low doped epitaxial region triggers the onset of the Kirk

effect already at low voltages, therefore moving the region providing the needed

current for the bipolar action from the depletion region of the collector-base junction

to the N /N junction.

It is interesting to note how the snapback voltage V depends on the doping

peak of the P junction ( ): more precisely, a decrease of doping peak causes a

decrease of V . This is understandable by noting the remarkable increase of the

current before the snapback takes place: this means that the breakdown voltage of the

“

EPI

T1

T1

+

-Figure 19

Simulation results

Gate


- 132 -

Chapter 6

N /P junction has been reduced, implying a higher avalanche current for a fixed drain

voltage. Therefore the Kirk effect takes place earlier, leading to the results shown in

.

EPI

-

Figure 19

Figure 19: Simulated effect of changing the p-well peak in the LDMOSt.doping

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

1.0E+00

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

P- peak=5e17

P- peak=3e17

P- peak=1e17

Once again, it is useful to point out that the former phenomenon is caused by a

pure bipolar mechanism and, because of that, the same results are obtained ( )

when the same experiments are carried out on the bipolar structure in .

Figure 20

Figure 13

Figure 20: Simulated effect of changing the p-well doping peak in the bipolar structure described in.Figure 13

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0 2 4 6 8 10 12VCollector (V)

I Co

lle

cto

r(A

/ �m

)

P- peak=5e17

P- peak=3e17

P- peak=1e17

Simulation results


- 133 -

Chapter 6

NDR region

Holding voltage

: when the snapback voltage is reached, the switching on phase of the

lateral parasitic bipolar structure begins and, according to the mechanisms explained in

about the behavior on N-well resistors under avalanche conditions, a NDR

regime is observed because of the conductivity modulation of the N-well region.

This represents the second important difference between the LDMOSt's under

study and the ggnMOSt's: in fact, in these devices the NDR is due to the voltage reduc-

tion across the collector-base depletion region (across which the entire applied voltage

is sustained) when the parasitic bipolar transistor begins to turn on [10] whereas in the

LDMOSt's the voltage reduction mainly occurs in the N-well region.

: the NDR regime continues until a new stable state, the holding

voltage V , is reached. Once the holding voltage V is reached the bipolar para-

sitic structure is fully turned on: in , the relevant base current and the lateral

flow of current at this biasing point confirm that the lateral parasitic bipolar structure

has been fully switched on.

Chapter 3

Figure 21

HOLD HOLD

Figure 21: Total density at the holding voltage.current

At this point the third difference between the LDMOSt's and the ggnMOSt's

manifests itself. In ggnMOSt's the holding voltage is a decreasing function of the

(forward gain) of the bipolar transistor according to the following functional relation-

ship [11]:

�F

� � nFCBBEonH VVV

1

01

��

Simulation results

Gate


- 134 -

Chapter 6

where is the base-emitter voltage at which the parasitic transistor turns on, is

the breakdown voltage of the collector-base junction and is the coefficient in the

Miller formula.

It then follows that the higher the beta is, the lower the holding voltage. But by

looking at the results pictured in (in which a change of the doping peak of the

P junction necessarily implies a change in the Gummel number in the intrinsic “base”

region and, then, of the beta of the parasitic bipolar structure), the holding voltage

changes only slightly as a function of the beta of the bipolar transistor.

This is understandable by noting that, once the parasitic bipolar structure is fully

switched on, the total voltage drop across the LDMOSt is current dependent because

of the conductivity modulation of the epitaxial region with the forced current. For this

reason devices with different Gummel number (and, then, beta) have nearly the same

holding voltage and the same behavior in the high current region.

: still the feedback mechanism leading to the snapback

conduction mode is not fully understood yet and it seems likely to be related to the

conductivity modulation of the base region (combined with the already present con-

ductivity modulation of the N-well region) because of the electrons injected, via the

channel, into the drain.

The more the electrons are flooding the channel, the more the conductivity of

the intrinsic “base” region increases: therefore more base current (and, of course, drain

current) is required to keep the base-emitter junction forward biased.

V V

n

Figure 19

BEon CB0

-

Snapback conduction mode

Figure 22: Electrons density for different biasing points along a vertical cross-section in the channel(0=surface; 0.2=junction depth).

2

4

6

8

10

12

14

16

18

0.00 0.04 0.08 0.12 0.16 0.20

Junction depth (�m)

log

co

nc.

n conc. in A

n conc. in B

n conc. in C

n conc. in D

1.0E-14

1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

0 2 4 6 8 10 12

StandardA

BC

D

Simulation results


- 135 -

Chapter 6

The conductivity modulation of the base region is pictured in in which

the electrons concentration along a vertical cross section in the channel (0=surface,

0.2=junction depth) is shown for different biasing points. Note that because of the

above-mentioned mechanisms driving the snapback and the holding voltage, the

voltage swing between them can be very large (as found, for instance, in [12]).

The effect of the application of a voltage on the gate electrode (technique often

used with capacitative coupling to lower V ) is reported in : as expected, the

snapback voltage decreased with the increasing of the applied voltage [13]. In fact the

mobile charge induced by the MOS effect reduces the need of current to switch on the

parasitic structure and, then, reducing the snapback.

In addition, the application of a gate voltage reduces the electric field in the y-

direction caused by the N /N junction depletion due to the positive potential at the

drain contact: therefore the Kirk limit is higher and the current at which the snapback

occurs is higher. Gate coupling has been widely used in [14] to counteract the limited

performances to obtain, through very wide structures, effective ESD protection.

Figure 22

6.III.f Application of a gate voltage

Figure 23T1

EPI

+

Figure 23: Simulated effect of applying a gate voltage.

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m)

V gate=0.5V

V gate=1V

V gate=1.5V

Simulation results


- 136 -

Chapter 6

6.III.g CO-PS distance

Figure 24

The effects produced by the changes in the CO-PS (contact to poly spacing)

distance have been also investigated. In protection structures for CMOS technologies

(usually ggnMOSt's) this parameter is known to play a critical role in the performances

of the structure [10]. Conceptually it consists of an extra resistor at the drain which

enables the spreading of the stress current, “slowing down” the filamentation phenom-

enon: this means a better current sustaining capability before reaching the 2 “thermal”

breakdown which leads to an irreversible damage of the structure.

Unfortunately this phenomenon has a typical 3D symmetry and, therefore, our

2D simulations were not able to prove any current constriction phenomenon: the

results are shown in and are comparable with what we already concluded

about the increasing of the drift resistive region (snapback voltage modulated from the

increased resistivity). In particular, the snapback voltage modulation is very small

because the largest voltage drop is located in the drift diffusion region.

nd

1.0E-05

1.0E-04

1.0E-03

6 7 8 9 10 11 12VDRAIN (V)

I DR

AIN

(A/ �

m)

CO-PS minimum

CO-PS = 0.2 micron

CO-PS = 0.4 micron

Figure 24: Simulated effect of changing CO-PS distance.

Simulation results


- 137 -

6.III.h Temperature effects and failure analysis

I(V) Figure 25

So far we have performed isothermal simulations for the above-mentioned

reasons: as last step we took into account thermal boundary conditions and solved the

lattice temperature too. The characteristic ( ) does not change until Joule

dissipated power is strong enough to cause self-heating effects and create deviations

from the purely electrical characteristic.

Chapter 6

Figure 25: "Cold " versus "Hot" simulations of the DC characteristics.I(V)

0.0E+00

4.0E-04

8.0E-04

1.2E-03

1.6E-03

2.0E-03

0 2 4 6 8 10 12VDRAIN (V)

I DR

AIN

(A/ �

m) Non-Isothermal

Isothermal

It is interesting to note the distribution of the lattice temperature in the marked

biasing point: the temperature peak ( ) is located in the N /N diffused

junction region where the dissipated Joule power ( ) has a maximum.

Figure 26

Figure 27

EPI

+

Figure 27: Joule power distribution in the markedbiasing point.

Figure 26: Temperature distribution in the markedbiasing point.

Gate

0.0E+00

2.0E-04

4.0E-04

6.0E-04

8.0E-04

1.0E-03

1.2E-03

1.4E-03

1.6E-03

0 2 4 6 8 10 12

Biasing Point

Simulation results

Gate

0.0E+00

2.0E-04

4.0E-04

6.0E-04

8.0E-04

1.0E-03

1.2E-03

1.4E-03

1.6E-03

0 2 4 6 8 10 12

Biasing PointJoule Power


- 138 -

Chapter 6

Figure 29: Picture of a deprocessed LDMOS.

Gate

Drain

Source

Back-gate

Failures

The last two results confirm the importance of this region not only for the

breakdown behavior but also for the perspective in the ESD maximum sustaining

current capability. Therefore damage after a destructive ESD stress is expected to be

located in this zone.

To verify this prediction different pictures of the damaged area of the devices

just after they were broken have been taken: all pictures look like . A large spot

between the drain contact and the gate edge is apparent.

Figure 28

Drain

Gate

Source/Back-gate

Failure

Figure 28: View of the damaged area.

In particular, in a deprocessed LDMOS after a destructive stress is

pictured: some spots from the gate edge to the drain contacts are well visible. In both

cases the only part interested in the failure is the drain side.

Figure 29

Simulation results


- 139 -


6.IV Conclusions

In this chapter the behavior under high reverse biasing condition of the

LDMOS transistors designed for medium voltage applications has been investigated.

Through measurements it has been possible to assess the unsuitability of these devices

as single ESD protection element in medium voltage pins application. Through 2D

simulations the causes for the shown weakness have been analyzed in detail.

In particular, it has been found that the breakdown of the N /P junction

cannot be very “deep” because the Kirk effect takes place as soon as the injected

current becomes in the order of the epitaxial region doping, which is normally low.

Since the presence of this low doped epitaxial region is a characteristic of all DMOS-

like transistors, it follows that the Kirk effect is “intrinsic” in this kind of structure.

The Kirk effect is a current controlled phenomenon that causes the relocation

of the high field region from the avalanching N /P junction to the N /N diffused

junction, where the maximum power is dissipated. Therefore, here is located the most

likely failure site as it has been confirmed by failure analysis.

It has been shown that the snapback voltage also depends on the Kirk effect:

more precisely, the early it takes place, the lower the snapback voltage is. Many parame-

ters have been found responsible for affecting the onset of this phenomenon: the P

diffusion engineering, the N-well epitaxial doping, the DIBL effect and the gate cou-

pling. All these parameters can significantly vary the snapback voltage: it is important to

note that the first three are process dependent and therefore only gate coupling tech-

niques can lead to a modulation of the snapback voltage.

The observed NDR region, during the switching on phase of the parasitic

bipolar transistor, is caused by the conductivity modulation of the N-well low doped

region under avalanching conditions. Once the holding voltage is reached, the parasitic

bipolar structure is switched on. The feedback mechanism leading to the high current

regime mode is not fully understood yet and it seems likely to be related to the conduc-

tivity modulation of the base region (combined with the already present conductivity

modulation of the N-well region).

Three main differences between the conventional ggnMOSt's breakdown behavior and

that of the LDMOSt's under study have been pointed out.

, in LDMOS transistors the avalanche of the collector-base junction

(speaking in “bipolar terms”) cannot be very “deep” because the low doped epitaxial

EPI

EPI EPI

-

- +

-

First


- 140 -

Chapter 6

region triggers the onset of the Kirk effect already at low voltages, which moves the

region providing the needed current for the bipolar action from the depletion region of

the collector-base junction to the N /N junction.

, in LDMOS transistors the NDR is due to the voltage reduction caused

by the conductivity modulation of the avalanching N-well region, whereas in

ggnMOSt's the voltage reduction appears across the collector-base depletion region,

where the entire applied voltage is sustained, because of the turning on of the bipolar

parasitic transistor.

, in LDMOSt's the holding voltage changes only slightly as a function of

the beta of the parasitic bipolar transistor whereas in ggnMOSt's the dependence is

much stronger.

We can therefore conclude that the LDMOS transistors object of study under

high reverse DC voltage conditions showed unsatisfactory performances both in terms

of effectiveness as ESD protection structure and in terms of modulability of the

characterizing parameters with changing geometry.

Since all the parameters that can module these devices in sight of a use as single

ESD protection structure are fixed by the process (with the exception of gate coupling

technique), there is a little room for improving the performances.

[1] Murari, B., Bertotti, F., and Vignola, G.A., “Smart Power IC's”, Berlin: Springer-

Verlag, 1996.

[2] Sze, S.M., “Physics of semiconductor devices”, 2 edition, NewYork: Wiley, 1981.

[3] Appels, J.A. and Vaes, H.M.J., “High voltage thin layers devices (RESURF devices)”.

In Proceedings of IEDM, Washington, DC, 1993, pp. 238-241.

[4] ATLAS, two dimensional device simulation program, Silvaco International, Santa

Clara, 1997, USA.

[5] Amerasekera, A., Chatterjee, A., and Chang, M.C., “Prediction of ESD robustness

in a process using 2-D device simulations”. In Proceedings of 31 IRPS, 1993, pp. 161-

167.

[6] Notermans, G., “On the use of N-Well Resistors for Uniform Triggering of ESD

Protection Elements”. In Proceedings of 19 EOS/ESD Symposium, EOS/ESD

EPI

+

nd

st

th

Second

Third

6.V References

References


1997, Santa Clara, CA, pp. 221-229.

[7] Hower, P.L., Lin, J., and Merchant, S., “Snapback and Safe Operating Area of

LDMOS transistors”. In Proceedings of IEDM, Washington, DC, 1999.

[8] Ludikhuize, A.W., “Kirk effects limitations in High Voltage IC's”. In Proceedings of

ISPSD, 1994.

[9] Arora, N., “MOSFET Models for VLSI Circuit Simulation”, Wien: Springer-Verlag,

1993.

[10] Amerasekera, A., and Duvvury, C., “ESD in silicon integrated circuits”,

Chichester:Wiley, 1995.

[11] Reisch, M., “On bistable behaviour and open-base breakdown of bipolar transis-

tors in the avalanche regime modeling and applications”, IEEE Trans. Elec. Dev., Vol.

39, number 6, 1992, pp. 1398-1409.

[12] Mergens, M., Wilkening, W., Mettler, S., Wolf, H., Stricker, A., and Fichtner, W., “

Analysis and Compact Modeling of Lateral DMOS Power Devices Under ESD Stress

Conditions”. In Proceedings of 21 EOS/ESD Symposium, EOS/ESD 1999,

Orlando, FL, pp. 1-10.

[13] Polgreen, T., and Chatterjee, A., “Improving the ESD failure threshold of Silicided

nMOS output transistors by ensuring uniform current flow”. In Proceedings of

EOS/ESD Symposium, ESO/ESD 1989, New Orleans, LO, pp. 167-174

[14] Duvvury, C., Carvajal, F., Jones, C., and Briggs, D., “Lateral DMOS Design for

ESD Robustness”. In Proceedings of IEDM, Washington, DC, 1997.

st

- 141 -



Chapter

Transient Phenomenain ggnMOSt's under

TLP Conditions

Abstract: In this chapter the clamping voltage of a grounded gate nMOS transistor (ggnMOSt) under TLP

stress will be analyzed in detail by means of a mixed-mode simulator. It will be shown that the breakdown

voltage of the ggnMOSt measured in static conditions could underestimate the maximum voltage across the

protection structure obtained by TLP stress, depending on the rise-time of the applied pulse. In particular, the

smaller is the rise-time, the larger the reached peak of the drain voltage. It will be shown that this can attributed

to the charging of the overlap capacitance. The influence of the LDD implant option with respect to the

standard implant will be investigated, too. The relationship between the maximum clamping voltage and the

triggering voltage of the parasitic bipolar transistor associated to the structure will be explained. A simple

analytical model describing the response of the device in the early phase of the forced pulse will be presented.

7

7.I Introduction

As introduced in Chapter I, in CMOS technology the protection against ESD

events is usually realized with grounded gate nMOS transistors (ggnMOSt's) in

snapback conduction mode exploiting the parasitic bipolar action intrinsic in the

structure. The snapback conduction mode is reached in this way: when a positive pulse

(ESD) is applied to the drain junction (N /P substrate), it is forced in reverse biasing. In

this condition hole-electron pairs are generated inside the depletion region because of

the high value of the electric field: electrons are collected at the drain contact while the

holes are collected at the grounded substrate contact, increasing the local substrate

potential with respect to the grounded source junction.

When this local potential difference is high enough to forward bias the source-

substrate junction, electrons are injected from the source to the drain. If this parasitic

bipolar structure (Drain=Collector; Substrate=Base; Source=Emitter) has a forward

gain high enough, it can provide its own base current, keeping the structure self-biased.

Then, in this condition, the stress current associated to an ESD event is entirely sus-

tained by the parasitic bipolar transistor. The characterizing parameters of this protec-

tion structure are:

: triggering voltage of the parasitic bipolar transistor;

: minimum clamp voltage across the protection device after snapback;

: switching on time of the protection structure;

: current at which the protection structure goes in 2 breakdown ("thermal

breakdown") that leads to irreversible damage [1];

: on-resistance of the structure in snapback conduction mode.

The triggering voltage V is normally identified as the breakdown voltage of

the drain/substrate junction and it is considered as the maximum reachable value, V ,

across the structure being protected. As V determines whether a gate oxide of a

device that is protected breaks down or is latently damaged, it is important to know the

value of V under various experimental conditions.

V can be obtained through DC characterization or quasi-static measurements

like TLP (transmission line pulse) [2]. In TLP a constant high current pulse is forced

into the structure under test: with 100nsec. of pulse duration, this test has been proven

+

nd

�

�

�

�

�

V

V

t

I

R

T1

HOLDING

ON

T2

ON

T1

MAX

MAX

MAX

T1


- 144 -Transient Phenomena in ggnMOSt's under TLP Conditions

Figure 1: Simulated nMOS LDD structure.

- 145 -

Chapter 7 Simulated devices

[3] to be equivalent (that is, inducing the same kind of failure) to an Human Body

Model (HBM) pulse [4], which is the most standardized test for qualifying ESD protec-

tion structures.

The TLP rise-time depends upon the parasitic elements in the measurement set-

up and is normally in the order of few nsec. even if it may be much shorter (< 1nsec.).

In this chapter the effects of reducing through numerical simulations the rise-time of

the TLP on V will be investigated and it will be shown that in the early phase of the

response to the forced stress V can not be considered any longer as V .

The simulated devices ( ) are typical nMOSt's for 0.25 m CMOS tech-

nology with Lightly Doped Drain (LDD) implant. The LDD option is chiefly used in

short channel devices to reduce the magnitude of the electric field nearby the drain

MAX

T1 MAX

7.II Simulated devices

Figure 1 �

region, which is the main cause for hot electrons [5]. The LDD is obtained by implant-

ing a low-doped N region (P or As) with the poly gate as mask. Afterwards an oxide

spacer is grown and used to mask the following standard N As implant. The effect of

the LDD option is twofold: a reduction to around 80% of the electric field value of the

conventional N implant and a shift of the electric field in the drain contact direction

-

+

+

Transient Phenomena in ggnMOSt's under TLP Conditions

Figure 2: Effect of LDD implant on the electric field along the surface (after [5]).

Figure 3: Simulated nMOS structure with standard source-drain implant.

- 146 -

Chapter 7

( ). On the other hand this leads to an increase of the drain/source series resis-

tance, resulting into a lowering of the transconductance. Moreover, the breakdown

voltage of the drain junction is increased. On such devices, simulations in transient

regime of TL pulses by means of a Mixed-Mode Simulator (device simulator combined

with circuit simulator) implemented in Atlas by Silvaco [6] have been carried out.

Figure 2

One of the advantages of such approach consists in the possibility of setting

rise-time pulses to experimentally unlikely orders of time to better understand the

physics mechanisms involved. All the simulations refer to devices in grounded gate

configuration (therefore with all electrodes grounded with the exception of the drain

Simulated devices


0.0E+00

1.0E-01

2.0E-01

3.0E-01

4.0E-01

5.0E-01

0 2 4 6 8 10VDRAIN (V)

I DR

AIN

(A/ �

m) LDD

Figure 4: Simulated DC characteristic of the structure with LDD implant.

- 147 -

Chapter 7 Results and discussion: LDD option

one). The simulations have been performed “cold” because from a first non-

isothermal approach [7] we obtained a T not larger than 20°K during the tran-

sient that leads to the snapback conduction mode. Therefore, in first approximation,

one may neglect the thermal production of minority carriers (which is only becoming

important in the neighborhood of the 2 breakdown [8]) and one does not have to

solve for the lattice temperature too.

In order to evaluate the effect of different drain configurations, we repeated the

same simulations on a device processed in the same way as the previous one but with a

standard source-drain implant ( ).

In the simulated DC characteristic of the device pictured in (in

grounded gate configuration) is shown: the breakdown voltage V is 9.5V, V =4.7V

and R in the snapback region is approximately 14 . Note that since the simulation is

2D, the current is normalized to 1 m of width. On the same device the response to a

TLM pulse (t =100nsec. and t =10nsec.) has been simulated. The forced current

has I =7mA/ m.

�

�

�

LATTICE

T1 HOLD

ON

PULSE RISE

AMPL

nd

Figure 3

Figure 4 Figure 1

7.III Results and discussion: LDD option

�

In the drain (clamping) voltage as function of time is shown: two

aspects are worth noting. Firstly, at approximately t=1e-8sec., the parasitic bipolar

associated to the structure is completely switched on: in fact a forced current of

Figure 5


Figure 6: Total density current for the LDD structure at the

beginning of the snapback conduction mode (V =4.95V).DRAIN

Figure 5: Drain (clamping) voltage vs. time for a pulse with I =7mA/ m and t =10nsec.AMP RISE�

0

2

4

6

8

10

12

14

0.0E+00 2.0E-09 4.0E-09 6.0E-09 8.0E-09 1.0E-08

t (sec.)

VD

RA

IN(V

)

LDD-10ns

7

8

9

10

11

12

13

5.0E-11 1.5E-10 2.5E-10

t (sec.)

VD

RA

IN(V

)

gate

source

- 148 -

Chapter 7

7mA/ m corresponds to a voltage across the structure of 4.95V, which is exactly the

same value we found for the DC case at the beginning of the snapback conduction

mode. Moreover, by looking at the total current density distribution for t=1e-8sec.

( ), we can clearly figure out that the current is mainly lateral, therefore confirm-

ing the parasitic bipolar action.

The second and more important aspect we can derive from is the maximum

value of the drain voltage (V =12V), which is exceeding the static breakdown

voltage (V =9.5V). This peak appears in a very short time (t =1e-10sec.) compared

to the switching on time of the parasitic bipolar.

�

Figure 6

Figure 5

DRAIN-PEAK

T1 PEAK

Results and discussion: LDD option


Figure 8: Electric Field distribution corresponding to the peak of the drain voltage (t =100 psec.).RISE

0

5

10

15

20

25

30

35

1.0E-11 1.0E-10 1.0E-09 1.0E-08

tRISE (sec.)

VP

EA

K-D

RA

IN(V

) V peak-drain (V)

Figure 7: Dependence of the maximum value of the drain voltage as a function of the rise-time.

Gate

- 149 -

Chapter 7

In order to figure out the origin of this extra contribution to the clamping

voltage, we reduced the rise-time of the forced pulse (while keeping its amplitude at

7mA/ m) to physically unlikely values to pinpoint the cause for the phenomenon.

In the maximum value of the drain voltage as a function of the applied rise-

time is shown: the smaller the rise-time, the larger the reached peak of the drain voltage.

�

Figure 7

In the electric field distribution corresponding to the peak of the drain voltage

(for a rise-time of 100psec.) is pictured: in the silicon the maximum electric field is

located in the LDD region whereas in the oxide it is near the edge of the poly gate.

Figure 8



Figure 10: I , I and V vs. t for a pulse with I =7 mA/ m and t =100 psec.GATE DRAIN DRAIN AMP RISE�

Figure 9 Figure 8.: Hole concentration in the same biasing point as in

gate

0

5

10

15

20

25

0.0E+00 1.0E-11 2.0E-11 3.0E-11t (sec.)

VD

RA

IN(V

)

-2.E-03

-1.E-03

0.E+00

1.E-03

2.E-03I D

RA

IN,I G

AT

E(m

A/ �

m)

Vdrain

Idrain

Igate

- 150 -

Chapter 7

In the same biasing point the hole concentration is far above its equilibrium

level and it is located in correspondence of the electric field peak ( ). These two

facts suggest that the extra voltage at the drain be due to the charging of the overlap

capacitance with holes displaced by capacitative effect.

Figure 9

In particular, if we look at the current distribution for the same previous structure

( ), we notice that the gate current component is very relevant for the peak

voltage.

Figure 10



0

5

10

15

20

25

0.0E+00 1.0E-11 2.0E-11 3.0E-11t (sec.)

VD

RA

IN(V

)

LDD-100ps-7mA/umLDD-100ps-10mA/umLDD-100ps-15mA/umLDD-100ps-20mA/um

Figure 12: Effects of changing the amplitude of the forced pulse from 7

mA/ m to 20 mA/ m with t =100 psec.� � RISE

Figure 11: Dependence of the maximum value of the gate current as a function of the rise-time.

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

3.0E-03

3.5E-03

4.0E-03

1.00E-11 1.00E-10 1.00E-09 1.00E-08

tRISE (sec.)

I GA

TE

-PE

AK

(A/ �

m)

I gate-peak (A/um)

- 151 -

Chapter 7

Moreover, the peak of the gate current as a function of the rise-time ( )

confirms our hypothesis: the higher the rise-time, the higher the number of the holes

displaced by capacitative effect and, therefore, the charging of the overlap capacitance.

Figure 11

In the effects of changing the amplitude of the forced pulse (while

keeping t =100psec.) are reported. The effect is twofold: a higher value of the maxi-

mum drain voltage with the larger current density and a shorter time to reach the peak

for the same case.

Figure 12

RISE



0.0E+00

5.0E-02

1.0E-01

1.5E-01

2.0E-01

2.5E-01

0 2 4 6 8 10VDRAIN (V)

I DR

AIN

(A/ �

m) Standard S-D

implant

Figure 13: Figure 3Simulated DC characteristic of the structure without LDD implant as pictured in .

- 152 -

Chapter 7

These effects can be explained as follows: fixing the rise-time but varying the

forced current means increasing the current density or, in other words, the dI/dt of the

forced pulse. This is equivalent to reducing the rise-time. This implies that during

stepped current TL measurements the last zaps are more severe that the first ones not

only because of the increased current but also because of the higher charging of the

overlap capacitance.

Since this mechanism drives the behavior of the clamping voltage, we will

perform the same experiments on a structure with different overlap capacitance to get

more insight about its influence.

If the same experiments are done with a standard source-drain implant (being

all the others process parameters kept constant), the simulated DC characteristics are

pictured in : the breakdown voltage V is 8.2V and V =3.1V. These differ-

ences with respect to the LDD configuration are expected due to the different resistiv-

ity of the implanted regions. On this structure we simulated the response to the same

current pulses we forced in the device with LDD. The forced current has amplitude of

7mA/ m, corresponding (by looking at the simulated DC characteristic) to a voltage

of 3.5V when the transient is over.

7.IV Results and discussion: non-LDD implant

Figure 13 T1 HOLD

�

Results and discussion: non-LDD implant


10

15

20

25

30

35

1.0E-11 1.0E-10 1.0E-09 1.0E-08tRISE (sec.)

VP

EA

K-D

RA

IN(V

)

Vpeak-drain:LDD

Vpeak-drain:Non-LDD

Figure 14: Dependence of the maximum value of the drain voltage as a function of the rise-time and of

the drain implant option.

- 153 -

Chapter 7

In the results of the same analysis presented in (superimposed

to for convenience's sake) are shown: the dependence of the maximum drain

voltage during the transient as a function of the rise-time of the applied current pulse.

The results are comparable with what already reported in LDD device (an increase of

the voltage peak with reducing the rise-time), but the maximum voltages are always

smaller. This suggests that the different geometry plays a role in this: we note, in partic-

ular, that the overlap capacitance has changed. In the next paragraph we will, then,

focus on its analytical evaluation.

Figure 14 Figure 7

Figure 14

Results and discussion: non-LDD implant


LlOV lOV

Gate

tOX

DS

CGS0 CGD0

LlOV lOV

Gate

tOX

DS

C1

�1 �1

C2 C2

C1

C3 C3

Figure 15: Different contribution to the overlap capacitance: basic model (a), model proposed in [12] (b).

(a) (b)

- 154 -

Chapter 7 Overlap capacitance evaluation

1)Eq.(F)000 OVOXOV

OX

SiGDGS WlCWl

tCC ��

��

2)Eq.(F/cm)00 OVOXgdgs lCCC ��

7.V Overlap capacitance evaluation

In self-aligned processes the gate overlap capacitance is due to the lateral diffu-

sions of the drain-source junctions in consequence of the wafer heating in the last

fabrication steps ( ). Since drain and source are normally symmetric it is

convenient to consider the overlap distance, , equal for the two junctions. Still, it must

be noted that in very shallow junctions, implant shadowing can be caused by off-axis

S/D implants, leading to a different for the two sides.

Figure 15a

l

l

OV

OV

By using the parallel plate formulation, the overlap capacitance C and C can be

approximated to:

GS0 GD0

By defining C and C as the overlap capacitance per unit width (F/cm) for the gate-

source and for gate-drain, becomes:

gs0 gd0

equation 1

In reality, there are other components that must be considered to properly evaluate the

overlap capacitance.

In fact we should also take into account ( ) C (fringing capacitance on the

outer side between gate and source-drain) and C (fringing capacitance on the inner side

between gate and the side wall of the source-drain junction). In [9] the three compo-

Figure 15b 2

3


5.0E-17

1.5E-16

2.5E-16

3.5E-16

4.5E-16

-2 -1 0 1 2VGATE (V)

Cg

ate

-dra

in(F

/ �m

) Non-LDD

LDD

Figure 16: Simulated AC analysis to extract the gate-drain overlap capacitance for LDD and Standard

structures.

- 155 -

Chapter 7

� � 3)Eq.sin1ln2

1ln 1

1

321

��

��

��

��

��

��

OX

JSI

OX

polyOXOVOXgdogso

t

X

t

tlCCCCCC

nents have been modeled as follows:

where accounts for the poly gate slope ( ) in the calculation of C . Note that there

exists an overlap capacitance even in the case of no lateral diffusion under gate. In

particular C >C because ~3 .

The overlap capacitance is both gate and drain voltage dependent, typically in

the LDD case because of the conductivity modulation of the lightly doped region [10,

11]. In [12] the bias dependence of the overlap capacitance has been similarly modeled

to a junction capacitance. We therefore simulated the gate-drain overlap capacitance of

both structures (with and without LDD option implant) using AC analysis: the small

signal AC response is solved at a frequency of 1 MHz. The V is fixed at 0V whereas the

gate is swept from -2V to +2V.

The simulation results are reported in : it is interesting to note that for

V =0V the overlap capacitance of the structure with LDD implant is smaller than that

with standard implant (around 25%).

� �

�

1

Figure 16

1

2 3 Si OX

D

G

�

Overlap capacitance evaluation


- 156 -

Chapter 7

4)Eq.)(

),()(dt

tdVVVCtI D

DGOVD �

5)Eq.[A/sec.].constdt

dID ��

6)Eq.)(

),( ��

��

� ��dt

tdVVVC

dt

d

dt

dI DDGOV

D

7)Eq.)(),()(

),(2

2

tVdt

dVVC

dt

tdVVVC

dt

dDDGOV

DDGOV ��

��

��

8)Eq.)(2

2

tVdt

dC DOV ��

9)Eq.2

)( 22 ��

�� tttC

tC

tVOVOV

D

In order to find out a quantitative relationship between the rise-time and the

clamping voltage behavior in the time-domain in which only the overlap capacitance is

involved, one should solve:

where C accounts for all the three components in .

The forced current pulse is characterized by a rise-time coefficient given by:

OV equation 3

�

Differentiating with respect the time, we obtain:equation 4

and then:

But since we are dealing with grounded gate configuration (V =0V), if we assume that

C is only slightly variable with V (and, then, with t), the whole first term in the right

side of can be neglected. Therefore, becomes:

G

OV D


By integrating twice, we finally get:



y = 2E+23x2

- 7E+11x + 1.0181

0

5

10

15

20

25

0.0E+00 4.0E-12 8.0E-12 1.2E-11t (sec.)

VD

RA

IN(V

)

LDD-100ps rise-time

Quadratic Fitting

Figure 17: Trend line of the simulated V (t) (with I =7 mA/ m and t =100 psec.).D AMP RISE�

- 157 -

Chapter 7

��

��

�

��

��

�� Fsec.m

A1033,2

105,12

107

2

23

16

7

��

�OVC

where and are constants dependent on the imposed boundary conditions after each

integration.

From we have that:

Increasing (that is, decreasing the rise-time if the pulse amplitude is constant)

leads to an increase of the maximum clamping voltage: this explains the depend-

ence pictured in and .

A decrease in C leads to an increase of the maximum clamping voltage: this

explains why in LDD structure (that has a lower C ) the maximum clamping

voltage is higher.

To check the validity of , we fitted the simulated V (t) for all the rise-

times. In the trend line of the simulated V (t) (with I =7mA/ m and

t =100psec.) for the domain corresponding to the solution of (then involv-

ing only the loading of the overlap capacitance) is shown. A second order polynomial

expression shows a very good fitting with the simulated curve.

� �

�

�

equation 9

Figure 7 Figure 11

equation 9

Figure 17

equation 8

�

� OV

OV

D

D AMP

RISE

Note that, according to and the value of C extracted from the simulation in

with V =0V, the coefficient of the second order term is:

equation 9

Figure 16

OV

G �



- 158 -

Chapter 7 V versus VMAX T1

BEonCBT VVV �� 01

which corresponds (within an error of 16%) to the same value of the exact fitting as

reported in . The error in the coefficient is expectable from the fact we are

dealing with a simple first order analysis.

The exact value of comes up from the correct solution of : if we had

considered the rigorous solution (by removing the hypothesis of overlap capacitance

independent from the drain voltage), we would have faced a not trivial differential

equation. But, still, the correct qualitative behavior, in spite of the approximation,

states that the analysis is correct. Therefore it provides another prove that the extra

voltage at the drain electrode is due to the loading of the overlap capacitance.

In quasi-static conditions V (triggering voltage of the bipolar parasitic structure) is

expressible as:

Figure 17

equation 7

�

�

7.VI V versus VMAX T1

T1

where V is the breakdown voltage of the collector-base junction and V the

voltage at which the emitter base junctions begins to emit electrons (in nMOSt's). To

understand the difference between the maximum clamping voltage across the device,

V , and V it is fundamental to note that the triggering mechanism for the bipolar

action is current controlled, as only current can increase V .

In the considered case this current is constituted by the holes generated by

impact ionization in the depletion region of the collector-base junction. To account for

this mechanism, in the compact modeling of ggnMOSt's under ESD conditions, an

avalanche current generator is inserted between collector and base nodes [13].

But ANY other mechanism (gate coupling, substrate biasing) providing the same

current in the same direction would achieve the same goal: V is lowered because less

hole current is needed from the reverse junction to trigger the bipolar, or in other

words, the junction does not need to be forced into a "deep" breakdown.

In transient conditions, an extra current contribution is provided by the collec-

tor-base capacitor displacement current (holes in ggnMOSt's) dV/dt, experimentally

identified in earlier studies with e-beam and electro-optic sampling [14]. The amount

of current displaced depends upon the rise-time and might, as limit case, disable the

CBO BEon

MAX T1

BE

T1


COV

DC Domain

CCB

CEB

IAV

RSUB

{{ {t >100psec.RISEt <100psec.RISE

Transient Domain{

Figure 18: Compact model of the ggnMOSt showing the different time-domains.

- 159 -

Chapter 7

junction from going into breakdown and still triggering the bipolar.

The effect is the same as before, a lowered V , for the same reasons (not-deep break-

down).

There is no contradiction between this concept and our simulations results. In

fact, the maximum clamping voltage is NOT the triggering voltage. The loading of the

overlap capacitance does not play any role in the turning on of the bipolar structure

because is physically located "outside" the bipolar. In fact the turning-on time of the

bipolar (defined as the time needed to reach a steady state situation) does not depend on

the rise-time but mainly on the base transit time, which is in the order of 100psec. for

the considered gate length [15].

We are, therefore, dealing with pre-triggering effects: when a TL pulse is forced

into a ggnMOSt, the overlap capacitance is charged up. The charging of the overlap

capacitance drives the drain voltage and it increases with reducing the rise-time. Later

the junction capacitance takes over. The charging of the overlap capacitance helps the

triggering of the bipolar and, dependently upon the rise-time, reduces the voltage

across the reversed collector-base junction (and not the WHOLE device). Still it is very

difficult to analytically assess when the junction capacitance takes over the overlap

capacitance, being both voltage dependent.

T1

V versus VMAX T1


Figure 19: Electric field distribution corresponding to the maximum reached drain voltage (t =100

psec. and I =7 mA/ m) for LDD (a) and Standard (b) structures.

RISE

AMP �

aDrain

bDrain

- 160 -

Chapter 7 Soft failures

Finally, it should be noted that for rise-times larger than 100psec. the extra-

voltage due to the overlap capacitance is very limited. We can, therefore, summarize the

modeling of a ggnMOSt under TL stress as in : under DC condition the usual

bipolar parasitic structure in parallel with the ggnMOSt (to account, eventually, for gate

coupling) and the avalanche generator are shown. By considering the transient regime,

according to the rise-time of the applied pulse, junction capacitance and overlap

capacitance are taken into account. Note that they are not in parallel, which explains the

different loading times.

Another aspect worth noting is the electric field distribution corresponding to

the peak of the clamping voltage (with t =100psec.) from the two different structures

(LDD and Standard). As clearly shown in in the LDD structure the electric

field is entirely extended all over the LDD region (not only under the gate), whereas in

the standard structure ( ) it is confined across the reverse junction mainly

under the gate.

Since its appearance, the LDD option has shown a worsening in terms of ESD

performance [16]. In particular LDD devices are sensitive to low level (not destructive)

stress. This stress can induce “soft failures”: they appear as small filaments in the drain

region [17] and lead to an irreversibly increased leakage current that might not meet the

requirements for a given logic.

Figure 18

Figure 19a

Figure 19b

7.VII Soft failures

RISE


Figure 20: Joule Power distribution corresponding to the maximum reached drain voltage (t =100

psec. and I =7 mA/ m) for LDD (a) and Standard (b) structures.

RISE

AMP �

(a)

(b)

- 161 -

Chapter 7

Many explanations have been given in literature: local heating of the LDD

region [18], non-uniform current flow [19], increased channel length [20]. In [21] soft

failures have been investigated in detail: the increased non-catastrophic leakage I

(Sub Surface Breakdown) was attributed (with the help of 2-D simulations) to an extra

dissipative spot just below the surface, underneath the gate.

Since in this position the cooling might be penalized by the presence of the

oxide, an early subsurface second breakdown might occur. By looking at Joule power

dissipated (which is one of the main indicators of the ESD robustness [22]) at the same

biasing points as in , we note that ( and ) the concept of a

“hot” spot of the dissipated power underneath the channel is applicable in our simula-

tions, too.

SSB

Figure 19 Figure 20a Figure 20b

But, unlike [21] the standard structure does show a peak, too. The difference is that in

the LDD case the peak in much more focalized in to a smaller area and with a higher

magnitude.

This would explain why by leaving out the LDD implant the subsurface break-

down still occurs but at higher current level, without affecting the second breakdown

level [23]. By comparison between and one can see that the “hot”

spot of the dissipated power is located where the electric field reaches its maximum

levels. Then one might argue that, once again, the overlap capacitance comes into play

(by driving the electric field) in the observed

Figure 19 Figure 20

“soft failures”.

Soft failures


RVIN

VSSPrimaryInput

SecondaryInput

Part to beprotected

A B

Figure 21: Typical p-network showing primary and secondary input protection elements.

- 162 -

Chapter 7 Latency aspects

7.VIII Latency aspects

The main objectives of a protection device are:

the high current stress

the voltage across the protected circuitry

In CMOS technology input/output buffers require a protection that clamps the

voltage that, during an ESD event, could cause irreversible failure (rupture) of the gate

oxide. Being the breakdown voltage (V ) the maximum voltage across the protected

device, it is compulsory to maintain a margin between this voltage and the gate oxide

breakdown (BV ) to avoid oxide failures. The gate oxide breakdown (BV ) is a critical

function of its thickness. But with the scaling down of the device sizes, thin-oxides are

also reduced, implying a decrease of the BV . If no extra drain engineering is per-

formed, V can exceed BV . In this situation oxide failures are very likely [24].

The typical solution for this case is to move the protection structure towards a

more complicated (and wafer consuming) layout in which some form of clamping

prevents a too high value of the voltage “seen” at the oxide. In a typical p-

network it is shown: the secondary input serves to provide a protection during the

switching-on of the primary protection, which has to sustain the largest part of cur-

rent.

�

�

shunting

clamping

T1

OX OX

OX

T1 OX

Figure 21


- 163 -


But as we have shown, overvoltages can appear across the gate during the rise-

time, largely exceeding the value of V . Although BV during pulsed events can

significantly be larger than in DC conditions, it is debatable whether these very fast

overvoltages can cause damages: in [25] hypotheses about latent damage of ultra-thin

gate oxide during non-destructive, ESD-induced overvoltages were presented.

What we could note from our analysis is:

the overvoltage due to the loading of the overlap capacitance appears in a very

short time. In particular, when the peak of the clamping voltage increases (due

to the reduction of the rise-time), the time-domain in which it appears is

reduced.

the use of the secondary input protection in the p-network has a beneficial

effect not only for the extra clamping but also because it introduces a delay in

the propagation of the voltage“seen” at the node B: in fact, there is a delay due

to the RC network of the secondary input protection stage, before the voltage in

A propagates in B.

In this chapter it has been shown, through simulations, how during the early phase of a

TLP like stress in a ggnMOSt it is possible to reach voltages even exceeding the trigger-

ing voltage V of the associated parasitic bipolar structures.

Since the breakdown voltage of the gate oxide, BV , during pulsed events is

significantly larger than in DC conditions, it is debatable whether these very fast

overvoltages can cause damages.

They appear in a very short time and this has two consequences:

the pulse has very little energy; in particular, when the peak of the clamping

voltage increases (due to the reduction of the rise-time), the time-domain in

which it appears is reduced (and then, its energy);

since for a rise-time of 100psec. the maximum clamping voltage is reached in

few tens of psec. we are dealing with a time-domain in which any experimental

verification is extremely problematic.

T1 OX

T1

OX

�

�

�

�

7.IX Conclusions


- 164 -


It has been assessed that the charging of the overlap capacitance with holes

displaced by capacitative effect causes these overvoltages. This has also been con-

firmed by the dependence of the maximum reached voltage on the rise-time of the

applied pulse. It has been found that in devices with LDD implant the maximum

clamping voltage reached during the transient is higher than that of analogous devices

with standard drain-source implant, which is due to the reduction of the overlap

capacitance.

[1] Amerasekera, A., Roozendaal, L.van, Bruines, J. and Kuper, F., “Characterization

and Modeling of Second Breakdown in NMOST's for the Extraction of ESD-Related

Process and Design Parameters”. IEEE Tran. El. Dev. 1991; 38(9), pp. 2161-2168.

[2] Maloney, T. and Khurana, N., “Transmission Line Pulsing techniques for circuits

modeling of ESD phenomena”. In Proceedings of 7 EOS/ESD Symposium,

EOS/ESD 85, Minneapolis, MN, September 1985, pp. 49-54.

[3] Pierce, D.G., Shiley, W., Mulcahy, D., Wagner, K.E. and Wunder, M., “ Electrical

Overstress Testing of a 256K UVEPROM to Rectangular and Double Exponential

Pulses”. In Proceedings of 10 EOS/ESD Symposium, EOS/ESD 88, Anaheim, CA,

September 1988, pp. 137-146.

[4] Amerasekera, A. and Duvvury, C., “ESD in silicon integrated circuits”. Chichester:

Wiley, 1995.

[5] Ogura, S., Tsang, P.J., Walker, W.W., Critchlow, D.L. and Shepard, J.F., “Design and

characteristics of the lightly doped drain-source (LDD) insulated gate field-effect

transistor”. IEEE Trans. Electron Devices 1980; ED-27, pp. 1359-1367.

[6] Silvaco International. ATLAS, Device simulation software. Santa Clara, CA, 1997.

[7] Russ, C., Kreisbeck, J., Gieser, H., Guggenmos, X. and Kanert, W., “Electrothermal

Device Simulation of a gg-nMOSt under HBM ESD conditions”. In Proceedings of 6

ESREF Conference, ESREF 95, Bordeaux, France, October 1995, pp. 141-146.

[8] Amerasekera, A., Chang, M.C., Seitchik, J.A., Chatterjee, A.K., Mayaram, K., and

Chern, J.H., “Self-Heating Effects in Basic Semiconductor Structures”. IEEE Trans.

Electron Devices 1993; 40(10), pp. 1836-1844.

[9] Shrivastava, R. and Fitzpatrick, K., “A simple model for the overlap capacitance of a

VLSI MOS device”. IEEE Trans. Electron Devices 1982, ED-29, pp. 1870-1875.

7.X References

th

th

th


- 165 -

Chapter 7

[10] Smedes, T. and Klaassen, F.M., “Effects of the lightly doped configuration on

capacitance characteristics of submicron MOSFET's”. In Proceedings of IEEE

IEDM 1990, Technical Digest, pp. 197-200.

[11] Arora, N.D., Bell, D.A. and Bair, L.A., “An accurate method of determining

MOSFET gate overlap capacitance”. Solid-State Electronics 1992, 35, pp. 1817-1822.

[12] Lee, S.W. and Rennick, R.V., “A compact IGFET model ASIM”. IEEE Trans.

Computer Aided Design 1988,CAD-7, pp. 952-975

[13] Hsu, F., Miller, R. and Hu, C., “A simplified model for short-channel MOSFET

characteristics in the breakdown mode”. IEEE Trans. Electr. Devices 1993, 40, pp.

571-576.

[14] Luchies, J.R.M., Kort, C.G.C.M.de and Verweij, J.F., “Bipolar transient turn on of

an ESD protection circuit”. In Proceedings of 5 IEEE Workshop, ProRISC 94,

Mierlo, The Netherlands, pp. 151-155.

[15] Muller, R.S. and Kamins, T.I., “Device electronics for integrated circuits”. 2 ed,

NewYork: Wiley, 1986.

[16] Duvvury, C., McPhee, R.A., Baglee, D.A., and Rountree, R.N., “ESD protection

reliability in 1 m CMOS technologies”. In Proceedings of IRPS 1986, pp. 199-205.

[17] Dickson, N. et al., “An investigation into the bake reversible low level ESD induced

leakage”. SPIE Vol. 1082, Microelectronics Manufacturing and Reliability 1992, pp.

155-166.

[18] Amerasekera, A., Roozendaal, L.van, Abderhalden, J., Bruines, J. and Sevat, L., “An

analysis of low voltage ESD damage in advanced CMOS processes”. In Proceedings of

12 EOS/ESD Symposium, EOS/ESD 1990, pp. 143-150.

[19] Othani, S. and Yoshida, M., “Model of leakage current in LDD output MOSFET

due to low-level ESD stress”. In Proceedings of 12 EOS/ESD Symposium,

EOS/ESD 1990, pp. 177-181.

[20] Chen, K.L., “The effects of the interconnects process and snapback voltage on the

ESD failure threshold of NMOS transistors”. IEEE Trans. Electron Devices, Vol. 35

(12), 1988, p. 2140.

[21] Kuper, F., Luchies, J.M. and Bruines, J., “Suppression of soft ESD failures in a

submicron CMOS process”. In Proceedings of 15 EOS/ESD Symposium,

EOS/ESD 1993, pp. 117-122.

[22] Amerasekera, A., Chatterjee, A., and Chang, M-C., “Prediction of ESD robustness

in a process using 2-D device simulations”. In Proceedings IRPS 1993, pp. 161-167.

[23] Luchies, J.M., “Electrostatic discharge in integrated circuits: testing and protec-

th

nd

th

th

th

�

References


Chapter 7

- 166 -

tion”, Ph.D. thesis, University of Twente (The Netherlands), 1995, p. 69.

[24] Amerasekera, A., Abeelen, W.van den, Roozendaal, L.van, Hannemann, M., and

Schofield, P., “ESD failures modes: Characteristics, Mechanisms and Process

Influences”. IEEE Trans. Electron Devices, ED-39, p. 430-435, 1992.

[25] Keung, K.P., “Plasma-charging and ESD, help each other?”. In Proceedings of 21

EOS/ESD Symposium, EOS/ESD 1999, pp. 8-42.

st

References


Chapter

Abstract: in this final chapter the summary of this thesis will be presented. The most important results of each

chapter will be reviewed. Finally, some recommendations for future research will be suggested.

Conclusions

8

Chapter 8 Summary

- 168 -Conclusions

8.I Summary

Electrostatic Discharge (ESD) is a common phenomenon in the nature: when a

statically charged material is put in contact with a grounded object, charge balance will

be restored through a discharge of the charged material towards the ground. In spite of

the phenomenon's name, the discharge is extremely fast, in the order of some tens of

nanoseconds. Furthermore, electrostatic potential of several KV's and discharge

current up to several amperes are not unusual. IC's are not immune to ESD, as the high

current (and, eventually, the high voltage) can cause irreversible failures to the devices:

it has been quantified that ESD (together with the EOS - Electrical Overstress - of

which ESD is a subset) constitutes about 38% of the overall field returns. Given the

major impact of ESD in IC's reliability, there is a strong need of developing protection

strategies.

There are two possible ways to tackle the problem. The first way is “external” and

consists in minimizing the potential causes of risk (neutralization of static charges

through air ionizers, shielded bags, grounded wrist straps during IC's handling and so

on). The second way of protecting an IC from an ESD event is “internal” and consists

in implementing an “on-chip” protection circuit. The design of an effective protection

circuit is a very complex task that may require several iterations. In fact, during and ESD

event protection structures are forced to work under high injection conditions in which

an electro-thermal interaction in a very short time frame takes place. In spite of the

many studies available on the subject, there is still a lack of modeling of the devices

behavior up to very high injection level.

For this reason, in this thesis we focused our attention to the high injection mecha-

nisms taking place during ESD events in single devices, by investigating diffused

resistors, substrate diodes, LDMOS transistors and ggnMOS transistors, in the static

domain as well as the dynamic domain. The research has been mainly carried out with

the help of numerical simulations because in the regime of interest it is possible to

derive analytical solutions to injection problems only in few and simplified cases. The

know-how acquired on these basic structures is fundamental to understand and predict

the behavior of more complex and effective protection networks.

The final goal is the generation of models that can be implemented in compact-

model simulators to provide reliable simulations prior to committing to silicon.

- 169 -Conclusions


8.II Conclusions

In diffused resistors have been analyzed under various conditions. It has

been shown that the complete characteristic can be split into four different

regions. In the first region, for low injection levels, Ohm's law holds. By increasing the

injection level, the behavior strongly depends on the n-well doping. For high resistive

structures, a space charge limited regime takes place already at low injection. For low

resistive structures space charge plays only a minor role. In both structures, the elec-

trons drift velocity reaches a saturation value and, as injection increases, the electric

field is more and more confined into a small region close to the anode. When the

threshold for the impact ionization is reached, the generated hole-electron pairs alter

the carrier's distribution in the structure until, after a maximum voltage (snapback

voltage), a current controlled NDR region takes place. In the NDR region the conduc-

tion moves from one-carrier current (electrons) to a two-carriers current. Through

transient electro-thermal simulation it has been possible to assess that when the lattice

temperature is such that the thermal generated carriers prevail over the avalanche

generated carriers, the current crowds into a small filament in which a positive feedback

(due to the positive thermal coefficient of the thermal generated carriers) the tempera-

ture is getting higher and higher, until a damage occurs.

In the applicability of the theory of P -N -N power rectifiers to substrate

diodes, structures virtually present in any ESD protection strategy, under high injection

conditions has been verified. Through numerical simulations and experimental verifi-

cations it has been possible to assess the suitability of the above-mentioned theory to

substrate diodes for applied voltages up to 1.6-1.7V. It has been shown how in such

structures the transport mechanism is mostly due to recombination. According to

whether the main contribution to recombination is in the middle region (where high

injection occurs) or in the end regions (where low injection level is still present), differ-

ent characteristics have been found.

In a study on P -N -N substrate diodes under ultra high injection condi-

tions has been presented. The problem has been tackled both from an experimental

point of view (through DC and pulsed analysis) and with the support of numerical

simulations. It turned out that the as soon as high injection takes place at the end

regions too (characterized by an excess of majority carriers) a new linear charac-

teristic is found. In this regime, the current is field driven in all the three regions of the

Chapter 3

I(V)

Chapter 4

J (V )

Chapter 5

J (V )

+ - +

+ - +

A A

A A

- 170 -Conclusions

Chapter 8

P -N -N substrate diode, which now behaves as a non-linear resistor. A fitting law that

matches the characteristic over a broad range of injection conditions has been

proposed and verified both on numerical results and on measured devices. Self-heating

effects as well as process and layout variations have been analyzed.

In the behavior under high reverse biasing condition of the LDMOS

transistors designed for medium voltage applications has been investigated. Through

measurements it has been possible to assess the unsuitability of these devices as single

ESD protection element in medium voltage pins application. Through 2D simulations

the causes for the shown weakness have been analyzed in detail. In particular, it has

been found that the breakdown of the N /P junction cannot be very “deep”

because the Kirk effect takes place as soon as the injected current becomes in the order

of the epitaxial region doping, which is normally low. Since the presence of this low

doped epitaxial region is a characteristic of all DMOS-like transistors, it follows that the

Kirk effect is “intrinsic” in this kind of structure. The Kirk effect is a current controlled

phenomenon that causes the relocation of the high field region from the avalanching

N /P junction to the N /N diffused junction, where the maximum power is

dissipated. Therefore, here is located the most likely failure site as it has been confirmed

by failure analysis.

In it has been shown, through simulations, how during the early phase of a

TLP like stress in a ggnMOSt it is possible to reach voltages even exceeding the trigger-

ing voltage V of the associated parasitic bipolar structures. Since the breakdown

voltage of the gate oxide, BV , during pulsed events is significantly larger than in DC

conditions, it is debatable whether these very fast overvoltages can cause damages. It

has been assessed that the charging of the overlap capacitance with holes displaced by

capacitative effect causes these overvoltages. This has also been confirmed by the

dependence of the maximum reached voltage on the rise-time of the applied pulse. It

has been found that in devices with LDD implant the maximum clamping voltage

reached during the transient is higher than that of analogous devices with standard

drain-source implant, which is due to the reduction of the overlap capacitance.

+ - +

-

- +

J (V )

Chapter 6

Chapter 7

A A

EPI

EPI EPI

T1

OX

Conclusions

Chapter 8 Recommendations for future research

8.III Recommendations for future research

One of the most important problems about ESD (if not the most) is the determi-

nation of the onset of the “second (thermal) breakdown”, after which an irreversible

change in the silicon takes place and the devices become definitely damaged. So far

many studies have been undertaken to determine the exact condition that leads to

thermal breakdown, but at the moment an analytical criterion related both to process

and design parameters is not available. Some more insights about this key-problem can

be earned by making use of the following methodology:

Focus the study on the easiest possible structures, like n-well resistors.

Manufacturing of samples with different layout/process parameters (well doping

and length, contacts geometry).

TLP characterization and failure analysis of the produced samples: possibility of

correlating the onset of damage with different layout/process parameters.

3-D simulations of the characteristics based of the on the 3-D simulation of

the doping profiles: determination and test of a process/layout-dependent criteria

for second breakdown. The 3D approach is indispensable mainly because the

phenomenon of filamentation has a typical cylindrical symmetry and because the

solution of the heat equation with a 2D thermal conductivity results in a consider-

able error compared with the 3D case in the evaluation of the temperature far from

the heat source. A further advantage in considering the third dimension consists in

the study of the influence of contacts geometry.

Derive a methodology for the extraction of compact model parameters in n-well

resistors including (cold) snapback and (thermal) second breakdown.

Application of the compact model to assess the effect of ballasting resistors in

ggnMOSt's.

�

�

�

�

�

�

I(V)

- 171 -Conclusions

- 173 -

Samenvatting

Elektrostatische ontlading (ESD = Electrostatic Discharge) is een veel

voorkomend verschijnsel in de natuur: als een statisch geladen materiaal in contact

wordt gebracht met een geaard object, zal het ladingsevenwicht hersteld worden door

ontlading van het geladen materiaal naar de aarde. In tegenstelling tot wat de naam van

het fenomeen suggereert, is de ontlading extreem snel, namelijk in de orde van een

tiental nanoseconden. Verder is een elektrostatische potentiaal (spanning) van enkele

kV en een ontladingsstroom die kan oplopen tot meerdere amperes niet ongewoon.

IC's zijn niet immuun voor ESD, omdat de hoge stroom (en uiteindelijk de hoge

spanning) onherstelbare schade aan de devices kan aanrichten. Er is vastgesteld, dat

ESD (samen met EOS - elektrische overbelasting - waarvan ESD een onderdeel is) de

oorzaak is van ongeveer 38% van de totale hoeveelheid field returns. Gegeven de grote

invloed van ESD op IC-betrouwbaarheid, is er een sterke behoefte aan ontwikkeling

van beschermingsstrategieën.

Er zijn twee manieren op dit probleem aan te pakken. De eerste manier is “extern”

en bestaat uit het minimaliseren van de potentiële risico's (neutraliseren van statische

lading door luchtionisatie, beschermende verpakking, geaarde polsbanden gedurende

het hanteren van de devices, enz.). De tweede manier om een IC tegen ESD ontlading

te beschermen is “intern” en bestaat uit het implementeren van een

beschermingsschakeling op de chip. Het ontwerp van een effectief

beschermingscircuit is een gecompliceerde taak, die enkele iteratieslagen nodig kan

hebben.

Gedurende een ESD ontlading worden de beschermingsstructuren gedwongen

om onder hoge injectiecondities te werken, waarbij in korte tijd een elektro-thermische

interactie plaatsvindt. In tegenstelling tot de vele studies die over dit onderwerp

beschikbaar zijn, is er nog steeds geen model van het gedrag van de circuits tot aan een

zeer hoog injectieniveau. Dit is de reden waarom wij ons in deze thesis focussen op de

hoge injectie mechanismen die in enkelvoudige devices plaatsvinden gedurende ESD-

ontladingen. Dit gebeurt door onderzoek aan, weerstanden op de chip,

substraatdiodes, LDMOS transistoren en ggnMOS transistoren, zowel in het statische-

als in het dynamische domein.

Het onderzoek heeft hoofdzakelijk plaatsgevonden met behulp van numerieke

simulaties, omdat in het interessegebied analytische oplossingen voor de

injectievraagstukken alleen in een beperkt aantal, vereenvoudigde gevallen mogelijk is.

De verkregen kennis van deze eenvoudige structuren vormt de basis voor het begrip en

- 174 -

de voorspe l l ing van het gedrag van complexere en ef fec t i eve

beschermingsschakelingen. Het uiteindelijke doel is het maken van modellen die in

compact-model simulators gebruikt kunnen worden om te voorzien in betrouwbare

simulaties voordat er aan implementatie in silicium begonnen wordt.

List of scientific publications

Award

�

�

�

�

�

�

�

�

�

Boselli, G., Mouthaan, A.J., and Kuper, F.G., “

”, in Proceedings of 6 ICSDT, ICSDT '98, pp. 141-144, October

14-16, 1998, Cape Town, South Africa.


”, in Proceedings of 1 IEEE-SAFE, SAFE '98, pp. 57-60, November

25-27, 1998, Mierlo, The Netherlands.


”, presented at 21 EOS/ESD

Symposium, September 27-30, 1999, Orlando, Florida, USA. Published in

EOS/ESD Symposium Proceedings 1999, IEEE Catalog No. 99TH8396, pg 11-

18.


”, in Proceedings of 2 IEEE-SAFE, SAFE '99, pp. 55-62,

November 24-26, 1999, Mierlo, The Netherlands.


”, in Proceedings of 22 IEEE-MIEL International Microelectronics

Reliability Conference, MIEL 2000, pp. 355-358, May 14-17, Nis, Yugoslavia.


”, in Journal of Microelectronics Reliability, vol.40, num.12, pp. 2061-2067,

December 2000.


”, to be published on Journal of

Microelectronics Reliability.

Boselli, G., Ramaswamy, S., Amerasekera, A., Mouthaan, T., and Kuper, F.,

“ ”, to be presented

at 23 EOS/ESD Symposium, September 9-13, 2001, Portland, Oregon, USA.

Best paper award (on behalf of Microelectronics Reliability Journal) at IEEE-

MIEL International Microelectronics Reliability Conference, Nis, Yugoslavia, May

2000.

Device simulation of ESD events in

protection structures

Dynamics of switching on ggMOSt in

HBM pulse

Investigations on Double-Diffused MOS

(DMOS) transistors under ESD zap conditions

Modeling DMOS Transistors under High

Injection conditions

Rise-time effects in ggnMOSt under TLP

stress

Rise-time effects in ggnMOSt under TLP

stress

Investigations on Double-Diffused MOS

(DMOS) transistors under ESD zap conditions

Modeling Substrate Diodes under Ultra High ESD Injection Conditions

th

st

st

nd

nd

rd

- 175 -

- 176 -

Acknowledgments

I am indebted to many people who have contributed, directly or indirectly, to the

realization of this thesis.

a, the dean of our faculty, for his courteous and efficient availability in

fixing all the matters related to the development of my thesis.

, my daily supervisor and assistant promoter, for succeeding in the diffi-

cult task to convince me to undertake a four years Ph.D. far away from my country.

Thanks Ton, no doubts anymore: it was the right choice.

, my promoter, for teaching me a new critical rigor that will be of great help

not only in scientific issues. Furthermore, thanks to his encouragements I could get in

touch with Texas Instruments world.

Many thanks also to the administrative staff of our group, ,

, , and , for working out their tasks

always with great precision and helpful smiles.

The computer experts, , and , for fixing with

punctuality all PC's, HP's and network's troubles.

, for the great patience he showed in bearing me as his virtual neighbor for

quite sometime.

and for the impeccable organization of the testing room

and their constant availability to solve any time any kind of problems.

, , and from Philips

Semiconductors Nijmegen, for giving me a fast start in the ESD world.

Three very special Friends without whom my stay in Holland would not have been the

same: , and . Above all, their absence will give me the feeling that

an experience is definitely over. and are also acknowledged for serving as

paranimfen at the dissertation ceremony.

Hans Walling

Ton Mouthaan

Fred Kuper

Marie-Christine Prédéry Margie

Rhemrev Mariska Buurman Sophie Kreulen Joke Vollenbroek

Cor Bakker Frederik Reenders Jan Hovius

Jisk Holleman

Henk de Vries Marcel Weusthof

Huug van der Vlist Stan Meeuwsen Marcel Hoeven Hans van Zwol

Rossano Vladimir Alberto

Alby Vlada

- 177 -

All the friends who time after time made this experience worth living: , ,

, , , , , , , and all those I am

unforgivably forgetting at the time of writing.

, more than a friend, the friend with whom I have shared three years of

sincere friendship.

All my pleasant roommates: , , , ,

and .

My splendid family, with a compulsory mention to my mother , who suffered a lot

from my continual absence. For this reason, this work is entirely dedicated to her.

, and from Texas Intruments Inc. Dallas,

for offering me a three months internship. The experience has been so extraordinarily

intense to convince me to come back for a longer period.

Last but not least, . She is the ideal link between the end of this thesis and my

adulthood.

Petra Federico

Milan Sara Arnaud Pietro Leonardo Franceschina Corrado l'Ammiraglio

Violeta Petrescu

Peter Stroet Alexey Kovalgin Jan Harm Nieland Natasa Tosic

Andreea Merticaru Liquan Fang

Afra

Tim Rost Ajith Amerasekera Sridhar Ramaswamy

Maria

- 178 -

Biography

Gianluca Boselli was born on February 12, 1967 in Busseto (Parma), Italy. From

1982 to 1987 he joined the High School of Mathematics and Physics “G.Ulivi”, Parma.

From 1988 to 1994 he completed his engineering studies at the Faculty of Electronic

Engineering, Department of Information Science, at the University of Parma. In the

1995 he spent six months within the framework of the Erasmus project in the IXL

Laboratory of Microelectronics, at the University of Bordeaux 1 (France) where he

worked towards his Master thesis dealing with reliability issues (specifically hot elec-

trons) in the III/V semiconductor compounds field. In 1996 he served the army.

In January 1997 he started his position as research fellow in the IC-technology,

Devices and Reliability (IDR) group at the University of Twente working towards his

Ph.D. degree. During this period he published several papers and he has been awarded

with the “Best Paper Award on behalf of Microelectronics Reliability Journal” at the

22 International Conference on Microelectronics, Nis, Yugoslavia, May 2000. In

February 2001 he joined the Logic Technology Development Group as reliability

engineer in Texas Instruments Inc., Dallas, Texas, USA. His results as Ph.D. student are

presented in this thesis.

nd

Documents

On High Injection Mechanisms in Semiconductor Devices under … · ON HIGH INJECTION MECHANISMS IN SEMICONDUCTOR DEVICES UNDER ESD CONDITIONS PROEFSCHRIFT ter verkrijging van de graad