October 10, 2000 1

October 10, 2000 2

USB 2.0 Compliance Program Overview

USB 2.0 Compliance Program Overview

Dan FroelichDan Froelich

IntelIntel

October 10, 2000 3

AgendaAgenda

USB-IF Compliance Testing HistoryUSB-IF Compliance Testing History Goals of the USB 2.0 Compliance ProgramGoals of the USB 2.0 Compliance Program USB 2.0 Differences from USB 1.1USB 2.0 Differences from USB 1.1 New/Modified Compliance TestsNew/Modified Compliance Tests

– ElectricalsElectricals– USBCheckUSBCheck– Transaction TranslatorTransaction Translator– System/PlatformSystem/Platform

High Speed Signal Quality Test DemonstrationHigh Speed Signal Quality Test Demonstration

October 10, 2000 4

HistoryHistory

USB-IF 1.1 Compliance ProgramUSB-IF 1.1 Compliance Program– Long evolution from 1996 (USB 1.0) to today (2000)Long evolution from 1996 (USB 1.0) to today (2000)

S3

Inrush

Signal Quality, S1

USBCheck, Hidview, Interoperability

Chap 11, OHCI, Current

Chap 9, UHCI, Drop/Droop

S3

Inrush

Signal Quality, S1

USBCheck, Hidview, Interoperability

Chap 11, OHCI, Current

Chap 9, UHCI, Drop/Droop

‘96‘96

YearYear

T e s ting

T e s ting

Level

Level

‘97‘97 ‘98‘98 ‘99‘99 ‘00‘00 ‘01‘01

October 10, 2000 5

Compliance Program EvolutionCompliance Program Evolution

The USB 2.0 Compliance Program is an extension The USB 2.0 Compliance Program is an extension of the USB 1.1 Compliance Programof the USB 1.1 Compliance Program– Years of experienceYears of experience– Tools already in placeTools already in place

USB 2.0 Compliance ProgramUSB 2.0 Compliance ProgramWill Start at a High Level!Will Start at a High Level!

USB 2.0 Compliance ProgramUSB 2.0 Compliance ProgramWill Start at a High Level!Will Start at a High Level!

TodayToday TomorrowTomorrow

USB2.0USB2.0

USB1.1USB1.1

October 10, 2000 6

Goals of theCompliance ProgramGoals of theCompliance Program

High Quality USB 2.0 ProductsHigh Quality USB 2.0 Products Stable, Repeatable, Well Documented TestsStable, Repeatable, Well Documented Tests

– Documented Test ProceduresDocumented Test Procedures– Documented Test Assertions and DescriptionsDocumented Test Assertions and Descriptions

Instantly Available Testing (Qualified Test Houses)Instantly Available Testing (Qualified Test Houses) Leverage USB 1.1 Compliance ProgramLeverage USB 1.1 Compliance Program

– Reuse USB CheckReuse USB Check– Reuse Interoperability Test ProceduresReuse Interoperability Test Procedures– Reuse Full and Low Speed Electrical TestingReuse Full and Low Speed Electrical Testing

Minimize Test Equipment CostsMinimize Test Equipment Costs

October 10, 2000 7

Compliance Program MilestonesCompliance Program Milestones

HS Testing Preview at October PlugFestHS Testing Preview at October PlugFest– HS Signal Quality and TDRHS Signal Quality and TDR– USBCheckUSBCheck– TT Functional TestingTT Functional Testing

Logo Testing AvailabilityLogo Testing Availability– Schedule Testing at Intel Peripheral Integration LabSchedule Testing at Intel Peripheral Integration Lab

Starting in NovemberStarting in November Contact Dan Froelich, daniel.s.froelich@intel.comContact Dan Froelich, daniel.s.froelich@intel.com

– Available at Plugfests in JanuaryAvailable at Plugfests in January– All Test HW and SW Available by Q3 2000All Test HW and SW Available by Q3 2000

October 10, 2000 8

USB 1.1 Testing Modifications and ReuseUSB 1.1 Testing Modifications and Reuse

Power MeasurementsPower Measurements USBCheckUSBCheck

– Chapter 9 AdditionsChapter 9 Additions– Chapter 11 AdditionsChapter 11 Additions

InteroperabilityInteroperability– HS Device and Hub AdditionsHS Device and Hub Additions

USB 1.1 Test FixturesUSB 1.1 Test Fixtures– Droop/DropDroop/Drop– InrushInrush– FS/LS Signal QualityFS/LS Signal Quality

October 10, 2000 9

USBCheck –Chapter 9 AdditionsUSBCheck –Chapter 9 Additions

Other Speed Device Qualifier andOther Speed Device Qualifier andConfiguration DescriptorsConfiguration Descriptors– HS/FS Devices Must Use In Either EnvironmentHS/FS Devices Must Use In Either Environment– Standard Configuration Descriptors OnlyStandard Configuration Descriptors Only

For Current EnvironmentFor Current Environment Endpoint Packet Size and Interval RulesEndpoint Packet Size and Interval Rules Electrical Test Mode SupportElectrical Test Mode Support HS Devices Tested At High and Full Speeds HS Devices Tested At High and Full Speeds

HS Capable Devices Must FunctionHS Capable Devices Must Functionin FS Environmentsin FS Environments

October 10, 2000 10

Compliance Tool USBCheckCompliance Tool USBCheck

October 10, 2000 11

USBCheck –Chapter 11 AdditionsUSBCheck –Chapter 11 Additions

TT RequestTT RequestCodesCodes

Port IndicatorsPort Indicators

New Status BitsNew Status Bits

Windows 2000 Version of USBCheck Available SoonWindows 2000 Version of USBCheck Available Soon

October 10, 2000 12

Interoperability TestingInteroperability Testing

Same Tree For HS/FS/LS Same Tree For HS/FS/LS TestingTesting

Similar To 1.1 InteropabilitySimilar To 1.1 Interopability– All Transfer TypesAll Transfer Types– 5 hubs deep with 5 meter 5 hubs deep with 5 meter

cables (i.e. Tier 6)cables (i.e. Tier 6)– Mix of speedsMix of speeds

Test devices at both FullTest devices at both Fulland High Speedsand High Speeds

RootRoot

HS HubHS Hub

DUTDUT

HS HubHS Hub

HS HubHS Hub

Other Devices

Other Devices

FS HubFS Hub HS HubHS Hub

HS HubHS Hub

October 10, 2000 13

Existing – Test FixturesExisting – Test Fixtures

CurrentCurrent

InrushInrush DropDrop

DroopDroop

Full/Low Speed Full/Low Speed Signal QualitySignal Quality

October 10, 2000 14

What Changed For USB 2.0What Changed For USB 2.0

HS Electrical Signaling and Electrical Test ModesHS Electrical Signaling and Electrical Test Modes– Defined Receiver CharacteristicsDefined Receiver Characteristics– Repeatable Signal Quality TestingRepeatable Signal Quality Testing

Hub Transaction Translator for FS/LS SupportHub Transaction Translator for FS/LS Support Other Speed Device DescriptorsOther Speed Device Descriptors

Model Largely UnchangedModel Largely Unchanged– Device FrameworkDevice Framework– Power Management and DistributionPower Management and Distribution– Cables, Connectors, and TopologyCables, Connectors, and Topology

October 10, 2000 15

New Testing AreasNew Testing Areas

ElectricalsElectricals– High Speed Signal QualityHigh Speed Signal Quality– Time Domain Reflectometry (TDR)Time Domain Reflectometry (TDR)– Receiver Sensitivity and SquelchReceiver Sensitivity and Squelch

Platform TestingPlatform Testing– ElectricalsElectricals– Port RoutingPort Routing

More Extensive Hub TestingMore Extensive Hub Testing– High Speed RepeaterHigh Speed Repeater– Transaction TranslatorTransaction Translator

October 10, 2000 16

USB 2.0 ElectricalTest ModesUSB 2.0 ElectricalTest Modes

High-speed Capable Devices/Hubs Must Support High-speed Capable Devices/Hubs Must Support Test Modes Test Modes

Test modes Enable Repeatable TestingTest modes Enable Repeatable Testing SetFeature(TEST_MODE) and SetFeature(TEST_MODE) and

SetPortFeature(PORT_TEST) Requests Provide SetPortFeature(PORT_TEST) Requests Provide Standard Means of Entering ModeStandard Means of Entering Mode

Exit Action is also StandardizedExit Action is also Standardized– Upstream Facing Port – Power CycleUpstream Facing Port – Power Cycle– Downstream Facing Port – Hub ResetDownstream Facing Port – Hub Reset

October 10, 2000 17

Test PointsTest Points

TransmitterTransmitter Receiver (New)Receiver (New)

USB CableUSB Cable

Device Circuit BoardDevice Circuit Board Hub / MotherboardHub / Motherboard

BBConnectorConnector

AAConnectorConnector

TracesTraces TracesTraces

TransceiverTransceiver TransceiverTransceiver

TP4TP4 TP3TP3 TP2TP2 TP1TP1

October 10, 2000 18Usb 2.0 Test FixtureUsb 2.0 Test Fixture

HS RelayHS RelayHS RelayHS RelayTest PortTest Port

InitializationInitializationPortPort

Diff ProbeDiff ProbeDataDataGeneratorGenerator

90 Ohms90 Ohms

PowerPowerSelectionSelection

CktCkt

PowerPowerSelectionSelection

CktCkt

Vbus1Vbus1 Vbus2Vbus2VccVcc

GndGnd

New Test FixturesNew Test Fixtures

Device and Host TestsDevice and Host Tests– Signal QualitySignal Quality– TDRTDR– Receiver SensitivityReceiver Sensitivity– ChirpChirp– J and K LevelsJ and K Levels

October 10, 2000 19

High Speed Signal QualityHigh Speed Signal Quality

USB 2.0 Spec Defines Required Eye Patterns USB 2.0 Spec Defines Required Eye Patterns – 6 Patterns6 Patterns

4 correspond to external connectors (TP2 & TP3)4 correspond to external connectors (TP2 & TP3) 2 correspond to internal connectors (TP1 & TP4)2 correspond to internal connectors (TP1 & TP4)

– Rise / Fall TimesRise / Fall Times– Allowance for JitterAllowance for Jitter– Overshoot / UndershootOvershoot / Undershoot

Testing at External ConnectorsTesting at External Connectors– New Test Fixture for HS Signal Quality Available SoonNew Test Fixture for HS Signal Quality Available Soon

October 10, 2000 20

HS Signal QualityTest ProcedureHS Signal QualityTest Procedure

Put Device in Test Put Device in Test Mode Test_PacketMode Test_Packet

Flip Test Fixture Flip Test Fixture Relays To Route Relays To Route Output to 90 Ohm Output to 90 Ohm TerminationTermination

Capture WaveformCapture Waveform Analyze DataAnalyze Data

9090

Test Mode SW

OscilloscopeOscilloscope

USB 2.0 Test FixtureUSB 2.0 Test Fixture

HS RelayHS RelayHS RelayHS Relay

Differential ProbeDifferential Probe

DeviceDeviceUnderUnder TestTest

October 10, 2000 21

HS Receiver Sensitivity and Squelch Test ProcedureHS Receiver Sensitivity and Squelch Test Procedure

DUT Placed In DUT Placed In Test_SEO_NAK ModeTest_SEO_NAK Mode

Data Generator Data Generator Generates IN PacketsGenerates IN Packets

Device Must Respond Device Must Respond For In Spec PacketsFor In Spec Packets

Device Must Not Device Must Not Respond to Out of Respond to Out of Spec Data Generator Spec Data Generator OutputOutput

Data GeneratorData GeneratorTest ModeTest Mode

SWSW

USB 2.0 Test FixtureUSB 2.0 Test Fixture

HS RelayHS RelayHS RelayHS Relay

DeviceDeviceUnderUnder TestTest

DeviceDeviceUnderUnder TestTest

SMASMA

October 10, 2000 22

Time DomainReflectometer (TDR)Time DomainReflectometer (TDR)

Means of Measuring a Receiver’s ImpedanceMeans of Measuring a Receiver’s Impedance– Receiver idle: D+, D- both at 0 volts (Test Mode Receiver idle: D+, D- both at 0 volts (Test Mode

SE0_NAK)SE0_NAK) Requires NewRequires New

Test FixtureTest Fixture

To be run onTo be run onAll Devices,All Devices,Hubs, and Hubs, and PlatformsPlatforms 0.00E+00 2.00E-09 4.00E-09 6.00E-09 8.00E-09 1.00E-08 1.20E-08

time

impedance

Connector Connector ReferenceReference

TimeTime

October 10, 2000 23

TDR Test ProcedureTDR Test Procedure

Device Under Test Placed Device Under Test Placed In Test_SEO_NAK ModeIn Test_SEO_NAK Mode

Relay Switches Idle Data Relay Switches Idle Data Lines to TDR Lines to TDR

TDR Broadcasts Test TDR Broadcasts Test SignalSignal

TDR MeasuresTDR MeasuresSignal Reflections ToSignal Reflections ToDetermine Termination Determine Termination And PCB ImpedanceAnd PCB Impedance

TDRTDR

Test ModeTest Mode SWSW

USB 2.0 USB 2.0 Test FixtureTest Fixture

HS RelayHS RelayHS RelayHS Relay

DeviceDeviceUnderUnder TestTest

DeviceDeviceUnderUnder TestTest

SMASMA

October 10, 2000 24

Host turns onHS termination

Reset

CHIRP Test ProcedureCHIRP Test Procedure

CHIRP TestingCHIRP Testing– Measured with single ended probesMeasured with single ended probes– At the A-connector (TP2)At the A-connector (TP2)

Important ParametersImportant Parameters– Reset durationReset duration– CHIRP K amplitudeCHIRP K amplitude– CHIRP K durationCHIRP K duration– HS termination timingHS termination timing– Host CHIRP amplitudeHost CHIRP amplitude

October 10, 2000 25

Platform TestingPlatform Testing

Eye Pattern Testing at TP2Eye Pattern Testing at TP2– Template 1 (Transmit)Template 1 (Transmit)– Template 4 (Receive)Template 4 (Receive)

TDR Testing TDR Testing Port RoutingPort Routing

MotherboardMotherboard

A ConnectorA Connector

TransceiverTransceiver

TP2TP2

TP1TP1

PC PlatformPC Platform

TracesTraces

Platform Design Guide Available on USB.ORGPlatform Design Guide Available on USB.ORGAttend Platform Design Considerations PresentationAttend Platform Design Considerations Presentation

October 10, 2000 26

Port Routing Logic Port Routing Logic

Ensure HS, FS, and LS Devices Recognized CorrectlyEnsure HS, FS, and LS Devices Recognized Correctly

Companion Companion USB 1.1 HCUSB 1.1 HCXX

Companion Companion USB 1.1 HCUSB 1.1 HCXX

Port RegisterPort RegisterPort RegisterPort Register

High Speed HCHigh Speed HCHigh Speed HCHigh Speed HC

TransceiverTransceiverTransceiverTransceiver

Port Routing LogicPort Routing LogicPort Routing LogicPort Routing LogicPort Owner ControlPort Owner ControlPort Owner ControlPort Owner Control

HC HC ConfiguredConfigured

HC HC ConfiguredConfigured

Port RegisterPort RegisterPort RegisterPort Register

HSHS DeviceDevice

LS LS DeviceDevice

FS FS DeviceDevice

October 10, 2000 27

Extensive Hub TestingExtensive Hub Testing

Signal Quality – Eye PatternsSignal Quality – Eye Patterns– At TP3 (downstream) in addition to TP2 (upstream) At TP3 (downstream) in addition to TP2 (upstream) – Both Transmitting (Template 1) and ReceivingBoth Transmitting (Template 1) and Receiving

(Template 4)(Template 4) Hub Specific CommandsHub Specific Commands

– Port Test ModesPort Test Modes TDR TestingTDR Testing

– All connectors (upstream B, downstream A)All connectors (upstream B, downstream A) Transaction TranslatorTransaction Translator Electrical HS Repeater TestingElectrical HS Repeater Testing

October 10, 2000 28

Transaction TranslatorTransaction Translator

What is a Transaction Translator?What is a Transaction Translator?– Component of the hub that handles data transfers Component of the hub that handles data transfers

to/from full and low speed downstream devicesto/from full and low speed downstream devices When is it Used?When is it Used?

– Active when hub is configured at Active when hub is configured at high speedhigh speed and and fullfull and/or and/or low speedlow speed devices connected downstream devices connected downstream Buffers data transfersBuffers data transfers Finite spaceFinite space 2 kind of Buffers - Periodic and Non-Periodic2 kind of Buffers - Periodic and Non-Periodic 1 TT per hub OR 1 TT per port1 TT per hub OR 1 TT per port

October 10, 2000 29

Transaction TranslatorTransaction Translator Hub Components Hub Components

HSHS DeviceDevice

LS LS DeviceDevice

Port 1Port 1

480 MHz480 MHz12 MHz12 MHz1.5 MHz1.5 MHz

Port 2Port 2 Port NPort N

FS FS DeviceDevice

Hub Hub RepeaterRepeater

Hub Hub RepeaterRepeater

RoutingLogic

Hub Hub ControllerController

Hub Hub ControllerController

Hub StateHub StateMachinesMachines Hub StateHub StateMachinesMachines

High speed connectionHigh speed connection

TTTT11TTTT11

TTTT22TTTT22

TTTTNNTTTTNN

October 10, 2000 30

Transaction Translator TestingTransaction Translator Testing

Devices & Hubs of Mixed Speeds Below Hub Devices & Hubs of Mixed Speeds Below Hub – Rigorous Functional Tests With FS/LS DevicesRigorous Functional Tests With FS/LS Devices

Proper Enumeration of DevicesProper Enumeration of Devices Perform LoopBacks (All Transfer Types)Perform LoopBacks (All Transfer Types)

Stress Periodic and Non-Periodic Buffers (Multiple Endpoints)Stress Periodic and Non-Periodic Buffers (Multiple Endpoints) Check for Isochrony Hiccups Check for Isochrony Hiccups Data IntegrityData Integrity

– Specific Test Cases For Possible Device BehaviorsSpecific Test Cases For Possible Device Behaviors Timeout, Stall, Protocol Violations, ETCTimeout, Stall, Protocol Violations, ETC

Separate Hub Testing Presentation with TT FocusSeparate Hub Testing Presentation with TT Focus

October 10, 2000 31

Oscilloscope RequirementsOscilloscope Requirements

List of Required Scope / Probe Capabilities List of Required Scope / Probe Capabilities – 5 G Samples/sec (Per Channel)5 G Samples/sec (Per Channel)– 2 GHz bandwidth2 GHz bandwidth– Accuracy RequirementsAccuracy Requirements

Tested Scopes and ProbesTested Scopes and Probes– Scope: TDS 694C – 10 GS/s, 3 GHzScope: TDS 694C – 10 GS/s, 3 GHz– Probe: P6217 Fet probe – 4 GHz, 0.4 pf typProbe: P6217 Fet probe – 4 GHz, 0.4 pf typ– More Scopes and Probes to be addedMore Scopes and Probes to be added

October 10, 2000 32

ConclusionsConclusions

Two significant Additions for USB2.0 ComplianceTwo significant Additions for USB2.0 Compliance– Electrical TestingElectrical Testing

HS Signal QualityHS Signal Quality TDRTDR Receiver SensitivityReceiver Sensitivity SquelchSquelch

– Transaction Translator TestingTransaction Translator Testing Well Documented TestsWell Documented Tests

– Test ProceduresTest Procedures– Test SpecificationsTest Specifications

October 10, 2000 33

DemoDemo

High Speed Signal QualityHigh Speed Signal Quality

Using Using Test Mode Test_PacketTest Mode Test_Packet

October 10, 2000 34

Questions?Questions?