OCT. 27. 2011 - · PDF fileOCT. 27. 2011 Sung-ki Park Hynix semiconductor Inc. •Prospects of Memory Market ... Challenges in DRAM Cell Transistor Cell Area [um2] Technology

OCT. 27. 2011
Sung-ki ParkHynix semiconductor Inc.

Prospects of Memory Market
DRAM/NAND Technologies- DRAM hurdles- NAND hurdles- Alternatives of DRAM/NAND. TSV, 3D stacking etc
New Memory Technologies- Future Memory Concept- PCRAM- ReRAM- STT-RAM
Summary- New Memory positioning
Outline

Sustainable Growth of Memory Market
1st Digital Revolution 2nd Digital Revolution
PC Mobile device
* Source : Gartner 4Q10, Hynix Estimate
Introduction of PC & Internet
Spread of Internet &Increase of PC demand
Mobile & Smart
12
55
25
61
70
45
Memory Usage100
($B)
80
60
40
20
55
1990 1994 1998 2002 2006 2010 2014 2018
Memory Market

6563 63
69
76
4.6%3.8% 4.2%
7.8%7.2%
-3% -3%
0%
9.5%10%
50
55
60
65
70
75
80
-6
-3
0
3
6
9
12
2011 2012 2013 2014 2015
Memory Market(B$) Semiconductor(CAGR) Memory(CAGR)
Prospects of Memory Market (~15)
* Source : isuppli, etnews
CAGR (%) Market(B$)
11 DRAM growth : -15% (because of excessive supply)

Memory Development History (1)
* Source : Gartner & Intel
No. of Tr. / Die
1995 2000 2005 20101985 1990
8G
2G4G
16G
1G
512M
32G
64G
Year
256K1M
16M
64M
4M
128M256M
512M1G
2G
4G
DDR1 200 ~ 400Mbps
DDR2400 ~ 800Mbps
DDR30.8 ~ 1.6Gbps
SDRAM~ 133Mbps
EDO50Mbps

2010 2011 2012 20132007 2008 2009
Year2014 2015 2016
1.8[V]
1.5
1.35
1.21.1
1.0x[V]
POWER
0.8
1.5Gbps
1.8
2.2
3.2GbpsSPEED
DENSITY
32
64GB
16
8GB
* Source : Gartner
Memory Development History (2)

DRAM Scaling & ASP Trend
[Source : WSTS ]
3Xnm
2011
Bit growth should be more than 50% for each technology generation.
Minimum Feature Size [nm]
[Year]
20
30
40
50
60
708090
200
* Source : ITRS

Outline

Cost
Density
Net die
Performance
Time toMarket
PowerConsumption

10nm
20nm
30nm
40nm
50nm
2008 2009 2010 2011 2012 2013 2014 2015
DRAM
NAND
Need to overcome the Technical Hurdles
New Memory : PCRAM, STT-RAM, ReRAM
High Cell Efficiency & Stacking : Multi Bit, TSV
Cell structure : 4F2, 3D Cell
New Material/Process : High-k, Patterning
Hurdles
* Source : Hynix

Challenges in DRAM Cell Transistor
Cell Area[um2]
Technology node
25%
33%
0.02
0.03
0.01
PlanarRCAT S-Fin
BWL
Pillar Gate
100nm 80nm 60nm 40nm 20nm
Floating Body Effect
Retention Degradation
Scalability
4F2 Pillar Gate
8F2
6F2
4F2
* Source : Hynix
DRAM Hurdles

Floating Body Effect- Technology Scale Down
Pillar Leaning after BBL etch- Due to high A/R & Film stress
BBL to WL Short & LPC to WL Short- No process margin
BBL Rs High - Use implant junction BBL
Technological Challenges of 4F2 Cell and Vertical Gate
SN
A
A'
WL
Tech shrink
Pillar
Well
A
A'
BBL
DRAM Hurdles

Challenges in DRAM Cell Capacitor
b
H
Aspect Ratio(A/R)of SN=H/b
70 2060 50 40 300
20
40
60
80
100
Tech node (nm)
Asp
ect R
atio
of S
tora
ge N
ode
9
8
7
5
11
* Source : S.J. Hong (Hynix), IEDM 2010
~3
DRAM Hurdles

Tech Node [nm]30 25 2x 1x
ZAZ (Tox~7) Ultra high-k, to be developed (Tox

History of NAND Technology Development
0.01
0.1
1
10
100
2004 2006 2008 2010 2012 2014
Chip
Are
a p
er
Gb [
mm
2]
64Gb32Gb
16Gb
9xnm
ISO / Gate / BL
SOD / CoSix / Cu
HDP / WSix / W
7xnm 6xnm 5xnm 4xnm 3xnm 2xnm 1xnm
* Index :
* Source : hynix
128Gb
256Gb
NAND Hurdles

Vpass Vpgm Vpass
Charge Loss
WL LKG
e
e
e
WL to WL leakage Cell to cell interference
Challenge of FG NAND (1)NAND Hurdles

Electron number decrease
160electrons in 1Xnm,We have to manage 16 electrons.
IPD LKG High
Cell Vt
IPD LKG Low
PGM Bias
e
e
ee
e
e
Thin IPD also results in bad Retention. Scaling limit ~ 100
IPD Scaling
Challenge of FG NAND (2)NAND Hurdles

p-BiCS (Toshiba) TCAT (Samsung) 3D FG (Hynix) VG-NAND
Structure
R. Katsumata, SOVT2009 J. Jang, SOVT2009 S. Whang, IEDM2010 W. Kim, SOVT2009
Key
Features
- Gate first
- GAA structure
- P+ SONOS Cell
- Gate-last
- GAA structure
- TANOS Cell
- Gate first
- GAA structure
- Floating Gate
- Gate-last
- Double Gate
- TANOS Cell
Key Issue- Large Cell Size
- Reliability
- Large Cell Size
- SL Resistance
- Process of bit
separation
- Disturbance
- BL address
coding
- Retention
3D NANDs encounter new challenges, which had never met before.
Challenge of 3D NAND NAND Hurdles

* Source: Lam Research
3D DRAM TSV
3D IC technology will be used for boosting both DRAMpackaging densities and performances
Alternatives of DRAM/NAND

Cost Comparison [DDP vs. TSV]
DDP TSV
FAB
Assy
FAB
AssyTest
Test
4%
100%
60%
22% Dual Die Package
Through Silicon Via
TSV Cost 22% higher than DDP

3D DRAM - Wafer Stacking
Metal bonding Issue
Low Thermal Budget Process
Floating Body Effect
Acceptor Wafer
1st Donor Wafer
2nd Donor Wafer
S/A, SWD & Peri.
Memory
Memory

Outline

Future Memory Concept [Capacitor Resistor]
B/L
1T1CDRAM
Voltage Sensing
WL
Substrate
WL
Capacito
r
Bit Line
Capacito
r
1T(D)1RPCRAM
STT-RAMReRAM
B/L
Current Sensing
WL
Substrate
WL
Bit Line
Source
Lin
e
R R

PCRAM Cell Operation
BE (Heater)
PCM
Amorphous Crystalline
BE (Heater)
Programming[Write]
State 1[SET] State 0[RESET]
State 1 State 0
Phase Change Material
Current Sensing
PCRAM

4F2 based Cell Integration
MLC: Cell & Driver Technology
. . . . . .
n th cell layer
1st cell layer
. . . . . .
. . . . . .
. . . . . .
. . . . . . . . . . .
GST
TE
BE
I_reset reduction
I_disturbance
-Confined type )
BECGST
TE & B/L
W
W
Cu
Al
WL
BL
WL
diode
SilicideBE
GST
TE
2F2F
Cross-point based diode scheme on metal W/L
Confined type based Cell to Cell Isolation Smart PNV, S/A resolution, Drift Control
GeSbTe friendly thermal process, high Ion/Ioff, Core to cell interconnection
2X = n states
ref_1 ref_2 ref_n
1st 2nd n-1 th n th
ref_n-1
Access device element
Storage cell element
. . .
MLS (Stackable Access Device)
Cell Scaling: Physical & Electrical
PCRAM Technical ChallengesPCRAM

Year /
Density~ 2008 2009 2010 2011 2012 2013 > 2014
> 4Gb
(4Gb ~
128Gb)
1Gb
< 512Mb
Min. feature size
NOR
90nm
54nm
45nmNOR and/or LPDDR2 NVM
2xnm
1xnmHighly Scalable & Cost Effective ?
DRAM-like and/or Storage-like
Development status and Challenges
Planar T-Cell(Ring-type Heater)
Planar T-Cell(Pillar-type Heater)
Partially Confined Cell(Pore-type)
Fully Confined Cell(Pillar type)
Fully Confined Cell(Ring type)
42nm
65nm
* Source : hynix
PCRAM

ReRAM - Device Operation
Binary oxide (NiO, TiO2, CuOx, etc)
Diode as access device
: Simple structure, Cost effective
Compliance current problem
Cr:SrZrO3, Pr0.7Ca0.3MnO3, etc.
Tr as access device
Stable switching characteristics
RESET
SET
LRS

Documents

OCT. 27. 2011 - · PDF fileOCT. 27. 2011 Sung-ki Park Hynix semiconductor Inc. •Prospects of Memory Market ... Challenges in DRAM Cell Transistor Cell Area [um2] Technology