NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT

NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT

James Dekker,

ack. Jaakko Saarilahti, Jyrki Kiihimäki, Hannu Kattelus

VTT TECHNICAL RESEARCH CENTRE OF FINLAND

OUTLINE

• Introduction• Ultrasonic transducers from polysilicon

• The Plug-Up process• SOI Resonators

• variations• Amorphous metals


INTRODUCTION

• Different micromachining technologies:• Surface Micromachining

• polysilicon and metal layers• oxide as sacrificial layer• Example:Acoustic emission sensor

• Bulk Micromachining• anisotropic etching (TMAH)

• SOI-based Micromachining• ICP etching• Buried oxide sacrificial layer• Example :Resonators

Both surface and SOI processes benefit from a novel release etch procedure

used at VTT


CAPACITIVE MICROMACHINED ULTRASONIC TRANSUCER (CMUT)

• A device for detecting ultrasonic pressure waves (6 to 13 MHz)

• NDT and ultrasonic imaging

• Surface micromachined using polysilicon

• Fully functional 500 element CMUT matrix has been demonstrated (1 mm2)

• A Novel method for etching of the sacrificial layer has been used.


CMUT PROCESS

• Process begins with LTO+poly + 600 nm TEOS depositions

• Deposition and patterning of nitride

5. Silicon nitride deposition 200 nm

6. Silicon nitride patterning

8. Cavity etching and sublimation

Silicon oxide

Polysilicon

Silicon nitride

Polysilicon

Al -metal

7. Polysilicon deposition

9. Polysilicon deposition 300 nm

13. Al –metallization patterning

• Deposition of porous poly-Si

• Cavity formed by HF etch and SC drying, then sealed with poly Si

• More depositions and patterning to get final structure

BEGIN

END


RELEASE ETCHING OF THE CMUT MEMBRANE

Silicon oxide

Polysilicon

Silicon nitride

Polysilicon

Al -metal

Removing the sacrificial oxide with HF

D = 40 - 60 um


CHARACTERIZATION OF RESONANCE

• Q= 100

• PULL-IN VOLTAGE ~40-200 V

Resonance frequencyC15 Gap = 600 nm

5.00E+06

7.00E+06

9.00E+06

1.10E+07

1.30E+07

1.50E+07

400000 500000 600000 700000 800000

Effective mass 1/SQRT(m)

Freq

uenc

y [H

z]

A -type

D -type

E -type

Resonance C_15_A3Osc Level=1 V pp DC Bias = 40 V

0.00E+00

4.00E+02

8.00E+02

1.20E+03

1.60E+03

2.00E+03

6.50E+06 7.00E+06 7.50E+06 8.00E+06 8.50E+06

Frequency [Hz]

Impe

danc

e [O

]

-100.00

-80.00

-60.00

-40.00

-20.00

0.00


LAME AND BAW RESONATORS from SOI

• Resonators for RF applications require high Q values with low power consumption.

• Low phase noise (Quartz resonators are ~-150 dBc/Hz)

• Bulk acoustic mode offers excellent characteristics compared to flexural mode

• 12 MHz BAW

• 13 MHz Lame

• gap=1 um (mask) by ICP

BAW

~400 um

LAMÉ


RESONATOR PROCESSING

• All MEMS processing is CMOS compatible

• 5-10 um SOI, 1 um BOX• pattern metal• ICP etch resonator and gaps• HF release etch• Supercritical drying

• Non-IC processing (esp. metals) done at back-end

frequency type Q (vacuum)1.6 MHz bridge (c-c) 3000014 MHz bridge (c-c) 1500111 kHz Cantilever 300012 MHz BAM 2x105


CHARACTERIZATION

• Measurement of S-parameters and resonance frequencies

• Phase noise (-115 dBc/Hz at 1 kHz offset)

11.7479 11.7480 11.7481 11.7482 11.7483-6

-4

-2

0

2

4

611.7 MHz BAW

S21

(dB

)

f (MHz)

13.0952 13.0953 13.0954 13.0955 13.0956-6

-4

-2

0

2

4

613.1 MHz Lame

S21

(dB

)

f (MHz)

11.7479 11.7480 11.7481 11.7482 11.7483

0.5

1.0

1.5

2.0

2.5

3.0

x (n

m)

f (MHz)

Q=180 000 Q>100 000

100 Hz


ALTERNATIVE SOI-PROCESS FOR RELEASING LARGE STRUCTURES

Nitride

Poly-Si

ThinPoly-Si

• Gaps and release holes by ICP etching• Structure released by HF etch followed

by SC drying• suitable for small or rigid structures

Pattern and etch release holes, strip, line with poly

Fill with poly, etchback, repattern,etch gaps to release structure

Etch cavity in HF and SC Dry

Better yield for large structuresNo holes in structure

Conventional process

Plug-Up process


MEMS, Amorphous Metals, and IC integration

MEMS first?

Topography!

Complexity!

IC first?

Metallurgy!


Reactive co-Sputtering of Mo-Si-N

SiMo

Wafers

Shutter TargetAr N2

DC

Mo Si

Si3N4

N

-Mo-N

MoSi2Mo5Si3Mo3Si

Mo2N

MoN AC

B

C:Mo34Si20N41 (O5)5.3 g/cm3

0.75 mcm

B:Mo19Si26N49 (O6)4.2 g/cm3

4.8 mcm


Thermal Stability

20 40 60 80 100 120 140 160 180 2000

20

40

60

80

Sh

eet

Res

ista

nce

()

Temperature (oC)

1100

1000900

500600700

RT

1000C / 1min in Ar

Dark-Field

as-deposited

200 nm Mo-Si-N layers

Conductive MoN or MoSi precipitates ?

800


Microelectromechanical test device: variable capacitor

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 2 4 6 8 10 12 14 16 18 20

Voltage (V)Ca

paci

tanc

e (p

F)

PhotoresistO+

O+O+

O+ O+

• Sputter MoSiN onto resist

• Dice

• O2 plasma “release etch”


Conclusions

- Amorphous metallic alloys are interesting alternatives for silicon in fabricating

MEMS devices

- Polymeric materials can be used for sacrificial layers

- Stress is more uniform and controllable than for polycrystalline metals

- Mo-Si-N is an IC-compatible material candidate

- Low deposition temperature (down to room temperature)

- High thermal stability


Summary

- Surface and SOI-based micromachining are dominant processes at VTT

- New release technology facilitates the fabrication of complex structures

- Amorphous metallic alloys are interesting alternatives for silicon in

fabricating MEMS devices

Documents

NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT