Indian Journal of Pure & Applied Physics Vol. 43, April 2005, pp. 301-307

Novel power VDMOSFET structure with vertical floating islands and trench gate

Rakesh Vaid & Naresh Padha Department of Physics & Electronics, University of Jammu, Jammu 180 006

Received 10 September 2004; revised 2 December 2004; accepted 15 February 2005

A novel power VDMOSFET (vertical double-diffused MOSFET) structure, simulated using PISCES-II, a 2-dimensional numerical device simulator has been described. The proposed device structure is based on the floating islands (FLI)-diode concept and trench gate technology. Extensive simulations were performed to understand physics of the device through various internal electrical quantities like potential distribution, electric field, etc. in different regions of the device both in on/off states.The simulation results show that the new device has a low on-resistance by virtue of reduced electric field in its drift region as well as due to the removal of parasitic JFET region resistance. Trench gate acts as a field plate to avoid the punch-through thus enhancing the breakdown voltage. For a 100 Volts design, an approximate 15% increase in the breakdown voltage has been observed in the proposed device compared to the conventional FLIMOSFET without trench gate.

Keywords: Power MOSFET, VDMOSFET, FLIMOSFET, Device simulation

IPC Code: H01J 1/00

1 Introduction

Power VDMOSFET (vertical double-diffused MOSFET) is mainly used as a switch in power electronics circuits, in which the specific on-resistance Ron (in the on-state) and breakdown voltage VB (in the off-state) are the two most important design parameters. Ideally the device should have minimum Ron and should sustain high breakdown voltage VB. For a higher VB, power MOSFETs are usually fabricated as a double-diffused structure with a lightly doped drift region to support the higher voltages. It increases the current densities by providing vertical current flow lines1,2.

The breakdown voltage VB can be increased by reducing the doping concentration and increasing the thickness of the drift region. However, this increases RON which is shown to be proportional1 to VB

2,5. Therefore, increasing VB can result in an increased RON, causing higher conduction losses in the on state. Many power MOSFET configurations have been reported in the literature to reduce RON such as Trench power3-6 MOSFET, super junction devices7,8, COOLMOSTM Refs (9-11) transistor, etc, and reduction in the RON has so far studied in terms of

optimum doping density, thickness and doping profile of the drift region.

Therefore, some structural changes in the VDMOSFET design are required so as to reduce its RON and simultaneously increasing the breakdown voltage VB. In this paper, a novel power VDMOSFET structure is proposed with vertical P+ floating islands and trench gate. The proposed device structure is based on the FLI diode concept12, high voltage sustaining structure with buried oppositely doped regions13-14 and trench gate technology3-6. The new device structure is designed using a two-dimensional advanced numerical device simulator15 PISCES-II. The device is studied both under on/off states and results were compared with the conventional VDMOSFET structure first by adding up to three P+ floating islands in the drift region one by one and then a trench gate. It will be shown that there is a reduction in maximum electric field in its drift region and breakdown voltage VB is enhanced about 15% for a 100 V device. Thus, making the device very attractive for high power electronic circuits. 2 FLI-Diode Concept and On-Resistance Reduction Mechanism

It is based on the concept that the triangular electric field distribution in the bulk is divided into several

_______________ E-mail: rakeshvaid@yahoo.co.in, Fax No. +91-191-2453079

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sections to decrease the magnitude of the peak electric field by inserting electrically vertical floating P+ buried layer in the N- drift region16 as indicated in Fig. 1. Thus, the doping of the drift region can be enhanced as long as the electric field is below its critical value (e.g. for silicon, breakdown electric field ~ 3×105 V/cm) thereby reducing the RON of the device. For an n-channel device, ideal specific on-resistance is given by:

TON, sp

n D

=qμ

WRN

… (1)

where WT is the width of the drift region conduction and μn is the bulk electron mobility.

The doping concentration of the epitaxial drift region affects the on-resistance of the device. The heavier the doping concentration, the smaller the on-resistance becomes. Smaller on-resistance is favoured for many applications; however, the breakdown voltage is sacrificed. The on-resistance reduction mechanism can also be explained in the following manner. In the conventional power VDMOSFET is as shown in Fig. 1(a), the N- drift region is required to be lightly doped so that the depletion region sufficiently develops into this area to sustain higher blocking voltage. The lightly doped N- drift region results in higher value of the resistivity. Whereas in FLIMOST structure in Fig. 1(b), the P+ floating layer increases the development of depletion layer due to a mechanism similar to the P-guard rings in planar terminations, i.e. once the source side reaches the P+

floating layer, the voltage of this layer is lowered due to the punch-through between the P+ floating layer and the P-base region, then a new depletion layer develops from the bottom of the P+ floating layer towards the drain. With this mechanism, the doping concentration of the N- drift region can be enhanced and hence the on-resistance can be reduced by a factor equivalent to the enhancement in doping of the drift region.

Thus, the drift region is divided into two sections, named upper and lower drift regions, by the insertion of the floating island. As the reverse bias is increased, the space charge region extends from the P-base region towards the floating island in the upper drift region. When this upper drift region is entirely depleted, then the space charge starts to extend from the bottom of the floating island towards the drain of the FLIMOST in the lower drift region. Thus, two electric field distributions, each of triangular shape are formed at both upper and lower drift regions, as shown in Fig. 1(c). In contrast, a single electric field distribution is formed in case of conventional power VDMOSFET structure [Fig. 1(c)]. Therefore, a number of consecutive vertical floating islands can be used to satisfy the desired device performance with designing the peak electric field in the FLIMOST kept below the critical electric field.

The most appropriate way to model the conduction of the device is through the total on-resistance of the device. The on-resistance of a conventional power VDMOSFET is a series combination of several resistances between the source and drain terminals when the device is turned on. The on-resistance determines the maximum current rating of the device.

Fig. 1—Figure explaining FLI-diode concept (a) a conventional VDMOSFET structure (b) FLIMOST with the induction of one floating island (c) explanation of electric field reduction mechanism

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The total on-resistance of a power VDMOSFET is expressed as sum of all the resistive components17,18 as:

ON CH ACC JFET DRIFT SUBNR R R R R R R+= + + + + + … (2)

The resistance of the N+ source (RN+) and substrate

regions (RSUB) is negligible for high voltage power MOSFETs that generally have high drift region resistance (RDRIFT). The channel resistance (RCH) and accumulation layer resistance (RACC) are determined by the conductivity of the thin surface layer induced by the gate bias. These are functions of the charge in the surface layer and electron mobility near the surface. The drift layer contributes two components to the total on-resistance. The reduction in the lower drift region resistance has already explained with the help of FLI-diode concept. The portion of the drift region that comes to the upper surface between the cells contributes a resistance (RJFET). Due to the shape of the gate electrode, the body regions of the adjacent unit cells remain isolated from each other, as a result, there is no parasitic JFET region formed. Therefore, contribution due to this region i.e. (RJFET) can be neglected for the proposed device, thereby reducing its overall resistance as indicated by Eq. (2).

3 Device Structure and Operation

Fig. 2 shows the proposed FLIMOST structure where P+ floating islands are incorporated in the conventional VDMOSFET structure in the N- drift region. These P+ floating islands are incorporated in a part of the whole conduction surface of the device, allowing the circulation of the drain current in the other part of the device. The length of these P+ islands is chosen in accordance with [Ref. 12]. The device behaves in a normal manner as the conventional VDMOSFET structure would have done in terms of current flow. The proposed device has non- symmetric source and drain (drift region). There is a long vertical, low-doped drift region which enables the device to block high voltage and the gate overlaps both the channel and the drift region so that an accumulation layer is formed in the linear operating region to enhance the conductivity. The source contact overlaps the P-body region to short-circuit the source/body junction, ensuring that the parasitic BJT is normally off and the channel region has graded doping.

With no bias on the gate, the N+ source and N+ drain are separated by P-base region and no current flows (transistor is turned-off). If a positive bias is applied to the gate, the minority carriers in the P-base (electrons) are attracted to the surface underneath the gate electrode. As the bias increases more electrons are being confined to this small space, the local minority concentration becomes larger than the hole (p) concentration and inversion occurs (meaning that the material immediately under the gate turns from p- to n-type). Now an n channel is formed in the p material right under the gate structure connecting the source to the drain; current can now flow. Like in the case of the JFET (although the physical phenomenon is different) the gate (by means of its voltage bias) controls the flow of current between the source and the drain.

In the off-state the breakdown voltage VB of this new structure is obtained by many P+-N junctions in series which reduce its value significantly due to enhanced drift region doping. This reduction in the VB is enhanced by modifying the gate electrode and using a trench gate3-6 which suppresses the punch through effect. Further, the vertical trench gate electrode in the proposed device also acts like a field plate, permitting higher drift-region doping concentration to achieve a specific breakdown voltage. According to Zeng6, the

Fig. 2—Schematic design of the proposed VDMOSFET transistor with vertical floating islands and trench gate. Structure shown represents half-cell of the device. All dimensions are as indicated in Table 1

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trench gate structure also helps to reduce the quasi-saturation effects in such type of structures.

The device simulations using PISCES-II take into account the mobility model that is dependent on electric field, impurity concentration and impact ionization at a temperature of 300 K. The device structure is mapped onto a mesh, which can be refined to follow closely the contours of the device. The various regions of the device are then defined, doping profiles and concentrations specified, and electrodes placed at the appropriate positions. PISCES-II can solve for a variety of electrical quantities like potential, electric field, carrier and charge concen-trations, currents, etc. under steady or transient bias conditions at the electrodes. The solution method used is Newton and both carrier types are considered. The effect of various physical mechanisms was included through model statement. All the post-processing and the graphical outputs are generated19 by POSTMINI graphical post-processor. The geometrical dimensions with the doping densities are listed in Table 1. It is worthwhile to mention here that PISCES-II assumes device width equal to one micron which means that all currents are given per unit device width (i.e., 1 μm). To be precise, all currents are given in A/μm.

For a device width different from 1 μm, the current will change proportionately.

4 Simulation Results and Discussion

To understand the behaviour of the proposed device and its relative comparison with the conven-tional power VDMOSFET, we started with the simulation of a 2-D device structure of (4 μm × 7 μm) dimensions respectively as shown in Fig. 2. The

Fig. 3 —PISCES simulated comparison of the electric field distribution with those obtained by first without a floating island and thereafter incorporating the floating islands one by one up to three and then with trench Gate at Vgs=5 V and Vds= 40 V

Table 1—Design parameters used for device simulation

Parameter Value

LAcc 2.3 μm Lch 1.0 μm LT 4.0 μm WT 7.0 μm tox 0.08 μm dp 1.5 μm Ln+ 0.5 μm dn+ 0.2 μm Nn- 5.0×1015 cm-3

Nn+ 5.0×1019 cm-3 Np 1.0×1017 cm-3 Np+ 5.0×1019 cm-3

Vgs=5 V & Vds=40 V

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doping densities are chosen so as to simulate a typical 100 V device. We then implanted P+ floating islands in the N- drift region one by one up to three and later modified the gate electrode to a trench gate. Fig. 3 shows the relative comparison of the electric field distribution in the drift region of the device in the on-state at Vgs=5 V and Vds=40 V and simulations reveal that there is almost three orders of magnitude

reduction in the electric field in the upper portion of the drift region which is desired. Since its value ranges much lower than the critical electric field those of the silicon devices, thus the doping of the drift region could be enhanced so as to get the same electric field thereby reducing the on-resistance of the device (Eq. 1). Figs 4(a-d) show the comparison of the potential distribution with and without trench gate

Fig. 4 (a & b)—PISCES simulated potential variations by varying the number of floating islands with and without trench gate in off state. (a) without floating islands (b) with one floating island

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by varying the number of floating islands. It is shown that the trench gate allows a more uniform potential distribution within the drift region and that area which is under the influence of trench gate has more potential drop with respect to drain whereas in the structure without trench gate more voltage is dropped across the lower part of the drift region. The trench gate here acts as a field plate which suppresses the punch through, thus enhancing the breakdown voltage of the device. Fig. 5 shows the PISCES simulated depletion region advancements in the off-state for

increasing drain voltage. Here also a similar mechanism is observed i.e. the depletion region extends more towards the lower part of the drift region as compared to the upper part due to the fact that the upper part of the drift region is under the influence of trench gate which acts as a field plate in the off state. Thus, the device can withstand higher off-state voltage i.e., more breakdown voltage. Fig. 6 shows the plot between breakdown voltage and number of floating islands with and without trench gate and it is shown that there is an approximate 15%

Fig. 4 (c & d)—PISCES simulated potential variations by varying the number of floating islands with and without trench gate in off state. (c) with two floating islands and (d) with three floating islands. The axes correspond to those shown in Fig. 2.

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increase in the breakdown voltage when the gate electrode is modified as trench gate.

5 Conclusions

A novel power VDMOSFET device structure has been discussed both in on/off states with the help of various internal electrical quantities such as electric field; potential distribution etc. based on the device simulation results obtained using PISCES-II. It is observed that the new device has much lower electric field in the drift region as compared to the conventional VDMOSFET structure. Trench gate helps suppressing the punch-through effect in the proposed device and acts like a field plate, permitting higher drift-region doping concentration to achieve a specific breakdown voltage and lower on-resistance. It is observed that for a 100 V device the breakdown voltage VB is enhanced approximately by 15% from 100-116 V. Thus, the new device is very attractive as it gives reduced RON and at the same time enhanced VB.

Acknowledgement

One of the authors (Rakesh Vaid) gratefully acknowledges Prof S K Khosa, Head, Department, Physics & Electronics, University of Jammu, Jammu for his constant encouragement throughout this work and the University Grants Commission (UGC), New

Delhi, for the award of Teacher Fellowship under the FIP scheme during the 10th plan period.

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Fig. 5—PISCES simulated depletion edges advancements for increasing drain bias in the off-state. The axes correspond to those shown in Fig. (2).

Fig. 6—Plot showing breakdown voltage variations versus number of floating islands with and without trench-gate