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7/27/2019 notesChapter 5
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Chapter 5 : Processing Unit
7/27/2019 notesChapter 5
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Chapter objectives
In this chapter you will learn about:
Execution of instructions by a processor
The functional units of a processor and how
they are interconnected
Hardware for generating control signals
Microprogrammed control
7/27/2019 notesChapter 5
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Main hardware
components of aprocessor
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Recap: Organisation
Processor
Control
Datapath
Memory Devices
Input
Output
Cache
Registers
Bus
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Fundamental Concepts
Processor (CPU): the active part of the computer,which does all the work (data manipulation and
decision-making).
Datapath: portion of the processor which contains
hardware necessary to perform all operations
required by the computer (the brawn).
Control: portion of the processor (also in
hardware) which tells the datapath what needs tobe done (the brain).
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Fetch and execute phase
Fetching an instruction and loading it into the IR is usually referred to as the
instruction fetch phase. Performing the operation specified in the
instruction constitutes the instruction execution phase.
With few exceptions, the operation specified by an instruction can be carried
out by performing one or more of the following actions:
Read the contents of a given memory location and load them into a
processor register.
Read data from one or more processor registers.
Perform an arithmetic or logic operation and place the result into aprocessor register.
Store data from a processor register into a given memory location.
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Instruction executioncycle: fetch, decode,execute.
Fetch: fetch next instruction
(using PC) from memoryinto IR.
Decode: decode theinstruction.
Execute: execute
instruction.
InstructionFetch
Instruction
Decode
Operand
Fetch
Execute
ResultStore
Next
Instruction
Fetch and execute phase cont..
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Processor: Datapath and Control
Single-bus Organization
Data line
Address line
PC
MAR
MDR
Y
Internalprocessor bus
Memorybus
Z
MUX
A
ALUB
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
::
TEMP
Instruction
decoder and
control logic
. . .
Control signalsRegister Y, Z and TEMP are
use ONLY by the processor
unit for temporary storage
during the execution of
some instructions.
Programmer cannot accessthese registers
The IR and the Instruction
decoder are integral parts of
the control circuitry in the
processing unit.
7/27/2019 notesChapter 5
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Processor: Datapath and Control
Single-bus Organization
Data line
Address line
PC
MAR
MDR
Y
Internalprocessor bus
Memorybus
Z
MUX
A
ALUB
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
::
TEMP
Instruction
decoder and
control logic
. . .
Control signalsThe data registers, ALUand the interconnecting bus
is referred to as data path
Register R0 through R(n-
1) are the processor register
These register include
General Purpose Registerand Special Purpose Register
(stack pointer, index register
and pointers)
The Register and ALU are
used for storing and
manipulating data
These are 2 option
provides for A & B input of
the ALU. Select by MUX
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Processor: Datapath and Control
Single-bus Organization
Data line
Address line
PC
MAR
MDR
Y
Internalprocessor bus
Memorybus
Z
MUX
A
ALUB
Constant 4
Select
Add
Sub
XOR
:ALUcontrollines Carry-in
IR
RO
R(n1)
::
TEMP
Instruction
decoder and
control logic
. . .
Control signals
The Multiplexer (MUX) is
used to select one of the
two inputs
If select (1) select outputof Y
If select (0)- select
Constant as input A for ALU
The constant number is
used to increment the
contents of program counter
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The execution of various instructions processor:
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Register Transfer
Y
Internalprocessor bus
Z
MUX
A
ALU
B
Constant 4
Select
Ri
X
Riin
X
Riout
Yin
X
X
Zin
Zout
X
Register to register transfer:
For each register Ri, twocontrol signals:
Riin used to load the data
on the bus into the register.
Rioutto place the registers
contents on the bus.
Example: To transfer
contents of R1 to R4:
Set R1out to 1. This places
contents of R1 on the bus. Set R4in to 1. This loads
data from the processor
bus into R4.
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Arithmetic/Logic Operation
ALU: Performs
arithmetic and logic
operations on its A and
B inputs.
To perform
R3 [R1] + [R2]:
1. R1out, Yin2. R2out, SelectY, Add, Zin
3. Zout, R3in
Y
Internalprocessor bus
Z
MUX
A
ALU
B
Constant 4
Select
Ri
X
Riin
X
Riout
Yin
X
X
Zin
Zout
X
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External Memory Bus
MDR has four control signals: MDRin, MDRout, MDRinE and MDRoutE.
Memory-bus data lines
MDR
X
MDRinE
X
MDRoutE
Internal processor bus
X
MDRin
X
MDRout
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Data line
Address line
PC
MAR
MDR
Y
Internal
processor bus
Memorybus
Z
MUX
A
ALU
B
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
:
:
TEMP
Instruction
decoder
and control
logic
. . .
Control signals
Memory-busdata lines
MDR
X
MDRinE
X
MDRoutE
Internalprocessor bus
X
MDRin
X
MDRout
External Memory Bus Datapath
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Memory-busdata lines
MDR
X
MDRinE
X
MDRoutE
Internalprocessor bus
X
MDRin
X
MDRout
Regiter to/ from Memory Transfer
Data line
Address line
PC
MAR
MDR
Y
Internal
processor bus
Memorybus
Z
MUX
A
ALU
B
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
:
:
TEMP
Instruction
decoder
and control
logic
. . .
Control signals
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Reading a Word from Memory
Move (R1), R2/* R2 [[R1]]
Instruction Sequence1. MAR [R1]
2. Start a Read operation on thememory bus
3. Wait for the MFC response fromthe memoryMFC Memory-Function-Completed Signal
4. Load MDR from the memory bus5. R2 [MDR]
Sequence of control steps:
1. R1out, MARin, Read
2. MDRinE,3. WMFC
4. MDRout,
5. R2in WMFC: Wait for arrival of MFC (Memory-
Function-Completed) signal.
Data line
Address line
PC
MAR
MDR
Y
Internalprocessorbus
Memorybus
Z
MUX
A
ALU
B
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
:
:
TEMP
Instruction
decoder
and control
logic
. . .
Controlsignals
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Data line
Address line
PC
MAR
MDR
Y
Internalprocessorbus
Memorybus
Z
MUX
A
ALU
B
Constant 4
Select
Add
Sub
XOR
:
ALUcontrollines Carry-in
IR
RO
R(n1)
:
:
TEMP
Instruction
decoder
and control
logic
. . .
Controlsignals
Storing a Word in Memory
Move R2, (R1)/* [R1]
R2
Sequence of control steps:
1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE, WMFC