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ELECTRICAL ENGINEERING AND COMPUTER SCIENCEMcCormick Northwestern UniversityRobert R. McCormick School of Engineering and Applied Science

Nostra-XTalk : A Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI

Circuits

Debasish Das, Ahmed ShebaitaYehea Ismail, Hai Zhou

EECS, NorthwesternKip Killpack

Strategic CAD Lab, Intel

April 19, 2023 (2)

Outline

• Motivation and Previous Research

• Directed Search Mechanism

• Static Timer Algorithm

• Experimental Setup

• Conclusions and future work

April 19, 2023 (3)

Coupling Dominates

• Coupling cap dominates interconnect parasitics

• Graph shows ratio of coupling cap vs. ground cap of nets Parasitics extracted from

65 nm logic block

Industrial Microprocessor design from Intel

April 19, 2023 (4)

Previous Research (Coupling Model)

• Accurate computation of MCF needed To model the effects of crosstalk

• Analytical models for MCF computation proposed Step transitions : (0,2) Sapatnekar et.al, ICCAD 2000

Ramp Models : (-1,3) Kahng et.al, DAC 2000 Chen et.al, ICCAD 2000

Exponential Models : (-1.885,3.885) Ghoneima et.al, ISCAS 2005

• Accurate models are applied to timing analysis Extending Ramp model to Timing Analysis Das et. al,

ICCD 2006

April 19, 2023 (5)

Previous Research (Timing Analysis)

• Timing Analysis with coupling iterative

• Iterative analysis with continuous models: Chen et.al ICCAD 2000

• Iterative analysis with discrete models: Sapatnekar et.al TCAD 2000, Chen et.al ICCAD 2000, Arunachalam et.al DAC 2000

• Circuit and coupling structure explored to speed up iterative analysis: Das et. al ICCD 2006

April 19, 2023 (6)

Issues in Previous Research

• Analytical models derived MCF based on Output delay windows on victim and aggressor nets

Output slew windows on victim and aggressor nets

• Correlation between input timing windows and MCF ignored

• Correlation between input slew windows and MCF ignored

• Such assumptions may lead to pessimistic MCF computation

April 19, 2023 (7)

Motivational Example

• Rise Delay Window at I1 [2,4]

• Fall Delay Window at I2 [3.5,4.5]

• Static timing assumption on slews Max victim input slew 0.6

Min aggressor input slew 0.8

• Consider 2 timing events from [2,4] (arrival time, slew) T1 = (3.9,0.6)

T2 = (4.0,0.6)

G1

G2

I1

I2

O1

O2

[2,4]

[3.5,4.5]

April 19, 2023 (8)

Motivational Example

• MCF due to T1 = 2.5

• MCF due to T2 = 2.4

• Previous approaches will consider MCF as 2.5 Update [2,4] with MCF 2.5

• Ideally Compute Delay push-out on

T1 due to MCF 2.5: T1po

Compute Delay push-out on T2 due to MCF 2.4: T2po

Maximum bound of output window

• max(T1po,T2po)

G1

G2

I1

I2

O1

O2

[2,4]

[3.5,4.5]

April 19, 2023 (9)

• Salient Features Directed Search Mechanism

• Search for input timing event

Results in worst/best delay push-out Use of input timing windows on victim and aggressor

• Accurate gate delay model employed

To take into account non-linearity of devices Iterative static timer

• Using Directed Search on a victim cluster

Collection of all aggressor nets connected to victim net

April 19, 2023 (10)

Outline

• Motivation and Previous Research

• Directed Search Approach

• Static Timer Algorithm

• Experimental Setup

• Conclusions and future work

April 19, 2023 (11)

Circuit Model

• Rise/Fall-Delay-Window : (Dil, Dih)

• Rise/Fall-Slew-Window : (sil,sih)

• Associated nodes with coupling edge : N1 and N2

NAND

NAND

NANDCC

N1

N2

N3

CCCC

N1

NANDI1

I2

Rise Arc

Fall Arc

Coupling Edge

April 19, 2023 (12)

Circuit Model for Directed Search

• Enumerate arcs on drivers Both victim and aggressor net

N1

arc1

arc2

N2

arc3

arc4

cc

Input delay (IDa) =[Dial, Dia

h]

Input slew (IDa)=[sial, sia

h]

Aggressor

Input delay (IDv)=[Divl, Div

h]

Input slew (ISv)=[sivl, siv

h]

output delay (ODv) D0v=[Dov

l, Dovh]

output slew (OSv) tvs=[sov

l, sovh]

output delay (ODa), D0a =[Doa

l, Doah]

output slew (ODa), tas =[soa

l, soah]

arc1

IDv,ISv

IDa,ISa arc3

Victim cc

arc2

IDv,ISv

IDa,ISa arc3

cc

arc1

IDv,ISv

IDa,ISa arc3

cc

arc2

IDv,ISv

IDa,ISa arc4

Victim Aggressor

ODv,OSv

ODa,OSa

ODv,OSv

ODa,OSa

ODv,OSv

ODa,OSa

ODv,OSv

ODa,OSa

April 19, 2023 (13)

Circuit Model for Directed Search (contd.)

• Enumerate arcs on drivers Both victim and aggressor net

N1

arc1

arc2

N2

arc3

arc4Aggressor

Victim

• Apply Directed Search on 4 possibilities Choose the one that results in worst delay push-out

cc

IDv,ISv

IDa,ISa arc3

cc

IDv,ISv

IDa,ISa arc3

cc

arc1

IDv,ISv

IDa,ISa arc3

cc

arc2

IDv,ISv

IDa,ISa arc4

ODv,OSv

ODa,OSa

ODv,OSv

ODv,OSv

ODa,OSa

ODv,OSv

arc1 arc2

April 19, 2023 (14)

Detailed Circuit Model for Directed Search

Input delay (IDa) =[Dial, Dia

h]

Input slew (IDa)=[sial, sia

h]

Input delay (IDv)=[Divl, Div

h]

Input slew (ISv)=[sivl, siv

h]

output delay (ODv) D0v=[Dov

l, Dovh]

output slew (OSv) tvs=[sov

l, sovh]

output delay (ODa), D0a =[Doa

l, Doah]

output slew (ODa), tas =[soa

l, soah]

Victim AggressorCoupled Circuit Equivalent Circuit

cc

arc1

IDv,ISv

IDa,ISa arc3

ODv,OSv

ODa,OSa

Cv = Cg + (Victim MCF)Cc

arc1

IDv,ISv

IDa,ISa arc3

ODv,OSv

ODa,OSa

Ca = Cg + (Aggressor MCF)Cc

April 19, 2023 (15)

Gate Delay Model

• We use logic gates from Faraday’s 90 nm cell libraries Figure (a) shows tv

s = f1(Cv,siv)

Figure (b) shows tas = f2(Ca,sia)

Figure (c) shows tvd = f3(Cv,siv)

Figure (d) shows tad = f4(Ca,sia)

• Assuming linear dependance is acceptable

• Output Waveform on victim Wv = G(Di

v + tvd, tv

s)

• Output Waveform on aggressor Wa = G(Di

a + tad, ta

s)

sivh

sivl cv

tvd

sivh

sivl

cv

tvs

siah

sial

tad

siah

sial

ca

tas

ca

(a) (b)

(c) (d)

April 19, 2023 (16)

Coupling Model (Das et. al, ICCD 2006)

• Overlap ratio (k) computation Overlap ratio is defined as the ratio of aggressor output

waveform that overlap with victim threshold voltage

• Use waveforms Wv and Wa to compute k

April 19, 2023 (17)

Aggressor

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Aggressor

(a) (b)

Aggressor

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Aggressor

(c) (d)

Aggressor

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Aggressor

(a) (b)

Aggressor

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Victim

Doa Do

a+tas

Dov Do

v+0.5tvs Do

v+tvs

t

t

Aggressor

(c) (d)

Coupling Model (Das et. al, ICCD 2006)• Use waveforms Wv and Wa to compute k

121 kt

tsv

sa

sv

sa

t

t1

sv

sa

t

t1

k

5.01

(a) Victim MCF = 1±2k, Aggressor MCF =

(b) Victim MCF = 1±2k, Aggressor MCF =

(c) Victim MCF = 1±2k, Aggressor MCF =

(d) Victim MCF = 1±2k, Aggressor MCF =

April 19, 2023 (18)

Worst Case Delay Computation

• Linearly span the domain of k

• Victim capacitance Cv = Cg + (1+2k)Cc

Compute tvd and tv

s

• Aggressor capacitance and slew are given by

sivh

sivl

cv

tvs

sivh

sivl cv

tvd

cg+(1+2k)cc cg+(1+2k)cc

April 19, 2023 (19)

Worst Case Delay Computation (contd.)

• Using tas we obtain aggressor capacitance [c1,c2]

• tad is calculated using c1 and c2

ca

siah

sial

tas

siah

sial

ca

tad

c1 c2 c1 c2

• Worst case delay computation produces

• Construct Feasible set F

• Choose one element from F which has worst tvd

April 19, 2023 (20)

Outline

• Motivation and Previous Research

• Directed Search Approach

• Static Timer Algorithm

• Experimental Setup

• Conclusions and future work

April 19, 2023 (21)

Practical Application of Directed Search

• Victim net coupled with more than one aggressors

• We model our circuit as directed graph G = (V,E) V : Gates in combinational circuit

E : F U C where F : Fan-out Edges C : Coupling Edges

• We give the following definition

V is the victim node while Ai are its aggressors

April 19, 2023 (22)

Worst Case Coupling Capacitance as fix-points

• We define a switching point as an ordered pair of delay and slew

• Following set gives all possible switching points in a k-cluster

• Set formed by pairs of switching points (si,sj) is a totally ordered set

• Directed Search between an victim and aggressor is order preserving transformation

• Fix-point iteration to get worst case caps

April 19, 2023 (23)

Iterative Static Timer Algorithm

April 19, 2023 (24)

Outline

• Motivation and Previous Research

• Directed Search Approach

• Static Timer Algorithm

• Experimental Setup

• Conclusions and future work

April 19, 2023 (25)

Circuit Modeling

• Experiments done on ISCAS85 benchmarks

• Circuit modeled as DAG (Timing Graph)

• Nodes in Timing Graph are Gates

• Edges represent interconnect

• Nodes are mapped to ASIC logic gates Faraday 90 nm experimental tech library used

Delay tables are used : f( output load, input slew )

• Coupling graph generation Extracted coupling capacitance values are used

Coupling graph is superimposed on timing graph

Each net is assumed to couple with 6 aggressors

April 19, 2023 (26)

Accuracy Enhancement Results

• IST-(0,1,2) : Iterative static timer MCFs 0,1,2 (Sapatnekar et. al)

• IST-DS : Proposed Iterative static timer

• RT : Runtime TA : Cell Table Accesses

• GA : Accuracy Gain, GT : Gain in Cell Table Accesses

April 19, 2023 (27)

Accuracy Enhancement Results

• Hold time given by IST-(0,1,2) can be non-conservative

• Accuracy Gain by proposed algorithm Average : 25.59% Highest gain C880 : 45.5%

• Decrease in Cell Delay Table Lookup by proposed algorithm Average : 40.1% Maximum decrease c6288 : 64.8%

• Decrease in cell delay is not reflected in runtime Search has high complexity Search should be used judiciously

April 19, 2023 (28)

Outline

• Motivation and Previous Research

• Directed Search Approach

• Static Timer Algorithm

• Experimental Setup

• Conclusions and future work

April 19, 2023 (29)

Conclusions and future work

• We present Nostra-XTalk Directed Search Approach for accurate timing analysis

Iterative static timer using directed search

• Directed Search is time consuming

• Directed Search should be selectively applied

• Can be used in a coupling partitioning based timer As proposed by Das et. al ICCD 2006

Directed Search can be applied on local clusters

• Future Directions Devise algorithms

• Selectively apply Directed Search

• Accurate as well as efficient analysis