No Slide TitleMetal programmable I/O cells zHSTL, LVCMOS, PCML, LVDS (622 Mbps), SSTL-2, PCI-66, PCI-X Specifically designed libraries for high density and performance Pre-diffused

All Rights Reserved.© Fujitsu Limited 2003

AccelArrayTM


Fujitsu Microelectronics Europe - www.fme.fujitsu.com, April 2003

ASIC Heritage

Process technology

0.11µm now, 90nm infinal stage of development

Internal packaging development

FCBGA, EBGA, FBGA,QFP…

Application-specific HSIO and IPWareTM

SERDES, XAUI, 10Gbpsmacros

ARM7/9, ARC, DSP, ..

Storage & storage

networking

Consumer electronics

Communications

Industrial

High-performance ASIC

Embedded arrayin 0.18µm

Leading global ASIC supplier



AccelArray Market Opportunity

Expands Fujitsu’s capability in mid-volume marketAlternative to ASSPs, FPGA and cell-based ASICs

Development COST TTM

Cell-based ASIC

AccelArrayTM

FPGA

Unit cost / Area / Power



AccelArray Creates Inflection Point…

0

2

4

6

8

1995 1997 2000 2002 20030

1,000

2,000Process (? ) 2.0 … 0.8 0.6 0.35 0.25 0.18 0.13 0.10

Single Maskcost ($K) 1.5 1.5 2.5 4.5 7.5 12 40 60

# of Masks 12 12 12 16 20 26 30 34

Mask Setcost ($K) 18 18 30 72 150 312 1,000 2,000

ASIC development and mfg. costs AccelArray reduces total cost of ownership (TCO) for 0.11µm

Time-to-market (TTM) advantage• Cost of lost opportunity

Lower design services and mask cost

Lower overall manufacturing costs for mid volume

• Shorter lead time, better inventory management



Overview AccelArray Features

Pre-fabricated platforms up to metalisationCustomer logic is implemented with 3 metal mask layers

Pre-diffused memory, APLLs and logicEmbedded Flip Flops to reduce powerMetal programmable I/O cells

HSTL, LVCMOS, PCML, LVDS (622 Mbps), SSTL-2, PCI-66, PCI-XSpecifically designed libraries for high density and performancePre-diffused and soft IPs support a wide range of applicationsReduced TCO: TTM for 0.11µm is weeks not months

Architecture enables shortest physical layout design time in 0.11µm• Back-end physical design time: 2 - 4 weeks• Re-spins: 1 week

Power dissipation is half that of similar solutionsSimilar performance to cell-based ASICsNRE cost: 60-70% less than cell-based ASICs in 0.11µm tech.3x performance of high-end FPGAs at 10% of their cost



TTM Advantage: Physical Design TasksArchitecture reduces tedious physical design tasks

Design review

0.11µmCell-based ASIC

Physicaldesign

Design review

Tape out toprototypes

Physical designtrial netlist

layout

Physical designfinal netlist layout

Tape out to prototypesmanufacturing cycle

0.11µmAccelArray

ASIC typical design cyclePhysical design: 16 weeksTape out to prototype: 12 weeks

AccelArray typical design cyclePhysical design: 2 - 4 weeksTape out to prototype: 2 - 4 weeks

AccelArray



TTM Advantage: Short Physical Design TimeASIC physical design

DFT insertion

Power mesh

Clock tree synthesis

I/O timingclosure

Cross talk analysis

Internal timing closure

AccelArray physical design

AccelArray

Cross talkanalysis

I/O timing closure

Internal timingclosure



TTM Advantage: Short Physical Design Time

Architecture solves design challenges that similar solutions overlook

Simplified internal timing and I/O timing closurePre-defined global clock trees and local peripheral clocksEmbedded dedicated cells for each I/O buffer

Solved signal integrity issuesImplemented techniques to avoid XtalkIR drop free solution

Simplified DFT All test-related components and connections are built in



Design Flow

Design acceptance check

Timingconstraint

NetlistSLIF

Logic design/synthesis

Design hand-off check list

Frame selection

Package pinassignment tool

FujitsuCustomer

Layout DFT insertion

Power,STA results

Formal verification

Power calculation

Tape-out

Scan chain info. Netlist-DFTAccelaBuilder

AccelaBuilder Formal verificationTiming verification

SDF ATPGSTA

Tested prototypes



AccelArray Key Differentiators

Pre-structured clock tree simplifies back-end physical design cycleEmbedded Flip Flops reduce cell size and power consumption Embedded Register Files (RF) aid in clock synchronisation, simplifying timing closureSupport for the highest number of DDR interface in all slots

Memory interface, chip-to-chip interface and physical interface Support for the largest variety of interfaces

DDR-SDRAM, FCRAM, QDR-SRAM, XGMII



Mega Platforms

Introducing ‘Mega’ platforms today

I/O cell count472 to 1128

Embedded memory860k to 4.6 Mbits SRAM

Available AccelArray gate counts

512k to 3842kAdditional embedded Flip Flops

23k to 173kPackages: Ball Grid Array 625-1681Soft IPs from Fujitsu’s IPWare™ libraries



Target Vertical Markets

Mid-volume, 0.11µm performance

Satellites Aerospace

Networking

Medical imagingStorage networking

Industrial automation Telecom

Target markets



Giga Platforms

Stage II of AccelArray programme (Q4CY03)Targeted at high-performance applications requiring high-speed serial interfaces

Telecoms, Networking, StorageUnique programmable ‘Universal PHY’ to support wide range of interface types



Giga Platforms

Universal-PHY target interfaces

Voltage I/O Cell Kind Data Rate (bps)1.2v/2.5v SFI4 622M - 800M1.2v/2.5v Hyper Transport 400M, 600M, 800M1.2v/2.5v RapidIO 500M, 700M1.2v/2.5v SPI4P2 622M - 800M1.2v/2.5v XAUI 3.125Gbps1.2v/2.5v FibreChannel 1.0Gbps, 2.0Gbps1.2v/2.5v RapidIO 1.25Gbps, 2.5Gbps, 3.125Gbps1.2v/2.5v SFI4P2 2.5Gbps - 3.125Gbps1.2v/2.5v Serial ATA 1.5Gbps, 3Gbps1.2v/2.5v PCI express 2.5G

Embedded clock tree

High-speed interface macro cells



AccelArray Roadmap

Tech

nolo

gy N

ode

130n

mTe

chno

logy

Nod

e

90nm

Gigaframeplatforms

General Purpose(Mega)

Platforms

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 121 2 3 4 5 6 7 8 9 10 11 12

2003 2004



AccelArray Value Advantage

TTM is weeks not months Architecture offers shortest timing closure and solves signal integrity issues in 0.11µm

Power dissipation is 2x better than similar solutionsEmbedded Flip Flops significantly reduce power dissipationSpecifically developed libraries offer the best solution for gate density and lower power dissipation Clock tree architecture helps reduce power drastically

Similar performance to cell-based ASICsEmbedded clock buffer and Flip Flops offer the most efficient solution for speed and density

NRE cost: 60~70% less than equivalent cell-based ASIC in 0.11µm technologySignificantly lower overall cost than equivalent complex FPGA



Documents

No Slide TitleMetal programmable I/O cells zHSTL, LVCMOS, PCML, LVDS (622 Mbps), SSTL-2, PCI-66, PCI-X Specifically designed libraries for high density and performance Pre-diffused