NIL Template : progress and challengescnt.canon.com/wp-content/uploads/2014/11/SPIE-2013-DNP-template-statusRE.pdfSPIE Advanced Lithography 2013. SPIE Advanced Lithography 2013. 1

© 2011 Dai Nippon Printing Co.,Ltd. All Rights Reserved.

NIL Template : progress and challenges

Naoya Hayashi

Electronic Device OperationsDai Nippon Printing Co., Ltd.

SPIE Advanced Lithography 2013SPIE Advanced Lithography 2013 11© 2011 Dai Nippon Printing Co.,Ltd. All Rights Reserved.1

Contents

1. IntroductionLithography technology trendParadigm shift in NGLsNIL applications

2. NIL template technology progressResolution, CD, IP, and defectivity controlInspection infrastructure

3. Next challenges for 1x nm era4. Summary


ITRS Lithography Solutions ~ DRAM/MPU2012 Update

Figure LITH3A DRAM and MPU Potential Solutions

First Year of IC Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

DRAM ½ pitch (nm) (contacted) 36 32 28 25 23 20.0 17.9 15.9 14.2 12.6 11.3 10.0 8.9 8.0 7.1 6.3

MPU/ASIC Metal 1 1/2 pitch (nm) 38 32 27 24 21 18.9 16.9 15.0 13.4 11.9 10.6 9.5 8.4 7.5 7.5 7.5

45 193nm Imm

32 193 nm DP

22 EUV193nm MPML2 (MPU)

16 EUV193nm MPML2DSA + LithoImprint

11 EUV higher NA / EUV + DPML2DSA + LithoEUV (new wavelength)ImprintInnovation

Narrow Options

Narrow Options

Narrow Options

MPU / DRAM time line

193nm+MP and EUV will lead scaling down to 16nmHP. Emerging technologies will be the candidate beyond then.


ITRS Lithography Solutions ~ Flash2012 Update

Figure LITH3B Flash Potential Solutions

First Year of IC Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

Flash ½ Pitch (nm) (un-contacted Poly)(f) 22 20 18 17 15 14 13 12 11 10.0 8.9 8.0 8.0 8.0 8.0 8.0

32 193 nm DP

22 193 nm DP

16 193nm MPEUVImprint

11 EUV higher NA / EUV + DP193nm MPDSA + LithoEUV (new wavelength)ImprintInnovation

Narrow Options

Narrow Options

NAND Flash Time Line

193nm+MP and EUV will lead scaling down to 16nmHP. Emerging technologies will be the candidate beyond then.


Paradigm shift in NGLsComplexity & Difficulty Color Map

Optical extension with MP is complex and costly

Design

EDA

Mask

Exposure tool(Scanner)

Process

Back -end

Optical Extension

(Immersion+MP)Litho-Friendly Design

Data Split + Complex OPC + Cutting

Overlay AccuracyCDU Accuracy

Alignment AccuracyThroughput

Complex Process FlowProcess tool capacity


Footprint comparison between Optical extension and EUV

Etch :33

CVD :21

Etch :10

CVD :10

Scanner/Track: 6 Scanner/Track

: 4


EUVL needs complex mask, scanner, and dedicated infrastructures.

Design

EDA

Mask


Process

Back -end

Optical Extention

(Immersion) EUVL

Design

EDA

Mask

Exposure tool(EUV Scanner)

Process

Back -end

Flare Correction

Complex StructureActinic Tools

Complex Vacuum ToolThroughput

EUV Resist



Mask Blank Structures Comparison

AR-TaN

CrN / -

Si / Ru

Mo-Si(40 pairs)

LTEM

Material/Layer

CrN

absorber layer

buffer layer

capping layer

reflective layer

substrate

back side film

>85 layers>85 layers8 materials8 materials

EUV mask substrate complexity

absorber layer/ phase-shift layer

~3 layers~3 layers3 materials3 materials

AR-Cr,MoSi

/ MoSiX

Qz substrate

EUV mask needs very different defect control and

metrology/inspection tools.

EUV ArF


NIL is simple, but needs 1x nm feature and defect control

Design

EDA

Mask


Process

Back -end

Optical Extention

(Immersion) NIL

Design

EDA

Template

Exposure tool(Imprinter)

Process

Back -end

EUVL

Design

EDA

Mask


Process

Back -end

1x FeaturesDefect Control

Overlay AccuracyThroughput

Defect Control



Comparison between optical and imprint lithography

Far Field Methods(e.g. KrF, ArF, EUV)Spatial resolution is

limited by diffraction.

Optical lithographyNear Field (Contact) Methods

Spatial resolution is notlimited by diffraction.

Nano-imprint lithography (NIL)

NIL template

X4 X1

Optical mask

design

NIL adopts 1X masks

OPC pattern is unnecessary.

Further resolution capability

in patterning process is needed.


ML2 needs high throughput, high accuracy EB tool

Design

EDA

Mask


Process

Back -end

Optical Extention

(Immersion) NIL

Design

EDA

Template


Process

Back -end

EUVL

Design

EDA

Mask


Process

Back -end

ML2

Design

EDA

No Mask

Exposure tool(EB Writer)

Process

Back -end

PECCompatibility

ThroughputOverlay

EB Resist



DSA may relax the lithography requirements with critical process

Design

EDA

Mask


Process

Back -end

Optical Extention

(Immersion) NIL

Design

EDA

Template


Process

Back -end

EUVL

Design

EDA

Mask


Process

Back -end

ML2

Design

EDA

No Mask

Exposure tool(EB Writer)

Process

Back -end

DSA

Back -end

Design

EDA

Mask


Process

DSA-Friendly Design

Data Split + Cutting

CDU AccuracyLER/LWR

Alignment Accuracy

Complex Process Control



Contents





DNP’s original font “Shu-ei-tai” NIL template with Qz

“Typography” with metal font

Printing meets Nanotechnology

hp22nm


Imprint Application in DNP

Hologram moldsApplications

min pixel 125nm

8Level

Mold pattern


J-FIL fluid dispenser

Planarization layerSubstrateStep 1: Dispense drops

Step 2: Lower template and fill pattern

Step 3: Polymerize J-FIL fluid with UV exposure

Step 4: Separate template from substrate

Template

Template

Substrate

Substrate

Substrate

Template Step & Repeat or

Whole Wafer PrintingPlanarization layer

Planarization layer

Planarization layer

Quartz template, coated with release layer

Field-to-field dispense & imprintingLow pressure (< 0.5 psi) processRoom temperature operationNo contact to wafer

Nanoimprint Process in CMOS：J-FIL @MII


Recent NIL applications

Current solution for the industry 450mm initiative


NIL Applications other than CMOS

17

Semiconductor

Flat Panel Displays

Hard Disk Drives

Biotech –DNA Sequencing

Biotech –Nano‐Pharmaceutical

Energy – Lighting

Energy – Solar

Energy – Batteries

Wire Grid Polarizer

Nanoparticle Delivery

MARKET APPLICATION MARKET APPLICATION

Memory Array

Bit Patterned Media

Flowcell Nano-Wells

Photonic Crystals

3D amorphous Si

Si Nano-anodes

Lowest Cost nanopatterning— Lower capex than optical— Near zero material waste

› Drop on demand resist jetting

— Compact footprint

Extensible Technology— Proven <15nm applications— Flexible and scalable technology— Large substrate sizes possible

450mm siliconflexible filmsflat panel glass

Key J-FIL Benefits

Wednesday February 27


Contents





Resolution in NIL Template～Small Field

Resolution with Mask Writer (50kV EB)

Resist images

hp14nmhp16nm hp15nm hp13nm

Resolution with 100kV EB Writer

h p 2 2 n m h p 2 0 n mh p 2 4 n mh p 2 6 n m


Resolution in NIL Template～Full Field

30nmHP 28nmHP 26nmHP

Full Field = 26 x 33 mm @Template


Cross Section Measurement by AFM


Critical Dimension Control

Avg. ：24.57Range： 2.583σ : 1.39

Avg. ：24.38Range： 1.543σ : 1.01

Total Vertical pattern

units [nm]


Master #1 Master #2 Mater #3

Master #1 Master #2 Master #3X Y X Y X Y

3σ[nm] 2.76 2.60 2.83 3.00 2.47 2.23 Min[nm] -3.21 -2.07 -2.47 -1.95 -1.78 -1.79 Max[nm] 2.54 2.42 1.87 1.62 2.07 2.23

Image Placement


Most of critical defects, open, short (red dot line)& CD, edge (blue dot line), were detected on 24nm L&S features.

Defect inspection capability with EBI


Master defect reduction

1

10

100

1000

10000

100000

1000000

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

2010 2011

Defe

ct density

/ｃｍ

２

After repair

Achieved <10w/o repair

Defect

*EB inspectionUp to 20nm

Achieved zero defect by adopting repair technology


Master template defect repair

E-beam based repair technology is applied


Defect on master template After repair

Line short defect

Defect printability after repair

Imprinted image onreplica template

Repaired pattern is successfully transferred on replica


PERFECTATM MR5000

Template Replication Tool


Cross sectional view of replica template after Qz etching and Cr removal.

Replication Process


Image Placement


EB inspectionUp to 20nm*

Replica Defect Reduction

1

10

100

1000

10000

100000

1000000

8 9 10 11 12 Q1 Q2 Q3 Q4

2011 2012

Achieved <5

Defect on replica template has been improved down to 5/cm2.


Attribute Target StatusMaster

CDU 2 nm 1.0nmImage Placement 3 nm 3 nm

Defect Density 0.1/cm2 0/cm2 w/repair

ReplicaCDU 2 nm 1.9nm

Image Placement 4 nm 5 nmDefect Density 1/cm2 <5/cm2

NIL Template Readiness

Image placement and defectivity still need to beimproved and stabilized.


Imprint Electrical Yield: Excellent Progress

1 10 100 1000 10000

100%

80%

60%

40%

20%

0%

Line Length (mm)

Yiel

d

2010

2009

2011

26nm HP

J-FIL

Electrical Defect Testing: Yield vs. Line Length

• Excellent progress in electrical yield- >90% at 10 meters

2012


NIL Readiness


Contents





Top down SEM

SEM images

100nm70nm50nm24nmhp 18nm16nm 20nm15nm

Top down SEM

SEM images

100nm70nm50nm24nmhp 18nm16nm 20nm15nm

CDerror(nm)

-5-4-3-2-1012345

0 20 40 60 80 100 120

hp(nm)

CD

err

or(

nm

)

CDerror(nm)

- 15nm etched Qz resolution is confirmed with Gaussian E-beam tool- Confirmed linearity within +/-1nm @ 15-100nm- Patterning throughput & LER will be issues

-15nmHP Etched Qz pattern was performed by “double patterning” method- Further tool / process optimization needed

Challenge for 1x nm ~ Etched Qz resolution


Replicated pattern features

Replicated resist imageTEM image of

Master template

15nm L&S is successfully transferred on replica template.


SummaryNIL is one of the NGL candidates to scale the device feature down to 1x nm and beyond.Compared with other lithography options, such as optical lithography extension and EUV lithography, NIL will be much less complex and cost effective. NIL will be adopted on the products which has certain level of defect redundancy, such as the storage devices and non-CMOS products.NIL template technologies have been developed to achieve the target specifications, such as CD and IP, but still has the tough challenge in defectivity control mostly in replication.1x nm pattern fabrication on template is developed with multiple paths, and will transfer to production stage.


Thank you!

Documents

NIL Template : progress and challengescnt.canon.com/wp-content/uploads/2014/11/SPIE-2013-DNP-template-statusRE.pdfSPIE Advanced Lithography 2013. SPIE Advanced Lithography 2013. 1