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Next Generation Integrated Circuits • 300 mm wafers • Copper metallization • Low-K dielectric under interconnect lines • High-K dielectric under gate • Silicon-on-insulator (SOI) • Strained silicon • New gate metals • Dual-core CPU chips

Next Generation Integrated Circuits

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Next Generation Integrated Circuits. 300 mm wafers Copper metallization Low-K dielectric under interconnect lines High-K dielectric under gate Silicon-on-insulator (SOI) Strained silicon New gate metals Dual-core CPU chips. Next Generation Integrated Circuits. 300 mm wafers - PowerPoint PPT Presentation

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Page 1: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 2: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 3: Next Generation Integrated Circuits

Copper Metallization – Low-K Dielectric

Page 4: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 5: Next Generation Integrated Circuits

High-K Gate Dielectric

• Reduced fringing of gate electric field – better switching control, less leakage current

• Reduced tunneling leakage current with thin oxides

• Si3N4, ZrO2, HfO2

Page 6: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 7: Next Generation Integrated Circuits

Silicon-On-Insulator

• No p-n junction for electrical isolation

• Reduced inter-device coupling

• Reduced parasitic capacitance

• No deep diffusion required for isolation - less fabrication time, closer device packing

Page 8: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 9: Next Generation Integrated Circuits

Strained Silicon

• Enhanced carrier mobility – compensates for increased ionized impurity scattering in thin, heavily-doped layers

Page 10: Next Generation Integrated Circuits

Next Generation Integrated Circuits

• 300 mm wafers• Copper metallization• Low-K dielectric under interconnect lines• High-K dielectric under gate• Silicon-on-insulator (SOI)• Strained silicon• New gate metals• Dual-core CPU chips

Page 11: Next Generation Integrated Circuits

New Generation ICs at Intel

http://www.intel.com/technology/silicon/index.htm

http://www.intel.com/technology/silicon/research.htm?iid=tech_sil+rd

Main Page

Reports and Publications

Page 12: Next Generation Integrated Circuits

New Generation ICs at AMD

http://www.thinkcp.com/AMD/roadmap.html

Processor Cores Roadmap

Main Page

http://www.amd.com/us-en/

Page 14: Next Generation Integrated Circuits

New Generation ICs at IBM

http://www.research.ibm.com/

http://www.ibm.com/search/?en=utf&v=11&lang=en&cc=&lv=w&q=%2BNanofabrication%20%2Burl.all:research.ibm.com

Main Page

Reports and Publications

http://www-916.ibm.com/press/prnews.nsf/jan/0C17FDCBF4B76CE185256C6F0064206D

Nanofabrication